CN217114390U

CN217114390U - Integrated clamping diode structure

Info

Publication number: CN217114390U
Application number: CN202220238726.9U
Authority: CN
Inventors: 吕宇强; 鞠建宏
Original assignee: Jiangsu Dior Microelectronics Co ltd
Current assignee: Jiangsu Dior Microelectronics Co ltd
Priority date: 2022-01-28
Filing date: 2022-01-28
Publication date: 2022-08-02
Anticipated expiration: 2032-01-28

Abstract

The utility model discloses an integrated clamping diode structure, include: the chip comprises a chip body, a deep N well layer, an N-type heavily doped buried layer and a P-type heavily doped layer; the deep N well layer, the N-type heavily doped buried layer and the P-type heavily doped layer are all sequentially arranged inside the chip body; the utility model discloses a breakdown voltage and the clamp voltage that set up this clamp protection device for do not influence the normal work of surface function circuit when the chip normally works, only when the excessive pressure surpasses the certain threshold value of maximum operating voltage and the clamp triggers, form ESD and EOS protection, thereby solved among the prior art single chip integrated ESD and EOS protection can the extra area's of greatly increased chip technical problem.

Description

Integrated clamping diode structure

Technical Field

The utility model relates to an integrated circuit technical field, more specifically the utility model relates to an integrated clamp diode structure that says so.

Background

At present, electrostatic discharge (ESD) and Electrical Overstress (EOS) are the main causes of failure of an integrated circuit chip, ESD and EOS phenomena are short-time overload, and when a chip pin is impacted by peak voltage or peak current in a short time, when energy exceeds a maximum rated value, the function or reliability of the chip is damaged or even fails.

However, in the main method for ESD and EOS protection of a chip, a discrete ESD/surge protection device, such as a transient voltage suppressing diode (TVS), is added outside a chip on a system circuit board, and then protection is performed by combining with a chip-level ESD path of the chip itself, and the external discrete protection device is a core clamp protection device for implementing ESD/EOS protection and is required to have strong clamping voltage and current discharge capabilities. In the prior art, one kind of idea is to additionally add an ESD and EOS detection circuit and a silicon surface power device such as a high voltage MOS transistor in a circuit of a chip, and control the on/off of the clamp protection MOS power transistor by using a detection circuit module to realize voltage clamping and discharge the pulse large current of the system ESD and EOS, thereby protecting the pins of the integrated circuit. The grade of the maximum current of the voltage clamp is in direct proportion to the area of the clamp protection MOS power tube, and the high-current discharge capacity required by higher ESD and EOS protection grade is realized, the clamp protection MOS power tube can only be realized by increasing the size, and in addition, the ESD and EOS detection circuit occupy a large amount of chip area, so that the area efficiency of the chip effective function module is reduced, and the chip cost is greatly increased.

Therefore, how to provide a clamp protection diode structure capable of solving the above problems is a problem that needs to be solved by those skilled in the art.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model provides an integrated clamp diode structure, breakdown voltage and clamp voltage through setting up this clamp protection device for do not influence the normal work of surface function circuit when the chip normally works, and when only triggering when the excessive pressure exceedes the certain threshold value of maximum operating voltage and the clamp, form ESD and EOS protection, thereby solved the technical problem that single chip integration ESD and EOS protection can the extra area of greatly increased chip among the prior art.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

an integrated clamp diode structure comprising: the chip comprises a chip body, a deep N well layer, an N-type heavily doped buried layer and a P-type heavily doped silicon substrate layer;

the deep N well layer, the N-type heavily doped buried layer and the P-type heavily doped silicon substrate layer are all sequentially arranged inside the chip body.

Preferably, the chip body is internally provided with: the deep N well layer is positioned in the lightly doped silicon epitaxial layer, the N type heavily doped buried layer is positioned between the lightly doped silicon epitaxial layer and the buffer epitaxial layer, and the P type heavily doped layer is positioned in the buffer epitaxial layer.

Preferably, the method further comprises the following steps: the back gold end is arranged on one side of the outer portion of the chip body.

Preferably, the method further comprises the following steps: the chip comprises a first device, a second device, a third device and a fourth device, wherein the first device, the second device, the third device and the fourth device are all arranged on one side of the outside of a chip body.

Preferably, the method further comprises the following steps: a CMOS device disposed inside the fourth device.

Preferably, the method further comprises the following steps: and the polysilicon resistors are arranged in the third device and the fourth device.

According to the above technical scheme, compare with prior art, the utility model discloses an integrated clamp diode structure, need not be like prior art through increasing extra silicon surface device, and then increase the mode of chip area and realize, this patent is through increasing injection P type heavily doped technology level, at the isolation of chip functional module itself and the internal parasitic clamp protection diode that forms of silicon between the substrate, be particularly suitable for in the great chip of area of chip self circuit isolation module, this parasitic surge clamp diode more can realize not occupying surface area and provide very considerable system ESD and EOS surge protection function. The utility model provides a technical scheme only through increasing a technology level, has formed the internal surge protection diode of placing chip self circuit module's isolation below in, has both saved the outside transient voltage suppression diode of chip, has saved the system board area, does not increase chip self area again, is a very high efficiency, and the innovative scheme of the protection of integrating of low-cost solution ESD and EOS is very suitable for being applied to present mobile terminal product.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic top view of an integrated clamp diode structure according to the present invention;

fig. 2 is a cross-sectional view of an integrated clamp diode structure according to the present invention;

fig. 3 is a schematic top view of a conventional structure according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1-2, an embodiment of the present invention discloses an integrated clamping diode structure, including: the chip comprises a chip body 1, a deep N well layer 9, an N type heavily doped buried layer 10 and a P type heavily doped silicon substrate layer 15;

the deep N well layer 9, the N-type heavily doped buried layer 10 and the P-type heavily doped silicon substrate layer 15 are sequentially arranged inside the chip body 1.

In a specific embodiment, the chip body 1 has disposed therein in sequence: the deep N well layer 9 is positioned in the lightly doped silicon epitaxial layer 11, the N type heavily doped buried layer 10 is positioned between the lightly doped silicon epitaxial layer 11 and the buffer epitaxial layer 14, and the P type heavily doped layer 16 is positioned in the buffer epitaxial layer 14.

In a specific embodiment, the method further comprises the following steps: the back gold terminal 17, the back gold terminal 17 is disposed at one side of the chip body 1.

Specifically, a PN junction formed by the N-type heavily doped buried layer 10 and the P-type heavily doped layer 16 below the N-type heavily doped buried layer is a clamping leakage ESD and EOS protection diode, the anode is led out from the back gold end 17 of the P-type heavily doped silicon substrate layer 15, and the cathode is directly led out to the surface from the deep N-well layer 9 above the N-type heavily doped buried layer 10.

In a specific embodiment, the method further comprises the following steps: the chip comprises a first device 3, a second device 4, a third device 5 and a fourth device 6, wherein the first device 3, the second device 4, the third device 5 and the fourth device 6 are all arranged on one side of the outer portion of the chip body 1.

Specifically, the first device 3, the second device 4, the third device 5 and the fourth device 6 represent conventional circuit blocks that do not need to be implemented in isolation.

The dotted line parts 8 are arranged in the first device 3, the third device 5 and the fourth device 6, and indicate schematic structures of the added P-type heavily doped layer 16 in the first device 3, the third device 5 and the fourth device 6 which are isolated by the N-type buried layer, a P-type heavily doped region graph shown by the dotted line 8 can be formed in the N-type buried layer graph, the boundary of a PN junction between the P-type heavily doped layer and the N-type buried layer is positioned in the boundary of the PN junction between the N-type buried layer and the P-type substrate, so that the influence of reduction of breakdown voltage between the P-type heavily doped layer and the N-type buried layer due to curvature of the PN junction boundary is eliminated, and the stable breakdown voltage of the clamping diode close to a plane junction is obtained. Meanwhile, 3 clamping diodes formed in a plurality of functional modules, such as those labeled 3, 5 and 6 in fig. 2, can be connected to the same protected pin to form clamping diodes connected in parallel to increase the bleeder current capability.

In a specific embodiment, the method further comprises the following steps: and the CMOS device 12, wherein the CMOS device 12 is arranged in the fourth device 6.

In a specific embodiment, the method further comprises the following steps: and a polysilicon resistor 13, wherein the polysilicon resistors 13 are disposed inside the third device 5 and the fourth device 6.

Further, the embodiment of the present invention provides a method for forming an integrated clamp diode structure, including:

s1: forming a deep N-well layer 9 in the chip body 1, sequentially adding an N-type heavily doped buried layer 10 and a P-type heavily doped silicon substrate layer 15 below the deep N-well layer 9, and forming a PN junction by the N-type heavily doped buried layer 10 and the P-type heavily doped layer 16;

s2: and forming a back gold end 17 on one side of the outside of the chip body 1 to lead out an anode, and leading out a cathode from the deep N well layer 9 to finish the preparation of the integrated clamping diode structure.

Referring to fig. 3, it can be seen that the chip area included in label 2 in fig. 3 is increased to realize a surge bleed circuit module represented by a silicon surface surge bleed tube included between a-a 'and a' indicated by a cross section, but the present invention can place ESD clamp protection in a body below the silicon surface of a chip, and is implemented below a functional circuit and isolated from a surface device by an N-type buried layer, so that the normal operation of the surface functional circuit is not affected when the chip normally operates, and the ESD and EOS discharge transient large current to protect the pin of the chip, thereby reducing the volume of the chip.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated clamp diode structure, comprising: the chip comprises a chip body (1), a deep N well layer (9), an N type heavily doped buried layer (10) and a P type heavily doped silicon substrate layer (15);

the deep N well layer (9), the N-type heavily doped buried layer (10) and the P-type heavily doped silicon substrate layer (15) are sequentially arranged inside the chip body (1).

2. An integrated clamp diode structure according to claim 1, characterized in that the inside of the chip body (1) is provided with in sequence: the epitaxial layer structure comprises a lightly doped silicon epitaxial layer (11), a P-type heavily doped layer (16) and a buffer epitaxial layer (14), wherein the deep N well layer (9) is located in the lightly doped silicon epitaxial layer (11), the N-type heavily doped buried layer (10) is located between the lightly doped silicon epitaxial layer (11) and the buffer epitaxial layer (14), and the P-type heavily doped layer (16) is located in the buffer epitaxial layer (14).

3. The integrated clamp diode structure of claim 1, further comprising: the back gold end (17), back gold end (17) set up in one side of chip body (1) outside.

4. An integrated clamp diode structure according to claim 3, further comprising: the chip comprises a first device (3), a second device (4), a third device (5) and a fourth device (6), wherein the first device (3), the second device (4), the third device (5) and the fourth device (6) are arranged on one side of the outside of the chip body (1).

5. The integrated clamp diode structure of claim 4, further comprising: a CMOS device (12), the CMOS device (12) being disposed inside the fourth device (6).

6. The integrated clamp diode structure of claim 4, further comprising: and a plurality of polysilicon resistors (13), wherein the plurality of polysilicon resistors (13) are provided inside the third device (5) and the fourth device (6).