CN111046623B - Layout design method of ESD diode - Google Patents
Layout design method of ESD diode Download PDFInfo
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- CN111046623B CN111046623B CN201911071138.XA CN201911071138A CN111046623B CN 111046623 B CN111046623 B CN 111046623B CN 201911071138 A CN201911071138 A CN 201911071138A CN 111046623 B CN111046623 B CN 111046623B
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000002347 injection Methods 0.000 claims abstract description 16
- 239000007924 injection Substances 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000002513 implantation Methods 0.000 claims description 6
- 238000007667 floating Methods 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a layout design method of an ESD diode, which comprises the following steps: designing a DNW on the P-type substrate, and designing an NW ring around the DNW to be connected with the DNW to form a large DNW closed area; designing NW and PW in the DNW closed region, designing a PW on each side of the NW, designing a P+ injection region on the NW, and designing an N+ injection region on the PW; the N+ injection region and the P+ injection region are isolated by STI, and are connected to metal through contact holes to form two ends P and N of the ESD diode. The invention uses the reverse breakdown of the diode to realize the protection of the internal circuit, skillfully connects the middle PW and NW not to any potential, and guides the current to the ground through the conduction path of N < + > -PW < - > -NW < - > -P < + >, thereby realizing excellent ESD resistance.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a layout design method of an ESD diode.
Background
ESD (electrostatic discharge) can have devastating consequences for an integrated circuit, which is one of the most significant causes of integrated circuit failure; particularly, with the continuous development of integrated circuit technology, the technology size is continuously reduced, the chip scale is increased, and the circuit operating frequency is higher and higher, so that the design of the ESD protection device is particularly important. Thus, how to design an ESD device with high reliability over a limited chip area without the need for additional process steps is a major concern for IC designers.
The design purpose of the ESD diode is to avoid the damage of the internal normal working circuit caused by the discharge path of the ESD; when the internal circuit works normally, the ESD diode is in a cut-off state (high resistance state), and the normal work of the internal circuit is not influenced; when the external pin is abnormally over-voltage and reaches the breakdown voltage of the ESD diode, the external pin can be quickly changed from a high-resistance state to a low-resistance state, and a low-impedance conduction path is provided, so that the internal circuit is protected from damage; when the abnormal overvoltage on the external pin disappears, the ESD diode is restored to a high-resistance state, and the internal circuit can also continue to work normally.
ESD diodes have a fatal disadvantage: when the reverse voltage reaches a certain value, the reverse current suddenly increases, and the ESD diode enters a breakdown region, but if the reverse voltage continues to increase to a certain value, the ESD diode is thoroughly broken down and damaged, so that the standard of 2000V of the ESD HBM (human body model) is not met.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention aims to provide a layout design method of an ESD diode, which utilizes reverse breakdown of the diode to realize protection of an internal circuit, adopts a conduction path in the form of N < + > -PW-NW-P < + >, skillfully connects the middle PW and NW not to any potential, and guides current to the ground through the path, thereby realizing excellent ESD resistance and improving the ESD resistance of the ESD diode.
In order to achieve the above purpose, the invention adopts the technical scheme that: a layout design method of an ESD diode comprises the following steps:
designing a DNW on the P-type substrate, and designing an NW ring around the DNW to be connected with the DNW to form a large DNW closed area;
designing NW and PW in the DNW closed region, designing a PW on each side of the NW, designing a P+ injection region on the NW, and designing an N+ injection region on the PW;
the N+ injection region and the P+ injection region are isolated by ST I, and are connected to metal through contact holes to form two ends P and N of the ESD diode.
Further, the NW and PW are separated from each other to form independent regions.
Further, the DNW and NW are the same implantation type.
Further, the DNW and NW are connected together.
Further, both NW and PW are floating, not connected to any potential.
Further, PW is designed on two sides of NW.
The invention has the following effects: the method of the invention uses the reverse breakdown of the diode to realize the protection of the internal circuit, adopts the N < + > -PW-NW < - > P < + > -form conduction path, skillfully connects the middle PW and NW not to any potential, and guides the current to the ground through the path, thereby realizing excellent ESD resistance and improving the ESD resistance of the ESD diode. And the purpose of improving the performance of the chip is achieved on the basis of not improving the cost of the chip without an additional photomask.
Drawings
FIG. 1 is a layout drawing of an ESD diode of the present invention;
FIG. 2 is an explanatory diagram of the layout levels of FIG. 1;
FIG. 3 is a cross-sectional view of the layout of FIG. 1;
fig. 4 is a current flow diagram of the ESD diode of the present invention in operation.
Detailed Description
The invention is further described below with reference to the drawings and detailed description.
As shown in fig. 1-4, the present invention provides a layout design method of an ESD diode, comprising the following steps:
first, the english abbreviations used in the present invention are: METAL (METAL line), PW (P-well), NW (N-well), DNW (deep N-well), OD (active diffusion region), n+ (N-type implantation region), p+ (P-type implantation region), ST I (shallow trench isolation region), CMOS (complementary METAL oxide semiconductor), PSUB (P-type substrate), CONTACT (CONTACT hole).
The ESD diode of the invention needs a CMOS process (DNW is arranged), a DNW is designed on a P-type substrate, an NW ring is designed around the DNW to be connected with the DNW, and a large DNW sealing area is formed at the moment; designing NW and PW in the DNW closed region, designing a PW (the NW and PW are mutually separated to form independent regions) on two sides of the NW, designing a P+ injection region on the NW, designing an N+ injection region on the PW, isolating the N+ injection region from the P+ injection region by ST I, and connecting the N+ injection region and the P+ injection region to metal through contact holes so as to form two ends P and N of the ESD diode; see fig. 1 and 2.
Fig. 3 is a cross-sectional view of the ESD diode, as shown in the figure, DNW and NW are of the same implant type, so DNW and NW are connected together; both NW and PW are floating and not connected to any potential; each NW has PW on both sides.
In the conducting circuit diagram of the ESD diode in the reverse bias in fig. 4, when the voltage of the n+ terminal exceeds a certain specific value, the n+ PW junction of the ESD diode is reversely biased, and a large current flows from n+ to PW at this time, because the PN junction between PW and NW is positively biased, the current quickly reaches the NW region from PW, and when the current in the NW region is gathered to a certain extent, the PN junction between NW and p+ is reversely biased, and the large current is successfully discharged through p+ to the ground; thus, an ESD conduction path of N+ -PW-NW-P+ is formed, and the P+ terminal is connected to the ground.
In summary, the invention has the following beneficial effects:
1. the standard ESD diode has only one PN structure, and after the reverse voltage is increased to a certain value, the standard ESD diode can be thoroughly broken down and damaged, so that the standard of the ESD HBM (human body model) 2000V can not be reached. The invention uses the reverse breakdown of the diode to realize the protection of the internal circuit, adopts the N < + > -PW-NW < - > P < + > -form conduction path, and the ESD diode skillfully prevents the middle PW and the NW from receiving any potential due to the design of the floating NW and PW, and leads the current to pass through the path to the ground, so that the large current is buffered greatly, thereby realizing excellent ESD resistance.
2. The invention has the greatest effect that the limited area is used for reaching the standard of 2000V of ESD HBM (human body model); and has advantages not possessed by other ESD devices such as fast response time, low clamp voltage, high current surge withstand capability, etc.
3. The invention does not need to add an extra photomask and does not increase the cost of the chip.
It will be appreciated by persons skilled in the art that the methods and systems of the present invention are not limited to the examples described in the detailed description, which are provided for the purpose of illustrating the invention only and are not intended to limit the invention. Other embodiments will occur to those skilled in the art from a consideration of the specification and practice of the invention as claimed and as claimed in the claims and their equivalents.
Claims (5)
1. A layout design method of an ESD diode comprises the following steps:
designing a DNW on the P-type substrate, and designing an NW ring around the DNW to be connected with the DNW to form a large DNW closed area;
designing NW and PW in the DNW closed region, designing a PW on each side of the NW, wherein the NW and the PW are floating and not connected to any potential, guiding current to the ground through an N+ -PW-NW-P+ -form conduction path, designing a P+ -implantation region on the NW, and designing an N+ -implantation region on the PW;
the N+ injection region and the P+ injection region are isolated by STI, and are connected to metal through contact holes to form two ends P and N of the ESD diode.
2. The layout design method of an ESD diode of claim 1, wherein: the NW and PW are separated from each other to form independent regions.
3. The layout design method of an ESD diode of claim 1, wherein: the DNWs and NWs are the same implantation type.
4. A layout design method of an ESD diode according to any one of claims 1 to 3, wherein: the DNWs and NWs are connected together.
5. A layout design method of an ESD diode according to any one of claims 1 to 3, wherein: PW is designed on two sides of the NW.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911071138.XA CN111046623B (en) | 2019-11-05 | 2019-11-05 | Layout design method of ESD diode |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911071138.XA CN111046623B (en) | 2019-11-05 | 2019-11-05 | Layout design method of ESD diode |
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| CN111046623B true CN111046623B (en) | 2023-07-21 |
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| CN117316929A (en) * | 2022-06-24 | 2023-12-29 | 长鑫存储技术有限公司 | Electrostatic protection structure and chip |
Citations (3)
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| CN1445849A (en) * | 2002-03-17 | 2003-10-01 | 联华电子股份有限公司 | Electrostatic discharge protection circuit |
| CN104409454A (en) * | 2014-11-10 | 2015-03-11 | 无锡友达电子有限公司 | NLDMOS anti-static protection tube |
| CN110391223A (en) * | 2019-07-29 | 2019-10-29 | 南京微盟电子有限公司 | A kind of esd protection circuit in inverse-excitation type primary side feedback Switching Power Supply control chip |
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| US6621126B2 (en) * | 2000-10-10 | 2003-09-16 | Sarnoff Corporation | Multifinger silicon controlled rectifier structure for electrostatic discharge protection |
| US6835985B2 (en) * | 2000-12-07 | 2004-12-28 | Chartered Semiconductor Manufacturing Ltd. | ESD protection structure |
| US7052939B2 (en) * | 2002-11-26 | 2006-05-30 | Freescale Semiconductor, Inc. | Structure to reduce signal cross-talk through semiconductor substrate for system on chip applications |
| JP4781620B2 (en) * | 2003-08-12 | 2011-09-28 | ルネサスエレクトロニクス株式会社 | Electrostatic discharge protection element |
| US7202114B2 (en) * | 2004-01-13 | 2007-04-10 | Intersil Americas Inc. | On-chip structure for electrostatic discharge (ESD) protection |
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| CN101847633B (en) * | 2010-05-05 | 2011-10-26 | 北京大学 | Electrostatic protective device and preparation method thereof |
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| US9455338B1 (en) * | 2012-12-14 | 2016-09-27 | Altera Corporation | Methods for fabricating PNP bipolar junction transistors |
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| JP6292041B2 (en) * | 2014-06-11 | 2018-03-14 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
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| CN110391223A (en) * | 2019-07-29 | 2019-10-29 | 南京微盟电子有限公司 | A kind of esd protection circuit in inverse-excitation type primary side feedback Switching Power Supply control chip |
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