TW201717351A - A semiconductor device - Google Patents

Abstract

A semiconductor device applied for ESD protection in VLSI includes a first TYPE_II lightly doped region, a second TYPE_II lightly doped region, a third TYPE_II lightly doped region and a fourth TYPE_II lightly doped region. The TYPE_II lightly doped regions are disposed sequentially and disconnected with each other in a TYPE_I semiconductor region. A first TYPE_I doped region is disposed in the first TYPE_II lightly doped region, a first TYPE_II doped region is disposed in the second TYPE_II lightly doped region, a second TYPE_I doped region is disposed in the third TYPE_II lightly doped region, and a second TYPE_II doped region is disposed in the fourth TYPE_II lightly doped region. The TYPE_I doped region is connected to ground, the first TYPE_II doped region and the second TYPE_I doped region are connected together to an I/O port, and the second TYPE_II-type region is connected to a terminal.

Description

Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a semiconductor device that provides an integrated circuit electrostatic discharge protection circuit.

The damage of static electricity to electronic products has always been a problem. When electronic products are subjected to electrostatic discharge (ESD), there are often some unstable phenomena, such as sudden malfunction of functions, etc., lighter must be restarted to eliminate, Sometimes electronic components in electronic products can be damaged by static voltage or current. In order to ensure the function of electronic products, internationally renowned manufacturers require OEM products to comply with international standards IES61000-4-2 ESD test will be accepted. However, in order to make the electronic products have the ability to prevent static electricity, in addition to the protection of the semiconductor components, it is necessary to start from the two aspects of product system design and prevention technology, in order to exert the electrostatic protection function.

The integrated circuit is used to protect the integrated circuit by a transient voltage suppressing circuit (TVS) to avoid damage caused by the impact of the abnormal overvoltage on the integrated circuit. However, in the case of electrostatic discharge (ESD), electrical fast transient (EFT) and lightning, a high voltage that cannot be expected and controlled may accidentally hit the circuit; therefore, borrow The internal circuit core protection function of the integrated circuit can be provided by the transient voltage suppression component to avoid possible problems due to overvoltage. Unrecoverable damage in the integrated circuit. With the gradual increase in the number of components implemented in integrated circuits and the use of low-power core circuits, these low-power core components are more susceptible to overvoltage damage, so the need and dependence on transient voltage suppressors is also It will increase. Typical applications for transient voltage suppressors are general-purpose serial bus power supplies, data line protection, digital image interfaces, high-speed Ethernet, notebook computers, display devices, and flat panel displays.

One aspect of the present invention is a semiconductor device comprising a light-doped region of a type A semiconductor, a first type B lightly doped region, a second type B lightly doped region, and a third type B lightly doped region. And the first to fourth B-type lightly doped regions are disposed in the light-doped region of the A-type semiconductor and are sequentially arranged without contact with each other. A first type A doped region is disposed in the first type B lightly doped region, a first type B doped region is disposed in the second type B lightly doped region, and a second type A doped region is disposed In the third type B lightly doped region, a second type B doped region is disposed in the fourth type B lightly doped region, wherein the first type A doped region is electrically connected to a ground point, the first type B The doped region and the second type A doped region are electrically connected to a signal input and output end, and the second type B doped region is electrically connected to an end point.

According to one or more embodiments of the present invention, the semiconductor device further includes: a first type A lightly doped region disposed in the lightly doped region of the semiconductor semiconductor, wherein the first type A lightly doped region is in close proximity The fourth type B lightly doped region is separated from the fourth type B lightly doped region by a first pitch. A third B-type doped region and a fourth B-type doped region are disposed in the first type A lightly doped region, wherein an isolation structure exists between the third B-type doped region and the fourth B-type doped region .

According to one or more embodiments of the present invention, there is an isolation structure between the second B-type lightly doped region and the third B-type lightly doped region. According to one or more embodiments of the present invention, the first B-type lightly doped region, the second B-type lightly doped region, the third B-type lightly doped region, and the fourth B-type lightly doped region have a Isolation structure.

According to one or more embodiments of the present invention, a B-type semiconductor substrate is further included, wherein the A-type semiconductor well is placed in the B-type semiconductor substrate. According to one or more embodiments of the present invention, the second type B lightly doped region and the third type B lightly doped region have an isolation structure. According to one or more embodiments of the present invention, the first B-type lightly doped region, the second B-type lightly doped region, the third B-type lightly doped region, and the fourth B-type lightly doped region have a Isolation structure.

Another aspect of the present invention is a semiconductor device comprising: a B-type semiconductor substrate; a first A-type lightly doped region and a second A-type lightly doped region, disposed in the B-type semiconductor substrate, wherein The first type A lightly doped region is not in contact with the second type A lightly doped region. a first type B lightly doped region and a second type B lightly doped region are disposed in the first type A lightly doped region, wherein the first type B lightly doped region and the second type B lightly doped region Not in contact. a third type B lightly doped region and a fourth type B lightly doped region are disposed in the second type A lightly doped region, wherein the third type B lightly doped region and the fourth type B lightly doped region Not in contact. A first type A doped region is disposed in the first type B lightly doped region, a first type B doped region is disposed in the second type B lightly doped region, and a second type A doped region is disposed In the third B-type lightly doped region, a second B-type doped region is placed in the fourth B-type lightly doped region. The first type A doped region is electrically connected to a ground point, the first type B doped region and the second type A doped region are electrically connected to a signal output end, and the second type B doped region is electrically connected To an endpoint.

According to one or more embodiments of the present invention, there is an isolation structure between the first type A lightly doped region and the second type A lightly doped region. According to one or more embodiments of the present invention, there is an isolation structure between the first B-type lightly doped region and the second B-type lightly doped region, and the third B-type lightly doped region and the fourth B-type lightly doped region There is an isolation structure between them.

According to one or more embodiments of the present invention, the type A is a P-type semiconductor, and the type B is an N-type semiconductor.

According to one or more embodiments of the present invention, the type A is an N-type semiconductor, and the type B is a P-type semiconductor.

10 100 200 300‧‧‧Integrated circuits

11 12 21 22 31‧‧‧Electrostatic protection components

41 42‧‧‧ circuit core

111 211 311‧‧‧First P-doped region

112 212 312‧‧‧First N-doped region

113 213 313‧‧‧Second P-doped region

114 214 314‧‧‧Second N-doped region

116 216 316‧‧‧Third N-doped region

118 218 318‧‧‧Four N-doped region

122 222 322‧‧‧First N-type well/lightly doped area

224 324‧‧‧Second N-type well/lightly doped area

226‧‧‧Third N-type well/lightly doped area

228‧‧‧Four N-type well/lightly doped area

230‧‧‧P type semiconductor well area

330‧‧‧N type semiconductor well area

131 221 231 321‧‧‧First P-well/lightly doped zone

133 233 323‧‧‧Second P-well

325‧‧‧ Third P-well

327‧‧‧Four P-type well

329‧‧‧ Fifth P-well

240‧‧‧N type semiconductor substrate

350‧‧‧P type semiconductor substrate

290‧‧‧Isolation structure

I/O I/O1 I/O2‧‧‧ signal output input

Vcc‧‧‧ power terminal

GND‧‧‧ Grounding point

VR‧‧‧Reverse bias VR

Vt‧‧‧ trigger voltage

Vh‧‧‧Pressure voltage Vh

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The schematic diagram of the integrated circuit of the ESD protection circuit; the third diagram shows the current-voltage characteristic curve of the ESD protection circuit discharge; the fourth diagram shows the schematic diagram of the integrated circuit of the ESD protection circuit; and the fifth figure shows the ESD protection The current-voltage characteristic diagram of the circuit discharge; the sixth diagram shows the schematic diagram of the integrated circuit of the ESD protection circuit; the seventh diagram shows the schematic diagram of the integrated circuit of the ESD protection circuit; and the figure 8 shows the product of the ESD protection circuit. FIG. 9 is a cross-sectional view showing the integrated circuit of the ESD protection circuit; FIG. 10 is a schematic cross-sectional view showing the integrated circuit of the ESD protection circuit; and FIG. 11 is a schematic cross-sectional view showing the integrated circuit of the ESD protection circuit; Figure 12 is a cross-sectional view showing the integrated circuit of the ESD protection circuit.

The embodiments of the present invention are disclosed in the following drawings, and the details of However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

1 is a schematic diagram of an integrated circuit 10 including a power supply terminal Vcc, a grounding point GND, a signal output input terminal I/O1 I/O2, an electrostatic protection component 11 12 21 22 31, and a circuit core 41 42. In one embodiment, the circuit core 41 42 is a digital logic circuit or analog circuit that operates at a lower voltage operating range, such as below 20 volts. Typically, the digital logic circuit operates at 5V, 3.3V, 2.5V, At 1.8V or lower, the analog circuit may operate at a higher voltage range, such as tens of volts. The constituent elements of the digital circuit or the analog circuit are generally a gold oxide semiconductor device MOS or a bipolar semiconductor device BJT. In the case where the integrated circuit 10 has not been operated, an electrostatic high voltage which is externally or self-accumulated may be encountered, typically several thousand volts or tens of thousands of volts, when a pin of the integrated circuit 10 contacts ground (Ground), The static electricity accumulated on the integrated circuit 10 itself is discharged to the ground point, which is liable to cause irreparable damage to the semiconductor elements in the circuit core 41 42 during the discharge. In another embodiment, when the integrated circuit 10 is in operation, it is also possible An external high voltage surge is encountered, causing damage to the semiconductor components within the circuit core 41 42.

In one embodiment, the integrated circuit 10 includes an Electrostatic Discharge (ESD) protection circuit to protect the circuit core 41 42 from damage caused by the electrostatic high voltage or high voltage surge described above. In the embodiment shown in Figure 1, the ESD protection circuit comprises an electrostatic protection element 11 12 21 22 31. In an embodiment, the electrostatic protection component 11 12 21 22 is a diode, but is not limited thereto; in another embodiment, the electrostatic protection component 11 12 21 22 includes a gold oxide semiconductor component MOS, a bipolar semiconductor component BJT or P/N junction formed by other semiconductor components. In one embodiment, the electrostatic protection element 31 is a Zener diode, but is not limited thereto; in another embodiment, the electrostatic protection element 31 comprises a gold oxide semiconductor component MOS, a bipolar semiconductor component BJT or the like. A P/N junction formed by a semiconductor device.

According to the embodiment shown in FIG. 1, in the actual application, when the integrated circuit 10 is not connected to the power supply, when there is a positive high-voltage electrostatic contact signal output input I/O1, the positive high-voltage static electricity is protected by static electricity. The component 11, the power supply terminal Vcc (when the power supply terminal Vcc is not connected to the external power supply), and the electrostatic protection component 31 are discharged to the grounding point GND, at which time the electrostatic protection component 11 is forward biased, and the electrostatic protection component 31 is reversely collapsed. The holding voltage (Vh), the above-mentioned holding voltage value Vh does not cause damage to the circuit core 41, and the electrostatic protection element 31 also has a sufficiently large interface area to release an instantaneous large current. In contrast, when a negative high-voltage electrostatic contact signal is output to the input I/O1, the negative high-voltage static electricity passes through the biased static electricity. The protection element 12 is discharged, the on-voltage value of the biased electrostatic protection element 12 does not cause damage to the circuit core 41, and the forward-biased electrostatic protection element 12 can discharge an instantaneous large current. It can be understood from the above description that when any external electrostatic contact is made to any one of the signal output terminals of the integrated circuit 10, the above principle can protect the circuit core 41 42 from electrostatic damage.

Next, please refer to FIG. 2, which shows a cross-sectional view of the electrostatic protection element 11 12 31 of FIG. 1 on the actual semiconductor wafer 100, to explain the principle of ESD protection, and FIG. 2 omits the electrostatic protection element 21 22 and A cross-sectional view of circuit core 41 42. As shown in Fig. 2, the first P-type well 131 includes the electrostatic protection element 12 shown in Fig. 1, the first N-type well 122 includes the electrostatic protection element 11, and the second P-type well 133 includes the electrostatic protection element. 31. The first P-type doping region 111 and the first N-type doping region 112 are disposed in the first P-type well 131, and the second P-type doping region 113 and the second N-type doping region 114 are disposed in the first N-type well In well 122, third N-type doped region 116 and fourth N-type doped region 118 are placed in second P-type well 133. In one implementation, the first P-type doping region 111 is connected to the ground point GND; the first N-type doping region 112 and the second P-type doping region 113 are commonly connected to a signal output input terminal I/O1; The N-type doped region 114 and the third N-type doped region 116 are commonly connected to the terminal 1 . In one embodiment, the terminal 1 is connected to the power supply terminal Vcc and the fourth N-type doped region 118 is connected to the ground GND. .

In an embodiment, when the semiconductor wafer 100 is not in operation, the terminal 1 is not connected to the power supply terminal Vcc. At this time, if the static electricity contacts the signal output input terminal I/O1, the second P-type doping region 113 and the first An N-type well 122 forms a positively biased P/N interface, and its equivalent circuit is such as the electrostatic protection element 11 shown in FIG. After the positive electrostatic current flows through the second P-type doping region 113 and the first N-type well 122, the second N-type doping region 114 flows out to the terminal 1 and then flows into the second N-type doping region 116. After the P-type well 133, it flows out to the ground point via the fourth N-type doping region 118. When it can be found that the third N-type doping region 116 and the second P-type well 133 at this time form a reverse biased N/P interface, the equivalent circuit thereof is the electrostatic protection element 31 shown in FIG. The breakdown voltage of the reverse bias N/P (116/113) interface is the trigger voltage of the electrostatic protection element 31 (Trigger voltage: Vt). As shown in FIG. 3, once the reverse bias voltage V _R exceeds the trigger voltage Vt, The reverse biased N/P (116/113) interface begins to generate a reverse current I _R and flows out through the forward biased P/N interface (133/118), where the entire current path is the second P-type doping. Zone 113 / first N-type well 122 / second N-type doped region 114 / third N-type doped region 116 / second P-type well 133 / fourth N-type doped region 118, which is P / N / The P/N structure forms an SCR element.

The current-voltage characteristic of the SCR component is as shown in Fig. 3. When the reverse bias voltage V _R exceeds the trigger voltage Vt, it first assumes a positive resistance state, and the voltage still increases slightly with the increase of the reverse current. When the reverse voltage is higher than one. When the critical value (not shown), the SCR component is in a negative resistance state, and the voltage rapidly decreases with the increase of the current. After the voltage Vh is maintained, the SCR presents a small positive resistance component, which can pass a large The current has only a slight voltage change, releasing a large amount of static electricity in this interval. A disadvantage of the SCR component is that it has a negative resistance state interval, which may cause the integrated circuit to oscillate due to the positive feedback effect, and its trigger voltage Vt may be too high to protect to the circuit core 41 42.

Conversely, when the negative high voltage static electricity contacts the signal output input I/O, the negative high voltage static electricity causes the electrostatic protection element 12 to pass the conduction. The forward biased P/N interface releases a negative electrostatic charge. In FIG. 2, the first P-type doped region 111 / the first P-type well 131 and the first N-type doped region 112 are forward biased. P/N interface, while releasing negative high voltage static electricity. The current-voltage characteristic curve of the negative high static voltage discharge is a current-voltage characteristic curve (not shown) of a positively biased P/N interface diode. It can be found that the current-voltage characteristic curve of the negative high static voltage discharge is different from the positive and negative high static voltage discharge.

FIG. 4 illustrates an embodiment of the present invention. To facilitate the description of the ESD protection principle, in the present embodiment, the semiconductor wafer 200 only shows a cross-sectional view of the ESD protection component, and the circuit core is omitted. Please refer to FIG. 1 at the same time to better understand the description of the embodiment. In this embodiment, the ESD protection circuit includes a P-type semiconductor well region 230, a first N-type well 222, a second N-type well 224, and a third. N-well 226, fourth N-well 228, and first P-well 221 are all placed in P-type semiconductor well region 230. In another embodiment, the P-type semiconductor well region 230 comprises a P-type semiconductor substrate, a P-type semiconductor well, and a P-type semiconductor epitaxial layer. The first P-type doping region 211 is disposed in the first N-type well 222, the first N-type doping region 212 is disposed in the second N-type well 224, and the second P-type doping region 213 is placed in the third In the N-well 226, the second N-type doping region 214 is placed in the fourth N-type well 228, and the third N-type doping region 216 and the fourth N-type doping region 218 are both placed in the first P-type well 221 in.

In one embodiment, the fourth N-well 228 has a spacing from the first P-well 221 that is adjustable in accordance with the applicable ESD range. In one embodiment, the third N-type doped region 216 has a spacing from the fourth N-type doped region 218, which spacing can be adjusted according to the applicable ESD range. In an embodiment, the first An N-type well 222, a second N-type well 224, a third N-type well 226 and a fourth N-type well 228 have a spacing from each other, and the spacing between them is not necessarily equal, depending on the applicable ESD. Adjust by scope.

In one implementation, the first P-type doped region 211 has a distance from the boundary of the first N-type well 222, and the distance can be adjusted depending on the actual application. In one embodiment, the first N-type doped region 212 has a distance from the boundary of the second N-type well 224, and the distance can be adjusted depending on the application. In one embodiment, the second P-type doped region 213 has a distance from the boundary of the third N-type well 226, and the distance can be adjusted depending on the application. In one embodiment, the second N-doped region 214 has a distance from the boundary of the fourth N-well 228, and the distance can be adjusted depending on the application. In one embodiment, the third N-type doped region 216 and the fourth N-type doped region 218 have a distance from the boundary of the first P-type well 221, and the distance can be adjusted according to practical applications.

In an embodiment, the first P-type doping region 211 is connected to the grounding point GND; the first N-type doping region 212 and the second P-type doping region 213 are commonly connected to an output input terminal I/O; The N-type doping region 214 and the third N-type doping region 216 are commonly connected to an end point 1; the fourth N-type doping region 218 is connected to the grounding point GND. When the semiconductor wafer 200 is not in operation, the terminal 1 is not connected to the power supply terminal Vcc, and the second P-type doping region 213 forms a P/N interface with the third N-type well 226, and its equivalent circuit is as shown in FIG. The electrostatic protection element 11; the first N-type doping region 212 / the second N-type well 224 and the P-type semiconductor well region 230 form an N/P interface, and the equivalent circuit thereof such as the electrostatic protection element 12; the third N-type doping The miscellaneous region 216 forms an N/P interface with the first P-well 221, and its equivalent circuit such as the electrostatic protection element 31.

In one embodiment, the first N-well 222, the second N-well 224, the third N-well 226, the fourth N-well 228, and the first P-well 221 shown in FIG. 4 are not limited to semiconductors. A well defined by the field, which is more generally referred to as a first N-type doped region 212, a second N-type doped region 214, a third N-type doped region 216, and a fourth The N-doped region 218, the first P-doped region 211, and the second P-doped region 213 are doped with a lighter concentration region, in one embodiment, the first, second, third, and fourth N-types described above. The well and first P-well 222/224/226/228/221 may be first, second, third, fourth N-type and first P-type lightly doped regions 222/224/226/228/221. The above-mentioned N-type and P-type doping regions, in a broader sense, mean a region having a relatively high doping concentration with respect to the above-mentioned wells.

Referring also to FIG. 5, in an embodiment, the second P-type doping region 213, the third N-type well 226, and the P-type semiconductor well region 230 form a parasitic PNP interface. When positive static electricity contacts the signal output input I/O, the second N-well 224 and the third N-well 226 and the P-type semiconductor well region 230 are reverse biased; when positive static electricity is greater than the trigger voltage Vt The discharge path of the current is from the second P-type doping region 213, through the third N-type well 226, the P-type semiconductor well region 230, the first N-type well 222, and the first P-type doped region 211 to the ground point GND. Since the current path has an equivalent resistance, when the discharge current increases, the voltage of the P-type semiconductor well region 230 increases, thereby turning on the P/N between the first P-type well 221 and the fourth N-type doped region 218. The interface further releases a larger electrostatic current. As shown in Fig. 5, in this embodiment, the current-voltage characteristic of the positive high voltage electrostatic discharge can be found to have at least two advantages: First, there is no negative resistance region, which does not cause the integrated circuit 200 to vibrate. The possibility of soup; second, no The holding voltage Vh lower than the trigger voltage Vt does not have the possibility that the holding voltage Vh falls within the operating voltage range of the integrated circuit 200.

Conversely, when the negative high-voltage static electricity contacts the signal output input I/O (please refer to FIG. 1 at the same time), the negative high-voltage static electricity causes the electrostatic protection component 12 to pass through, and the forward biased P/N interface The negative electrostatic charge is released. In FIG. 4, the P-type semiconductor well region 230 and the second N-well 224 are forward biased P/N interfaces; however, the first N-well 222 and the P-type semiconductor well region 230 are When the N/P interface is reverse biased, but the negative voltage is higher than the negative trigger voltage Vt, the first P-type doping region 211 and the first N-type well 222 generate a tunneling effect, and release the negative high-voltage static electricity. Another advantage of this embodiment is that positive high voltage statics have similar current-voltage characteristics as negative high static voltage discharges, all of which have no negative resistance intervals.

In one example, the first P-type doping region 211 is disposed in a central region of the first N-type well 222, and the placing in the central region means that the two sides of the first P-type doping region 211 are separated from the first N-type well. The two side boundaries of 222 have substantially the same spacing. Also in an embodiment, the first N-type doped region 212 is placed in a central region of the second N-type well 224. In an embodiment, the second P-type doping region 213 is disposed in a central region of the third N-type well 226. In other embodiments, the first P-type doping region 211, the first N-type doping region 212, the second P-type doping region 213, and the second N-type doping region 214 may also not be placed therein. The central regions of the first, second, third, and fourth N-type wells 222/224/226/228 may be biased toward either side of the N-type region in which they are located.

In one embodiment, there is an isolation structure 290 between the second N-well 224 and the third N-well 226, and/or the fourth N-well 228 and the first P There is an isolation structure 290 between the wells 221. In one embodiment, there is an isolation structure 290 between the first N-well 222 and the second N-well 224, and/or an isolation structure 290 between the third N-well 226 and the fourth N-well 228. The isolation structure 290 includes shallow trench isolation (STI) and field oxide (FOX). In one embodiment, the P/N interface within the first P-well 221 is comprised of a parasitic P/N interface of a transistor (MOS, but not limited thereto).

For convenience of description, the following embodiments of the present invention only show the first, second, third, and fourth N-type wells 222/224/226/228/ in the P-type semiconductor well region in FIGS. 6-9. Schematic diagram in 230. Referring to FIG. 6, in an embodiment, the P-type semiconductor well region 230 can be disposed in an N-type semiconductor substrate 240. In an embodiment, between the second N-well 224 and the third N-well 226 An isolation structure 290 is included. As shown in FIG. 7, in an embodiment, an isolation structure 290 is included between the first N-well 222 and the second N-well 224, and the third N-well 226 and the fourth N-well 228 are included. An isolation structure 290.

Fig. 8 is a view showing another embodiment of the present invention, and the difference from the embodiment of Figs. 6 and 7 is that the P-type semiconductor well region 230 in the first embodiment of Fig. 6, 7 is divided into two spaced apart sections. A P-well 231 and a second P-well 233. The first and second P-type wells are placed in the N-type semiconductor substrate 240 and the two P-type wells are spaced apart by a spacing; the first N-type well 222 and the second N-type well 224 are placed in the first P-type well 231, A three N-well 226 and a fourth N-well 228 are placed in the second P-well 233. The right side boundary of the second N-type well 224 has a first distance from the right side boundary of the first P-type well 231, and the left side boundary of the third N-type well 226 and the left side of the second P-type well 233 There is a second distance in the boundary. A pitch, a first distance, and/or a second distance may be adjusted to adjust the trigger voltage Vt of the static electricity protection circuit.

In an embodiment, an isolation structure 290 is included between the first P-well 231 and the second P-well 233. In another embodiment, as shown in FIG. 9, an isolation structure 290 is included between the first N-well 222 and the second N-well 224, and between the third N-well 226 and the fourth N-well 228. An isolation structure 290 is included.

In an embodiment, the N-type or P-type semiconductor type in the ESD protection circuit semiconductor structure may be changed, such as the ESD protection circuit semiconductor structure shown in FIG. 10, and the difference from the embodiment shown in FIG. 4 is mainly Changes in N-type and P-type semiconductor types. In this embodiment, the ESD protection circuit includes a first P-type well 321, a second P-type well 323, a third P-type well 325, a fourth P-type well 327, and a fifth P-type well 329, all of which are placed in an N-type. In the semiconductor well area 330. In another embodiment, the N-type semiconductor well region 330 can be an N-type semiconductor substrate, an N-type semiconductor well (N well), and an N-type semiconductor epitaxial layer. The first N-type doping region 312 is disposed in the first P-type well 321 , the first P-type doping region 311 is disposed in the second P-type well 323 , and the second N-type doping region 314 is disposed in the third In the P-well 325, the second P-type doping region 313 is placed in the fourth P-type well 327, and the third N-type doping region 316 and the fourth N-type doping region 318 are both placed in the fifth P-type well 329. in.

In one embodiment, the first P-type well 321 , the second P-type well 323 , the third P-type well 325 , the fourth P-type well 327 and the fifth P-type well 329 shown in FIG. 10 are not limited to semiconductors. Wells defined by the field, which are more broadly described as being opposite to the first N-type doped region 312, the second N-type doping The region 314, the third N-type doped region 316, the fourth N-type doped region 318, the first P-type doped region 311, and the second P-type doped region 313 are doped with a lighter concentration region. The above-mentioned N-type and P-type doping regions, in a broader sense, mean a region having a relatively high doping concentration with respect to the above-mentioned wells.

In one embodiment, the first N-type doping region 312 is connected to the terminal 1; the first P-type doping region 311 and the second N-type doping region 314 are commonly connected to an output input terminal I/O; The P-type doping region 313 is connected to the ground point, the third N-type doping region 316 is connected to the terminal 1; and the fourth N-type doping region 318 is connected to the grounding point GND. When the semiconductor wafer 300 is not operating, the terminal 1 is not yet connected to the power supply terminal Vcc.

When positive static electricity contacts the signal output input I/O, the first P-type doping region 311 / the second P-type well 323 and the N-type semiconductor well region 330 are forward biased, but the N-type semiconductor well region 330 and The fourth P-well 327 is reverse biased; when the positive static electricity is greater than the trigger voltage Vt, the current discharge path is from the first P-type doping region 311 and the second P-type well 323 via the N-type semiconductor well region 330. The fourth P-type well 327 and the second P-type doped region 313 are connected to the ground point GND. Conversely, when negative static electricity contacts the signal output input I/O, the N-type semiconductor well region 330 is reverse biased with the second and third P-wells 323 325, when the negative static electricity is greater than the trigger voltage Vt. The discharge path of the current is from the second N-type doped region 314 / the third P-type well 325 via the N-type semiconductor well region 330, the fourth P-type well 327 and the second P-type doped region 313 to the ground point GND.

It is worth noting that the negative static electricity described in this specification is greater than the trigger voltage Vt compared with the absolute value of the voltage. In other words, it means that the absolute value of the negative static voltage is greater than the absolute value of the trigger voltage Vt.

For convenience of description, the embodiments of FIGS. 11 and 12 only show schematic diagrams of the first, second, third, and fourth P-type wells 321/323/325/327 in the N-type semiconductor well region 330. . Referring to FIG. 11, in an embodiment, the N-type semiconductor well region 330 can be placed in a P-type semiconductor substrate 350. Referring to FIG. 12, in an embodiment, the N-type semiconductor well region 330 in the embodiment of FIG. 11 is divided into two spaced apart first N-type wells 322 and second N-type wells 324. The first N-type well 322 324 is placed in the P-type semiconductor substrate 350 and the two N-type wells are spaced apart by a spacing; the first P-type well 321 and the second P-type well 323 are placed in the first N-type well 322. The third P-well 325 and the fourth P-well 327 are placed in the second N-well 324.

It should be noted that the P-type or N-semiconductor well region of the present invention, the P-type or N-type well, refers to a semiconductor region having a lower doping concentration, and can be formed differently in the semiconductor region with low doping concentration. A semiconductor region of the type; for example, another P-type low doping concentration semiconductor region is formed in the N-type low doping concentration semiconductor region, or vice versa. Or forming a heavily doped doped region in the low doping concentration semiconductor region, and the doped region having the heavily doped concentration can be used as a source, a drain, or a low doping concentration semiconductor of the MOS device. Zone to external contact area to reduce contact resistance. In other words, the semiconductor region having a lower doping concentration may be a well known to those skilled in the semiconductor art, which is a low doping concentration semiconductor region formed by ion implantation and then high temperature diffusion, if an epitaxial technique is used. Or a low doping concentration semiconductor region formed by other methods, which are all equal ranges of the "well" of the present invention.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and those skilled in the art, without departing from the spirit of the invention, In the scope of the invention, the scope of the invention is defined by the scope of the appended claims.

200‧‧‧ integrated circuit

211‧‧‧First P-doped region

212‧‧‧First N-doped region

213‧‧‧Second P-doped region

214‧‧‧Second N-doped region

216‧‧‧Third N-doped region

218‧‧‧4th N-doped region

222‧‧‧First N-type well/lightly doped area

224‧‧‧Second N-type well/lightly doped area

226‧‧‧Third N-type well/lightly doped area

228‧‧‧Four N-type well/lightly doped area

221‧‧‧First P-well/lightly doped zone

230‧‧‧P type semiconductor well area

290‧‧‧Isolation structure

I/O‧‧‧ signal output input

Vcc‧‧‧ power terminal

GND‧‧‧ Grounding point

Claims (10)

A semiconductor device comprising: a light-doped region of a type A semiconductor; a first type B lightly doped region disposed in the lightly doped region of the type A semiconductor; and a second type B lightly doped region disposed therein a light-doped region of the semiconductor A; a third B-type lightly doped region disposed in the light-doped region of the semiconductor; a fourth B-type lightly doped region disposed in the light-doped semiconductor In the region, wherein the first, second, third, and fourth B-type lightly doped regions are sequentially arranged in the light-doped region of the semiconductor semiconductor, and are not in contact with each other; a first type A doping a region is disposed in the first B-type lightly doped region; a first B-type doped region is disposed in the second B-type lightly doped region; and a second B-type doped region is disposed in the third B-type region In the lightly doped region, a second type B doped region is disposed in the fourth type B lightly doped region, wherein the first type A doped region is electrically connected to a ground point, and the first type B is doped The impurity region and the second type-doped region are electrically connected to a signal output terminal, and the second type B doping region is electrically connected to an end point. The semiconductor device of claim 1, wherein the second type B lightly doped region and the third type B lightly doped region have an isolation structure. The semiconductor device of claim 1, further comprising a type B semiconductor substrate, wherein the type A semiconductor region is placed in the type B In a semiconductor substrate. The semiconductor device of claim 3, wherein the second type B lightly doped region and the third type B lightly doped region have an isolation structure. The semiconductor device according to any one of claims 1 to 4, wherein the type A is a P type, and the type B is an N type. The semiconductor device according to any one of claims 1 to 4, wherein the type A is an N type, and the type B is a P type A semiconductor device comprising: a B-type semiconductor substrate; a first type A lightly doped region disposed in the B-type semiconductor substrate; and a second type A lightly doped region disposed in the B-type semiconductor substrate Wherein the first type A lightly doped region is not in contact with the second type A lightly doped region; a first type B lightly doped region is disposed in the first type A lightly doped region; a lightly doped region disposed in the first type A lightly doped region, wherein the first type B lightly doped region is not in contact with the second type B lightly doped region; a third type B lightly doped region a region, disposed in the second type A lightly doped region; a fourth type B lightly doped region disposed in the second type A lightly doped region, wherein the third type B lightly doped region and the The fourth type B lightly doped region is not in contact; a first type A doped region is disposed in the first type B lightly doped region; a first type B doped region is disposed in the second type B lightly doped region; a second type A doped region is disposed in the third type B lightly doped region; and a second type B doped region And being disposed in the fourth type B lightly doped region, wherein the first type A doped region is electrically connected to a ground point, and the first type B doped region is electrically connected to the second type A doped region The second B-type doping region is electrically connected to an end point to the signal input and output terminals. The semiconductor device of claim 8, wherein the first type A lightly doped region and the second type A lightly doped region have an isolation structure. The semiconductor device according to claim 7 or 8, wherein the type A is a P type, and the type B is an N type. The semiconductor device according to claim 7 or 8, wherein the type A is an N type, and the type B is a type P