CN102148241A - Coupling-capacitor triggered silicon controlled device - Google Patents
Coupling-capacitor triggered silicon controlled device Download PDFInfo
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- CN102148241A CN102148241A CN 201010616239 CN201010616239A CN102148241A CN 102148241 A CN102148241 A CN 102148241A CN 201010616239 CN201010616239 CN 201010616239 CN 201010616239 A CN201010616239 A CN 201010616239A CN 102148241 A CN102148241 A CN 102148241A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 59
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 57
- 239000010703 silicon Substances 0.000 title claims abstract description 57
- 239000003990 capacitor Substances 0.000 title abstract description 13
- 230000001960 triggered effect Effects 0.000 title abstract 3
- 230000008878 coupling Effects 0.000 claims abstract description 39
- 238000010168 coupling process Methods 0.000 claims abstract description 39
- 238000005859 coupling reaction Methods 0.000 claims abstract description 39
- 238000002347 injection Methods 0.000 claims description 37
- 239000007924 injection Substances 0.000 claims description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000003068 static effect Effects 0.000 abstract description 13
- 239000002184 metal Substances 0.000 abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 abstract 2
- 150000004706 metal oxides Chemical class 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000010248 power generation Methods 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a coupling-capacitor triggered silicon controlled device which comprises a triggering signal generating circuit and a controlled silicon with a triggering end; a coupling capacitor circuit is used for outputting trigging signals and supplying enough starting currents to the controlled silicon so as to differentiate ESD (electronic static discharge) pulses and normal electric signals of the circuit; a PMOS (P-channel metal oxide semiconductor) switch for distinguishing the ESD pulses is added on the coupling capacitor circuit so that the coupling capacitor circuit is connected into a power line only in the condition of ESD, thereby achieving the purpose of reducing standby leakage of the coupling capacitor circuit. Compared with the traditional coupling-capacitor triggered SCR (silicon controlled rectifier) structure depending on a metal layer capacitor to serve as a coupling capacitor, the silicon controlled device adopts an MOS (metal oxide semiconductor) capacitor tube so as to save more area and solves the current leakage problem of the MOS capacitor tube under direct-current bias.
Description
Technical field
The invention belongs to integrated circuit electrostatic defending field, be specifically related to a kind of coupling capacitance and trigger silicon-controlled device.
Background technology
Natural Electrostatic Discharge phenomenon constitutes serious threat to the reliability of integrated circuit.In industrial quarters, the inefficacy 30% of integrated circuit (IC) products all is owing to suffer the static discharge phenomenon caused, and more and more littler process, and thinner gate oxide thickness all makes integrated circuit be subjected to the probability that static discharge destroys to be increased greatly.Therefore, the reliability of improving integrated circuit electrostatic discharge protection has very important effect to the rate of finished products that improves product.
The pattern of static discharge phenomenon is divided into four kinds usually: HBM (human body discharge mode), MM (machine discharge mode), CDM (assembly charging and discharging pattern) and electric field induction pattern (FIM).And the most common two kinds of static discharge patterns that also are the industrial quarters product must pass through are HBM and MM.When static discharge took place, electric charge flowed into and flows out from the another pin from a pin of chip usually, and the electric current that this moment, electrostatic charge produced is usually up to several amperes, and the voltage that produces at the electric charge input pin is up to several volts even tens volts.Can cause the damage of inside chip if bigger ESD electric current flows into inside chip, simultaneously, the high pressure that produces at input pin also can cause internal components generation grid oxygen punch-through, thereby causes circuit malfunction.Therefore, damaged by ESD, all will carry out effective ESD protection, the ESD electric current is released each pin of chip in order to prevent inside chip.
Under the normal operating conditions of integrated circuit, electrostatic discharge protection component is to be in closing state, can not influence the current potential on the input and output pin.And externally static pours into integrated circuit and when producing moment high-tension, this device can be opened conducting, emits electrostatic induced current rapidly.
ESD protection design not only will be protected inside chip; also to guarantee not the operate as normal of chip is exerted an influence; promptly only when ESD arrives; ESD safeguard structure unlatching work; and need to guarantee that the ESD safeguard structure can not open work under circuit input/output signal, situation about normally powering on, otherwise latch-up will take place.In addition, ESD protection design will reduce the influence to circuit performance as far as possible, reducing of parasitic capacitance for example, the reducing etc. of static leakage current.
As shown in Figure 1, as a kind of ESD safeguard structure commonly used, in the prior art, the controllable silicon that coupling capacitance triggers is made of coupling circuit and controllable silicon, controllable silicon comprises P type substrate and N trap, wherein, be provided with a P+ injection region, a N+ injection region and P+ trigger end on the P type substrate successively, be provided with the 2nd P+ injection region and the 2nd N+ injection region on the N trap successively, triggering signal produces circuit and comprises an electric capacity and the coupling circuit that the resistance series connection constitutes, and is used to export the reactor that this coupling circuit generates signal.The controllable silicon that above-mentioned coupling capacitance triggers is widely used in the protection of integrated circuit die I/O port and power domain.The controllable silicon that coupling capacitance triggers has advantages such as conducting is even, trigger voltage is adjustable.But because the metal-insulating layer-metal capacitor structure that adopts is as coupling capacitance usually, area is very big when obtaining suitable capacitance, is not suitable for the design of integrated circuit (IC) chip electrostatic defending.In order to reduce capacity area, usually adopt the higher mos capacitance (grid oxygen electric capacity) of unit-area capacitance efficient as coupling capacitance, but along with constantly reducing of integrated circuit (IC) chip manufacturing process size, measure of precision continues to increase, because the attenuate of gate oxide, cause the static leakage problem of mos capacitance in the controllable silicon that capacitive coupling triggers more and more serious, need improve existing capacitive coupling at leakage problem and trigger structure.
Summary of the invention
The invention provides a kind of coupling capacitance and trigger silicon-controlled device, simple in structure, have low static leakage, be a kind of electrostatic discharge protection component with high reliability and low speed paper tape reader static power disspation.
A kind of coupling capacitance triggers silicon-controlled device, is made of triggering signal generation circuit and controllable silicon; Wherein, described controllable silicon comprises P type substrate and N trap for the controllable silicon of band trigger end, wherein, is provided with a P+ injection region, a N+ injection region and P+ trigger end on the P type substrate successively, is provided with the 2nd P+ injection region and the 2nd N+ injection region on the N trap successively; Described P+ trigger end is near the boundary of described P type substrate and N trap, and described the 2nd P+ injection region is near the boundary of described P type substrate and N trap; A described P+ injection region and a N+ injection region connect electrical cathode, and described the 2nd P+ injection region and the 2nd N+ injection region connect electrical anode;
Described triggering signal produces circuit and is made of PMOS pipe, polysilicon resistance, mos capacitance, NMOS pipe, first inverter and second inverter; Wherein, the source electrode of PMOS pipe connects electrical anode, the drain electrode of PMOS pipe connects the upper end of polysilicon resistance and the input of first inverter, the output of first inverter then connects the grid of PMOS pipe and the grid of NMOS pipe, the lower end of polysilicon resistance connects the anode of mos capacitance, the input of second inverter and the drain electrode of NMOS pipe respectively, and the source electrode of NMOS pipe connects electrical cathode with the negative electrode of mos capacitance; The output of described second inverter links to each other with P+ trigger end in the described controllable silicon.
Because between 0.1～0.2 microsecond, therefore, there is the time-delay of 0.1～0.2 microsecond in the ESD signal that the triggering signal of second inverter output and anode produce to the width of esd pulse usually.Because the value of this time-delay is the product of the capacitance of the resistance of polysilicon resistance and mos capacitance, so the product of polysilicon resistance value and mos capacitance value is 0.1～0.2 microsecond.The resistance of preferred polysilicon resistance is 20 kilo-ohms, and the capacitance of mos capacitance is 5 pico farads.
Among the present invention, triggering signal produces circuit and is made of PMOS pipe, polysilicon resistance, mos capacitance, NMOS pipe and two inverters, wherein PMOS pipe, polysilicon resistance and mos capacitance are formed the capacitive coupling loop, and the source electrode of PMOS pipe connects electrical anode, and the negative electrode of mos capacitance connects electrical cathode.The NMOS pipe is connected in parallel on the two ends of mos capacitance, as the capacitance charge path of releasing.The output termination PMOS pipe of first inverter and the grid of NMOS pipe are used to control the unlatching of PMOS pipe and NMOS pipe, and the PMOS pipe and first inverter are formed ESD signal recognition structure.The lower end of polysilicon resistance connects second inverter in addition, and the output of second inverter produces the triggering signal output of circuit as whole triggering signal.
In addition, be different from the controllable silicon commonly used and open by the PN junction reverse breakdown of N trap and P type substrate, among the present invention, controllable silicon itself has triggering signal incoming end (P+ trigger end), and controllable silicon pours into trigger current by triggering signal generation circuit to the P+ trigger end on the P type substrate and realizes opening.
Coupling capacitance of the present invention triggers silicon-controlled device, utilize mos capacitance to trigger the silicon controlled capacitor cell as coupling capacitance, reduced area greatly than common metal electric capacity, simultaneously provide a kind of ESD recognition mechanism at the static leakage problem of mos capacitance under the small size deep submicron process, utilize triggering signal to produce circuit output triggering signal enough controllable silicon firing currents are provided, realize the difference of esd pulse and the normal power on signal of circuit; By producing the PMOS switch that circuit is provided with the identification esd pulse in triggering signal, break trigger signal generating circuit and power supply is connected under the circuit normal operation, be connected with power supply and provide enough trigger currents to open controllable silicon and when ESD arrives, triggering signal produced circuit, thereby reach the purpose that reduces the capacitance coupling circuit static leakage, realized the dynamic safeguard function of ESD.The present invention is simple in structure, and electric current is even, and the device robustness is good, and is reliable and stable.
Compare the traditional capacitance coupling and trigger SCR structure dependence metal level electric capacity, adopt the mos capacitance pipe more to save area among the present invention, and solved the leakage problem of mos capacitance pipe under circuit operate as normal bias voltage as coupling capacitance.
Description of drawings
Fig. 1 is the schematic diagram of the silicon-controlled device that triggers of conventional capacitive coupling;
Fig. 2 is the schematic diagram that coupling capacitance of the present invention triggers silicon-controlled device;
Fig. 3 is the schematic diagram of the SCR structure of the band trigger end among Fig. 2;
Fig. 4 is the circuit simulation result that coupling capacitance of the present invention triggers silicon-controlled device.
Embodiment
Describe the present invention in detail below in conjunction with embodiment and accompanying drawing, but the present invention is not limited to this.As shown in Figures 2 and 3, a kind of coupling capacitance triggers silicon-controlled device, is made of triggering signal generation circuit and controllable silicon 27.
Wherein, controllable silicon 27 is the controllable silicon of band trigger end, comprise P type substrate 31 and N trap 32, be provided with a P+ injection region 33, a N+ injection region 34 and P+ trigger end 37 on the P type substrate 31 successively, be provided with the 2nd P+ injection region 35 and the 2nd N+ injection region 36 on the N trap 32 successively; P+ trigger end 37 is near the boundary of P type substrate 31 and N trap 32, and the 2nd P+ injection region 35 is near the boundary of P type substrate 31 and N trap 32; The one a P+ injection region 33 and a N+ injection region 34 connect electrical cathode, and the 2nd P+ injection region 35 and the 2nd N+ injection region 36 connect electrical anode;
Wherein, triggering signal generation circuit is made of PMOS pipe 21, polysilicon resistance 22, mos capacitance 23, NMOS pipe 24, first inverter 25 and second inverter 26; Wherein, the source electrode of PMOS pipe 21 connects electrical anode, the drain electrode of PMOS pipe 21 connects the upper end of polysilicon resistance 22 and the input of first inverter 25, the output of first inverter 25 then connects the grid of PMOS pipe 21 and the grid of NMOS pipe 24, the lower end of polysilicon resistance 22 connects the anode of mos capacitance 23, the input of second inverter 26 and the drain electrode of NMOS pipe 24 respectively, and the source electrode of NMOS pipe 24 connects electrical cathode with the negative electrode of mos capacitance 23; The output of second inverter 26 links to each other with P+ trigger end 37 in the controllable silicon 27.
Above-mentioned P type substrate, N trap, P+ trigger end, N+, P+ injection region structure and PMOS, NMOS, polysilicon resistance, inverter and mos capacitance pipe all can adopt existing standard CMOS integrated circuit fabrication process to realize.
Above-mentioned coupling capacitance triggers in the silicon-controlled device, utilizes and can open the silicon controlled principle to the base injection current of parasitic triode in the controllable silicon 27, realizes being opened by outer contacting Power Generation Road control controllable silicon.
In the controllable silicon 27 of band trigger end, be connected as electrical cathode with a P+ injection region 33 usefulness metal wires by a N+ injection region 34.Electrical anode is made in the 2nd N+ injection region 36 and the 2nd P+ injection region 35.After anode produced the ESD signal, the esd pulse waveform was managed the drain electrode of 21 lower ends and is produced the high level current potential through being coupling in PMOS, and this high level oppositely produces low level signals at the grids of PMOS pipe 21 through first inverter 25, makes PMOS pipe 21 open the conducting electric currents.After PMOS manages 21 conductings, because the delay effect of below polysilicon resistance 22 and mos capacitance 23, the esd pulse that anode produces can be just at the coupling output after certain time-delay, just the upper end of the lower end of polysilicon resistance 22, mos capacitance 23 produces pulse signal, and the concrete value of this time-delay is the product of the capacitance of the resistance of polysilicon resistance and mos capacitance.Final pulse signal offers the trigger end of controllable silicon 27 through second inverter, 26 output driving currents.
Because the width of esd pulse is usually between 0.1～0.2 microsecond, therefore, this time-delay is generally 0.1～0.2 microsecond, is 0.1～0.2 microsecond so get the product of polysilicon resistance value and mos capacitance value, for example: the resistance of polysilicon resistance is 20 kilo-ohms, and the capacitance of mos capacitance is 5 pico farads.
After the trigger current of second inverter 26 output is accepted in the base of NPN pipe in the parasitic triode in the controllable silicon 27, because the positive feedback effect of parasitic NPN pipe and PNP pipe in the controllable silicon is opened and the ESD electric currents of releasing controllable silicon 27.
Fig. 4 is the transient state simulation result that above-mentioned coupling capacitance triggers the circuit of silicon-controlled device, four curves are respectively among Fig. 4: be used to simulate the square-wave signal of esd pulse, through being coupling in the time delayed signal that PMOS manages high level voltage that 21 lower ends drain electrodes produces, produced by polysilicon resistance 22 and mos capacitance 23 couplings, the output signal of second inverter.Shown in the 4th curve of Fig. 4, above-mentioned coupling capacitance triggers in the silicon-controlled device, triggering signal generation circuit can produce the above trigger current of about 70mA provides controllable silicon to open (the 4th curve is the second inverter output current), compare conventional controllable silicon 20mA less than the trigger current demand, the trigger current that this triggering signal produces circuit to be provided is enough to open fast the controllable silicon ESD electric current of releasing.
Whole controllable silicon 27 is opened and the process of the ESD electric current of releasing and the electric current unlatching work that unconventional controllable silicon relies on the reverse avalanche breakdown of PN junction, but the trigger current that relies on the outer contacting Power Generation Road to provide comes unlatching work, being the influence whether unlatching of ESD safeguard structure is not subjected to ESD device self structure, is a kind of ESD protection mode of active.
Claims (3)
1. a coupling capacitance triggers silicon-controlled device, produce circuit and controllable silicon (27) formation by triggering signal, described controllable silicon (27) comprises P type substrate (31) and N trap (32), wherein, be provided with a P+ injection region (33), a N+ injection region (34) and P+ trigger end (37) on the P type substrate (31) successively, be provided with the 2nd P+ injection region (35) and the 2nd N+ injection region (36) on the N trap (32) successively; Described P+ trigger end (37) is near the boundary of described P type substrate (31) and N trap (32), and described the 2nd P+ injection region (35) is near the boundary of described P type substrate (31) and N trap (32); A described P+ injection region (33) and a N+ injection region (34) connect electrical cathode, and described the 2nd P+ injection region (35) and the 2nd N+ injection region (36) connect electrical anode, it is characterized in that:
Described triggering signal produces circuit and is made of PMOS pipe (21), polysilicon resistance (22), mos capacitance (23), NMOS pipe (24), first inverter (25) and second inverter (26); Wherein, the source electrode of PMOS pipe (21) connects electrical anode, the drain electrode of PMOS pipe (21) connects the upper end of polysilicon resistance (22) and the input of first inverter (25), the output of first inverter (25) then connects the grid of PMOS pipe (21) and the grid of NMOS pipe (24), the lower end of polysilicon resistance (22) connects the anode of mos capacitance (23), the input of second inverter (26) and the drain electrode of NMOS pipe (24) respectively, and the source electrode of NMOS pipe (24) connects electrical cathode with the negative electrode of mos capacitance (23); The output of described second inverter (26) links to each other with P+ trigger end (37) in the described controllable silicon (27).
2. coupling capacitance as claimed in claim 1 triggers silicon-controlled device, and it is characterized in that: the product of the capacitance of the resistance of described polysilicon resistance (22) and mos capacitance (23) is 0.1～0.2 microsecond.
3. coupling capacitance as claimed in claim 1 or 2 triggers silicon-controlled device, and it is characterized in that: the resistance of described polysilicon resistance (22) is 20 kilo-ohms, and the capacitance of described mos capacitance (23) is 5 pico farads.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201010616239 CN102148241B (en) | 2010-12-30 | 2010-12-30 | Coupling-capacitor triggered silicon controlled device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201010616239 CN102148241B (en) | 2010-12-30 | 2010-12-30 | Coupling-capacitor triggered silicon controlled device |
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| CN102148241A true CN102148241A (en) | 2011-08-10 |
| CN102148241B CN102148241B (en) | 2012-10-24 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102801146A (en) * | 2012-08-24 | 2012-11-28 | 北京大学 | Power clamp ESD (Electronic Static Discharge) protective circuit |
| CN111668209A (en) * | 2020-06-10 | 2020-09-15 | 电子科技大学 | Low-leakage silicon controlled rectifier for low-voltage ESD protection |
| CN111883596A (en) * | 2020-06-15 | 2020-11-03 | 东南大学 | MOS capacitor capable of reducing parasitic capacitance and optimization method |
| CN112289790A (en) * | 2020-11-30 | 2021-01-29 | 杰华特微电子（杭州）有限公司 | Multi-finger GGNMOS (grounded-gate bipolar transistor) device for ESD (electro-static discharge) protection circuit and manufacturing method thereof |
| CN117977518A (en) * | 2024-03-27 | 2024-05-03 | 杭州芯正微电子有限公司 | Substrate triggering type ESD protection circuit |
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| CN1918707A (en) * | 2004-02-13 | 2007-02-21 | 奥地利微系统股份公司 | Circuit arrangement and method for protecting an integrated semiconductor circuit |
| CN101030574A (en) * | 2006-03-02 | 2007-09-05 | 财团法人工业技术研究院 | High-voltage tolerant power-rail electrostatic discharge protection circuit for mixed-voltage i/o interface |
| CN101188237A (en) * | 2006-11-17 | 2008-05-28 | 上海华虹Nec电子有限公司 | Semiconductor anti-static protection structure |
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2010
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Patent Citations (5)
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| CN1404159A (en) * | 2001-08-30 | 2003-03-19 | 联华电子股份有限公司 | SCR with base triggering effect |
| CN1918707A (en) * | 2004-02-13 | 2007-02-21 | 奥地利微系统股份公司 | Circuit arrangement and method for protecting an integrated semiconductor circuit |
| US20060209478A1 (en) * | 2005-03-17 | 2006-09-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102801146A (en) * | 2012-08-24 | 2012-11-28 | 北京大学 | Power clamp ESD (Electronic Static Discharge) protective circuit |
| CN111668209A (en) * | 2020-06-10 | 2020-09-15 | 电子科技大学 | Low-leakage silicon controlled rectifier for low-voltage ESD protection |
| CN111668209B (en) * | 2020-06-10 | 2022-03-15 | 电子科技大学 | Low-leakage silicon controlled rectifier for low-voltage ESD protection |
| CN111883596A (en) * | 2020-06-15 | 2020-11-03 | 东南大学 | MOS capacitor capable of reducing parasitic capacitance and optimization method |
| CN112289790A (en) * | 2020-11-30 | 2021-01-29 | 杰华特微电子（杭州）有限公司 | Multi-finger GGNMOS (grounded-gate bipolar transistor) device for ESD (electro-static discharge) protection circuit and manufacturing method thereof |
| CN117977518A (en) * | 2024-03-27 | 2024-05-03 | 杭州芯正微电子有限公司 | Substrate triggering type ESD protection circuit |
| CN117977518B (en) * | 2024-03-27 | 2024-06-04 | 杭州芯正微电子有限公司 | Substrate triggering type ESD protection circuit |
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