CN112289790A - Multi-finger GGNMOS (grounded-gate bipolar transistor) device for ESD (electro-static discharge) protection circuit and manufacturing method thereof - Google Patents
Multi-finger GGNMOS (grounded-gate bipolar transistor) device for ESD (electro-static discharge) protection circuit and manufacturing method thereof Download PDFInfo
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits
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Abstract
The invention provides a multi-finger GGNMOS device for an ESD protection circuit, which comprises a substrate; the device comprises a device area formed on a substrate, wherein the device area comprises a plurality of NMOS devices, a body wiring area positioned on one side of the device area, and a strip-shaped polycrystalline silicon resistor positioned outside the device area, wherein a grid electrode of each NMOS device is connected to different positions of the strip-shaped polycrystalline silicon resistor, and the grid electrode grounding resistance of the NMOS device closer to the body wiring area is larger. The grid electrode of each parasitic NPN tube is connected to different positions of the strip-shaped polycrystalline silicon resistor to obtain different resistors, the RC coupling under the ESD pulse is utilized to lift up the grid electrode voltage, different channel currents are provided to compensate and assist in triggering the GGNMOS, and when electrostatic discharge occurs, each insertion finger in the GGNMOS can be simultaneously started. The invention also provides a manufacturing method of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a multi-finger GGNMOS (grounded-gate bipolar transistor) device for an ESD (electro-static discharge) protection circuit and a manufacturing method thereof.
Background
Electrostatic Discharge (ESD) should be the major cause of damage to all electronic components or integrated circuit systems due to Electrical Overstress (EOS). Because static electricity is typically very high in transient voltage (> several kilovolts), such damage is destructive and permanent, causing direct circuit burn-out. Statistics of National-Semiconductor data indicate that 38% of today's integrated circuit failure products are caused by ESD/EOS.
In conventional designs, grounded gate field effect transistors (GGNMOS) are often used as ESD protection devices, which are compatible with most CMOS processes. In the prior art, each pin is subjected to ESD protection by using a field effect transistor (GGNMOS) with a grounded grid electrode, avalanche breakdown is mainly generated by an N +/P-Well junction of a drain terminal, and then a parasitic NPN triode is started and discharges ESD current due to voltage drop generated by current of the avalanche breakdown on a Well resistor.
Referring to fig. 1 and 2, a conventional GGNMOS transistor for ESD protection is shown. As shown in the device layout of fig. 2, the GGNMOS device is formed on a P-type semiconductor silicon substrate 10 ' having a Gate (Gate)14 ' and N-doped Source (Source)11 ' and Drain (Drain)12 ' on either side of the Gate, and a body terminal 13 '. The drain 12 'is connected to an I/O port (Anode), the gate 14', source 11 'and body 13' are connected to ground (Cathode), and the drain 12 'is in contact with a silicide Block 15' (shown in dashed lines) between the polysilicon gate and the contact hole. When the protected internal circuit is in a normal working state, the voltage on the I/O is not enough to enable the reverse PN junction formed by the N + injection region of the drain terminal and the P-Well to generate avalanche breakdown because the grid electrode of the GGNMOS is grounded, so that the GGNMOS belongs to a turn-off state. When the anode of the GGNMOS is subjected to positive ESD stress, the voltage of the drain terminal rises until avalanche breakdown occurs at the N +/P-Well junction of the drain terminal, and then the parasitic NPN triode is turned on and discharges ESD current due to the voltage drop generated by the current of the avalanche breakdown on the Well resistor.
In practical applications, to protect higher ESD pulses and save ESD device area, a multi-finger GGNMOS is often used for protection. As shown in fig. 3, a cross-sectional view of a conventional GGNMOS is shown. In the device region of the GGNMOS, a plurality of NMOS devices are included, a source S and a gate G in each NMOS device are grounded, a body (body) P + is also grounded, and resistances formed between a parasitic NPN transistor formed between each pair of the source S and the drain D and the body region are R1, R2, R3, and R4, respectively, where the parasitic NPN transistor formed between each pair of the source S and the drain D is one finger (finger). Due to the different distances between each parasitic NPN tube and the body region, the parasitic well resistances R1, R2, R3, and R4 are also different. R1 < R2 < R3 < R4, i.e., the longer the distance, the greater the resistance value of the resistor formed. When the static pulse comes, the parasitic NPN far away from the body region has the largest trap resistance (R4), so that the voltage drop can reach 0.7V by a small BV current, the GGNMOS is turned on and enters hysteresis, other insertion fingers are turned on slowly or even cannot be turned on, and the ESD performance of the device is reduced.
In CN102315217, a solution to the above problem is given. In the patent, an N-well resistor is introduced into two adjacent parasitic NPN transistors, and the resistance of the well region in the adjacent NPN transistors is balanced by adjusting the magnitude of the N-well resistor, so that the two NPN transistors can be turned on simultaneously. However, this solution has the following technical drawbacks: 1. due to the fact that the N well needs to be made deep, junction depletion is increased, avalanche breakdown voltage is increased, for the current MOS tube process, the grid oxide tends to be made thin continuously, and the excessive avalanche voltage preferentially breaks down the grid oxide to damage the device. 2. The scheme is relatively reliable when the resistance of the adjacent NPN tubes is adjusted, but when the number of the parasitic NPN tubes reaches 3 or more than 3, the method can not control the resistance adjustment of the non-adjacent NPN tubes, so that the problem of poor opening uniformity still exists.
Disclosure of Invention
Accordingly, the present invention is directed to a multi-finger GGNMOS device for ESD protection circuits. The grid electrode of each parasitic NPN tube is connected to different positions of the strip-shaped polycrystalline silicon resistor by introducing the strip-shaped polycrystalline silicon resistor to the grounding position of the device, so that different resistors are obtained, the grid electrode voltage is raised by RC coupling under ESD pulse, different channel currents are provided to compensate and trigger the GGNMOS, and when electrostatic discharge occurs, each insertion finger in the GGNMOS can be simultaneously started.
The multi-finger GGNMOS device for the ESD protection circuit comprises a substrate;
a device region formed on the substrate, the device region including a plurality of NMOS devices, at least some of the NMOS devices sharing a drain, and a gate and a source of each of the NMOS devices being grounded,
a body terminal region on one side of the device region, the body terminal region being grounded through a lead-out wire,
a bar-shaped polysilicon resistor outside the device region, wherein the grid electrode of each NMOS device is connected with different positions of the bar-shaped polysilicon resistor, so that the grid electrode of each NMOS device has different grid grounding resistance, and the grid grounding resistance of the NMOS device closer to the body wiring region is larger,
when an ESD pulse comes, the grid grounding resistor and a parasitic capacitor in the NMOS device form RC coupling, so that the larger the grid grounding resistor is, the larger the pulling voltage of the grid is, the larger the compensation is performed on the starting voltage of the NMOS device, and the starting time of each NMOS device is balanced.
Preferably, the widths of the stripe-shaped polysilicon resistors are varied in a gradient manner according to distances from the body terminal region, wherein the narrower the portion closer to the body terminal region, the wider the portion farther from the body terminal region.
Preferably, the width variation of the strip-shaped polysilicon resistor is nonlinear, so that the resistance value of the gate grounding resistor connected to each NMOS device is matched with the turn-on voltage of the NMOS device, thereby synchronizing the start time of each NMOS device.
Preferably, the strip-shaped polysilicon resistors have non-linear length variation in an access section between the respective NMOS device access points.
Preferably, the access section is bent, and the bent setting enables the resistance value of the gate grounding resistor accessed by each NMOS device to be matched with the turn-on voltage of the NMOS device, so as to synchronize the start time of each NMOS device.
Preferably, the gate of the NMOS device is a polysilicon gate, and each polysilicon gate is connected to the polysilicon resistor through a conductive metal layer.
Preferably, a field oxide layer isolation or a shallow trench isolation is arranged between the body wiring region and the device region.
The preparation method of the multi-finger GGNMOS device for the ESD protection circuit comprises the following steps
Providing a substrate;
defining a device region and a body terminal region on the substrate, and defining a drain region, a source region and a gate region of each NMOS device in the device region;
doping regions of corresponding conductivity types required for forming the drain region, the source region and the body terminal region;
sequentially manufacturing a gate oxide layer and a polysilicon gate on the gate region, and manufacturing a strip-shaped polysilicon resistor in a synchronous process for manufacturing the polysilicon gate, wherein the strip-shaped polysilicon resistor is positioned outside the device region;
forming a conductive metal layer on each polysilicon gate, so that the gate of each NMOS device is connected to the strip-shaped polysilicon resistor;
respectively connecting an electric outgoing line to the body wiring region, the drain region, the source region and the strip-shaped polycrystalline silicon resistor, grounding one end of the body wiring region, the source region and the strip-shaped polycrystalline silicon resistor, which is far away from the body wiring region, to serve as a cathode, and connecting the drain region to a circuit to be protected to serve as an anode;
the grid of each NMOS device is connected to the strip-shaped polycrystalline silicon resistor and then has different grid grounding resistances, and the grid grounding resistance of the NMOS device closer to the body wiring region is larger.
Preferably, when the strip-shaped polysilicon resistor is manufactured, the strip-shaped polysilicon resistor is subjected to a patterning process, so that the width of the strip-shaped polysilicon resistor is in gradient change according to the distance from the body wiring region, wherein the narrower the part closer to the body wiring region is, the wider the part farther from the body wiring region is.
Preferably, when the strip-shaped polycrystalline silicon resistor is manufactured, a patterning process is further performed on the strip-shaped polycrystalline silicon resistor, the access section of the strip-shaped polycrystalline silicon resistor between the access points of the NMOS devices is in a bent arrangement, and the bent arrangement enables the resistance value of the grid grounding resistor accessed by each NMOS device to be matched with the starting voltage of the NMOS device, so that the starting time of each NMOS device is synchronized.
According to the invention, the grounding resistor is introduced into the grid of the NMOS device, so that different NMOS devices have different grid grounding resistors, and the grid voltage is pulled up through the grid grounding resistor, thereby compensating the opening of the NMOS device. Compared with the prior art, the invention has the technical effects that:
1. the grid grounding resistor is arranged outside the device region, and each well region in the device is not required to be doped, so that the manufacturing process is simple, and the ESD protection capability of the device is not influenced.
2. The method is not limited by the number of NMOS devices and is suitable for multi-finger GGNMOS devices.
3. The polysilicon resistor can be subjected to graphical processing, and the length or the width of the polysilicon resistor is designed according to the matching of the starting voltage of each NMOS device, so that each NMOS device can be started more uniformly.
Drawings
Fig. 1 is a top view of a conventional grounded gate fet.
Fig. 2 is a sectional view of fig. 1.
Fig. 3 is a cross-sectional view of a conventional multi-finger GGNMOS device.
Fig. 4 is a cross-sectional view of a multi-finger GGNMOS device according to a first embodiment of the present invention.
Fig. 5 is a top view of a multi-finger GGNMOS device in accordance with the first embodiment.
Fig. 6 is a flowchart of a method for manufacturing a multi-finger GGNMOS device according to the first embodiment.
Fig. 7 is a top view of a GGNMOS device of the second embodiment.
Fig. 8 is a top view of a GGNMOS device of the third embodiment.
Detailed Description
The present invention will be described in detail with reference to the specific embodiments shown in the drawings, which are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the specific embodiments are included in the scope of the present invention.
Hereinafter, the technical solution of the present invention will be described in detail with reference to the specific embodiments. It should be noted that, since the MOS transistor is divided into a P-type transistor and an N-type transistor, which are distinguished by carrier types, and although the operation characteristics are different, the operation principle of the MOS transistor for realizing the function is basically the same, in the following embodiments, an N-type junction field effect transistor is taken as an example, where the P-type dopant is used as the first conductivity type semiconductor and the N-type dopant is used as the second conductivity type semiconductor. The P-type tube (i.e. GGPMOS) can be used for reverse ESD current, and corresponding adjustment can be made on the basis of the idea of the patent.
First embodiment
Referring to fig. 4 and 5, fig. 4 is a schematic cross-sectional view of a multi-finger GGNMOS device according to a first embodiment of the present invention, and fig. 5 is a top view of the device. As shown in the figure, in this embodiment, the multi-finger GGNMOS device includes a P-type substrate 10, a device region 11 formed on the P-type substrate 10, and a plurality of NMOS devices included in the device region 11, each having an N-type heavily doped drain 111 and source 113, with a channel and gate region 112 between the drain 111 and source 113. At least some of the NMOS devices share a drain 111, and the gate 112 and source 113 of each of the NMOS devices are grounded. In the embodiment shown in the figure, two NMOS devices on the left half share the drain 111, and two NMOS devices on the right half share the drain 111, so that a total of 4 NMOS devices are formed.
A body wiring region (P-body)12 is arranged on one side of the device region 11, the body wiring region (P-body)12 is a heavily doped P + type well region, and the body wiring region 12 is grounded through a leading-out wire. Between the body terminal region 12 and the device region, an isolation 14 is provided, which isolation 14 may be a field oxide isolation or a shallow trench isolation.
Referring to fig. 4 again, 4 parasitic NPN transistors are formed inside the four NMOS devices, and since the body connection region 12 is disposed at one side of the device region 11, the distances between each parasitic NPN transistor and the body connection region 12 are different, which results in different well resistances (corresponding to the resistances R1, R2, R3, and R4 connected to the base in the parasitic NPN transistors) in the respective NMOS devices, and the resistance of the well resistance increases with increasing distance. Therefore, when the ESD current is injected into the device and avalanche breakdown occurs, for the NMOS device with larger well resistance, a smaller current can generate a larger well voltage, and finally, the time for each parasitic NPN transistor to reach the starting voltage (0.7 v) is inconsistent.
Referring to fig. 5, in the present invention, in order to compensate for the activation voltage of the NMOS device with a smaller well resistance, a strip-shaped polysilicon resistor 13 is disposed outside the device region 11, and the gate 112 of each NMOS device is connected to different positions of the strip-shaped polysilicon resistor 13, so that the gate 112 of each NMOS device has a different gate grounding resistance, and the gate grounding resistance of the NMOS device closer to the body connection region 12 is larger, such as resistors 131, 132, 133, and 134 shown in the figure, wherein the length of the NMOS device corresponding to the resistor 134 connected to the polysilicon resistor 13 is longest as the NMOS device is closer to the body connection region 12, and therefore has the largest gate grounding resistance. Therefore, when an ESD pulse comes temporarily, the gate grounding resistor and the parasitic capacitor in the NMOS device form RC coupling, the gate voltage at the initial moment is raised by the gate grounding resistor, the higher the resistance value is, the higher the raised voltage is, the gate voltage enables channel carriers in the parasitic NMOS device to be increased, and the current in a channel is compensated, so that the time for the NMOS device to be conducted is shortened, and the equivalent to the indirect compensation of the starting voltage of the device is realized. And the larger the resistance is, the larger the compensated current is, the faster the device is turned on, so that the originally inconsistent starting time of each NMOS device is adjusted to be basically consistent, thereby balancing the starting time of each NMOS device in the multi-finger GGNMOS device and improving the integral ESD protection capability.
Referring again to fig. 5, the gates 12 of the NMOS devices are polysilicon gates, which are arranged in parallel and long strips. For convenience of access, the strip-shaped polysilicon resistor 13 is arranged near one end of the polysilicon gate, so that each polysilicon gate can be accessed to different positions of the polysilicon resistor 13 through the conductive metal layer.
Next, a method of manufacturing a multi-finger GGNMOS device according to the first embodiment will be described. Referring to fig. 6, fig. 6 is a flowchart of a method for manufacturing a multi-finger GGNMOS device according to the first embodiment, where as shown in the figure, the method includes the steps of:
s1, providing a substrate, which is a P-type substrate in this embodiment.
S2, defining a device area and a body terminal area on the substrate, and defining a drain area, a source area and a gate area of each NMOS device in the device area. And determining the region of each device to be manufactured through layout design so as to implement the following processes of doping, photoetching and the like.
S3, doping regions of corresponding conductivity types required to form the drain, source and body terminal regions. Taking an NMOS device as an example, when a drain region and a source region are fabricated, N-type ions need to be heavily doped on a P-type well to form an N + well. In the body terminal region, the P-type ions are required to be heavily doped to form a P + well.
S4, sequentially manufacturing a gate oxide layer and a polysilicon gate on the gate region, and manufacturing a strip-shaped polysilicon resistor in the synchronous process of manufacturing the polysilicon gate, wherein the strip-shaped polysilicon resistor is positioned outside the device region. In the step, because the grid electrode of each NMOS device adopts polysilicon, the NMOS device and the polysilicon resistor can be manufactured in one process, and only a photomask with a corresponding pattern needs to be designed.
And S5, forming a conductive metal layer on each polysilicon gate, and enabling the gate of each NMOS device to be connected to the strip-shaped polysilicon resistor.
And S6, finally, respectively connecting electric outgoing lines to the body wiring region, the drain region, the source region and the strip-shaped polycrystalline silicon resistor, grounding one ends of the body wiring region, the source region and the strip-shaped polycrystalline silicon resistor, which are far away from the body wiring region, as cathodes, and connecting the drain region to a circuit to be protected as an anode.
The grid of each NMOS device is connected to the strip-shaped polycrystalline silicon resistor and then has different grid grounding resistances, and the grid grounding resistance of the NMOS device closer to the body wiring region is larger.
Example 2
Referring to fig. 7, fig. 7 is a top view of a multi-finger GGNMOS device according to a second embodiment of the present invention. In the first embodiment, the polysilicon resistors are designed in a stripe shape with the same width, in this scheme, although the purpose of equalizing the starting time of each NMOS device can be achieved by connecting gate grounding resistors with different resistance values. However, the strip design with the same width leads the resistance value of the polysilicon resistor to be completely dependent on the access length and lack of variation. Therefore, under the condition that the positions of all the polysilicon gates are determined, the accessed polysilicon resistors can hardly be completely matched with the resistor requirements required by consistent starting time of all the NMOS devices. Which is detrimental to the overall control of the device. In the second embodiment, therefore, a strip-shaped design of unequal width is used. As shown in fig. 7, the width of the strip-shaped polysilicon resistors 15 varies in a gradient manner as it goes from the body terminal area to the body terminal area, wherein the narrower the portion thereof that goes from the body terminal area, the wider the portion thereof that goes from the body terminal area. Therefore, the width can be controlled under the condition that the access length cannot be controlled, and the aim of adjusting the resistance value of the accessed polysilicon resistor is further fulfilled.
Preferably, the width of the strip-shaped polysilicon resistor changes nonlinearly, that is, the width does not change according to a certain rule, but according to the design requirement, for a resistor needing to be connected into a larger resistor, the width of the connection section can be relatively thinner than the design, and when a resistor needing to be connected into a smaller resistor, the width of the connection section can be relatively larger than the design. The actual resistance value requirement of the gate grounding resistor for different NMOS devices is not strictly in inverse relation only according to the length from a body access region, but is under the combined action of a plurality of factors such as well region impurity concentration, junction region depletion layer width, gate region electric field intensity and the like, so that after the factors are considered, the optimal polysilicon resistor design scheme is to design the width of each section of the accessed polysilicon resistor according to the resistance value required by the corresponding NMOS device, so that the resistance value of the gate grounding resistor accessed by each NMOS device is matched with the starting voltage of the NMOS device, and the starting time of each NMOS device is synchronized.
In this embodiment 2, in the corresponding manufacturing process, a special mask pattern is required to design the shape of the polysilicon resistor, that is, in the patterning process of the polysilicon resistor, the width of the strip-shaped polysilicon resistor is made to exhibit a gradient change according to the distance from the body wiring region, wherein the portion closer to the body wiring region is narrower, and the portion farther from the body wiring region is wider. And the specific width is preferably such that the resistance value of the resistor satisfies the start-up time of each NMOS device.
Example 3
Referring to fig. 8, fig. 8 is a top view of a multi-finger GGNMOS device according to a third embodiment of the present invention. As shown, in this embodiment, the adjustment of the resistance value of each accessed polysilicon is achieved by controlling the lengths of different access points. Specifically, each access segment of the polysilicon resistor 16 is arranged in a curved manner, and if the resistor to be accessed is larger, the curved radian or curved stroke is increased to increase the resistance value of the segment, and conversely, the curved radian or stroke is decreased. The bending arrangement enables the resistance value of the grid grounding resistor connected to each NMOS device to be matched with the starting voltage of the NMOS device, so that the starting time of each NMOS device is synchronized.
Similarly, in the embodiment, in the corresponding manufacturing process, a special mask pattern is required to design the shape of the polysilicon resistor, that is, in the patterning process of the polysilicon resistor, the access section of the strip-shaped polysilicon resistor between the access points of the NMOS devices is bent, and the bent setting enables the resistance value of the gate ground resistor accessed by each NMOS device to be matched with the turn-on voltage of the NMOS device, so as to synchronize the start time of each NMOS device.
Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
Claims (10)
1. A multi-finger GGNMOS device for ESD protection circuit is characterized in that: comprises that
A substrate;
a device region formed on the substrate, the device region including a plurality of NMOS devices, at least some of the NMOS devices sharing a drain, and a gate and a source of each of the NMOS devices being grounded,
a body terminal region on one side of the device region, the body terminal region being grounded through a lead-out wire,
a bar-shaped polysilicon resistor outside the device region, wherein the grid electrode of each NMOS device is connected with different positions of the bar-shaped polysilicon resistor, so that the grid electrode of each NMOS device has different grid grounding resistance, and the grid grounding resistance of the NMOS device closer to the body wiring region is larger,
when an ESD pulse comes, the grid grounding resistor and a parasitic capacitor in the NMOS device form RC coupling, so that the larger the grid grounding resistor is, the larger the pulling voltage of the grid is, the larger the compensation is performed on the starting voltage of the NMOS device, and the starting time of each NMOS device is balanced.
2. The multi-finger GGNMOS device for ESD protection circuitry of claim 1, wherein: the width of the strip-shaped polycrystalline silicon resistor is changed in a gradient manner according to the distance from the body wiring region, wherein the part closer to the body wiring region is narrower, and the part farther from the body wiring region is wider.
3. The multi-finger GGNMOS device for ESD protection circuitry of claim 2, wherein: the width change of the strip-shaped polycrystalline silicon resistor is nonlinear, so that the resistance value of the grid grounding resistor connected to each NMOS device is matched with the starting voltage of the NMOS device, and the starting time of each NMOS device is synchronized.
4. The multi-finger GGNMOS device for ESD protection circuitry of claim 1, wherein: the strip-shaped polysilicon resistors have nonlinear length variation in access sections between the NMOS device access points.
5. The multi-finger GGNMOS device for ESD protection circuitry of claim 4, wherein: the access section is in a bent arrangement, and the bent arrangement enables the resistance value of the grid grounding resistor accessed by each NMOS device to be matched with the starting voltage of the NMOS device so as to synchronize the starting time of each NMOS device.
6. The multi-finger GGNMOS device for ESD protection circuitry of claim 1, wherein: the grid of the NMOS device is a polysilicon gate, and each polysilicon gate is connected to the polysilicon resistor through a conductive metal layer.
7. The multi-finger GGNMOS device for ESD protection circuitry of claim 1, wherein: and field oxide layer isolation or shallow trench isolation is arranged between the body wiring region and the device region.
8. A method of manufacturing a multi-finger GGNMOS device for ESD protection circuitry as claimed in any one of claims 1-7, wherein: comprises that
Providing a substrate;
defining a device region and a body terminal region on the substrate, and defining a drain region, a source region and a gate region of each NMOS device in the device region;
doping regions of corresponding conductivity types required for forming the drain region, the source region and the body terminal region; sequentially manufacturing a gate oxide layer and a polysilicon gate on the gate region, and manufacturing a strip-shaped polysilicon resistor in a synchronous process for manufacturing the polysilicon gate, wherein the strip-shaped polysilicon resistor is positioned outside the device region;
forming a conductive metal layer on each polysilicon gate, so that the gate of each NMOS device is connected to the strip-shaped polysilicon resistor;
respectively connecting an electric outgoing line to the body wiring region, the drain region, the source region and the strip-shaped polycrystalline silicon resistor, grounding one end of the body wiring region, the source region and the strip-shaped polycrystalline silicon resistor, which is far away from the body wiring region, to serve as a cathode, and connecting the drain region to a circuit to be protected to serve as an anode;
the grid of each NMOS device is connected to the strip-shaped polycrystalline silicon resistor and then has different grid grounding resistances, and the grid grounding resistance of the NMOS device closer to the body wiring region is larger.
9. The method of claim 8, wherein: when the strip-shaped polycrystalline silicon resistor is manufactured, a patterning process is further carried out on the strip-shaped polycrystalline silicon resistor, so that the width of the strip-shaped polycrystalline silicon resistor is in gradient change according to the distance from the strip-shaped polycrystalline silicon resistor to the body wiring region, wherein the part closer to the body wiring region is narrower, and the part farther from the body wiring region is wider.
10. The method of claim 8, wherein: when the strip-shaped polycrystalline silicon resistor is manufactured, a patterning process is further carried out on the strip-shaped polycrystalline silicon resistor, the strip-shaped polycrystalline silicon resistor is in a bent arrangement at an access section between the access points of the NMOS devices, and the bent arrangement enables the resistance value of the grid grounding resistor accessed by each NMOS device to be matched with the starting voltage of the NMOS device so as to synchronize the starting time of each NMOS device.
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| US5581105A (en) * | 1994-07-14 | 1996-12-03 | Vlsi Technology, Inc. | CMOS input buffer with NMOS gate coupled to VSS through undoped gate poly resistor |
| US20040164354A1 (en) * | 2001-06-14 | 2004-08-26 | Sarnoff Corporation | Minimum-dimension, fully- silicided MOS driver and ESD protection design for optimized inter-finger coupling |
| US20030213995A1 (en) * | 2002-05-15 | 2003-11-20 | Charvaka Duvvury | Substrate pump ESD protection for silicon-on-insulator technologies |
| US20060033163A1 (en) * | 2003-10-01 | 2006-02-16 | Lsi Logic Corporation | I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process |
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