CN110912098B

CN110912098B - Circuit for preventing electrostatic discharge ESD protection from causing leakage current under power-off

Info

Publication number: CN110912098B
Application number: CN201911163570.1A
Authority: CN
Inventors: 刘万福
Original assignee: Nanjing Erxin Electronic Co ltd
Current assignee: Nanjing Erxin Electronic Co ltd
Priority date: 2019-11-25
Filing date: 2019-11-25
Publication date: 2021-08-24
Anticipated expiration: 2039-11-25
Also published as: CN110912098A

Abstract

The invention discloses a circuit for preventing electrostatic discharge ESD protection from causing leakage current under the condition of power supply turn-off, which comprises two switch circuits and a capacitor, wherein the two switch circuits are used for connecting input/output IO to a power supply end, and the first switch circuit is responsible for ensuring the reliable cut-off of a parasitic diode of an electrostatic discharge tube under the power supply turn-off mode. The second switch is responsible for disconnecting the substrate of the electrostatic discharge ESD tube from the power supply end. Under the condition that a power supply is turned off (pulled to the ground), a current path from an input signal end to the power supply is effectively prevented, and meanwhile, the electrostatic protection level is not influenced; when the power supply voltage returns to normal, the output swing of the input/output IO and the electrostatic discharge protection capability are not affected, and the performance of the circuit is ensured. The technology solves the problem that in system application, under the condition that partial module power is switched off, the device is damaged due to the fact that large current is generated from the input/output port IO of a module which is not switched off to the switching-off module, and the technology also truly realizes no electric leakage and has significant significance for low-power consumption application.

Description

Circuit for preventing electrostatic discharge ESD protection from causing leakage current under power-off

Technical Field

The invention relates to a digital and analog oriented integrated circuit, belonging to the technical field of circuits.

Background

Electrostatic discharge is a very common phenomenon, and is often generated in our daily life, but for an integrated circuit, an electrostatic discharge ESD process generally refers to an electrostatic discharge process with a duration of about 150ns caused by an external object contacting a certain connection point of a chip, and this process may generate very high transient current and transient voltage (several tens of amperes of current or several kilovolts of voltage), which may cause a failure of the integrated circuit chip.

In general, an ESD circuit of an integrated circuit has signal paths between an input/output port IO and a power supply and ground, and normally, the input/output port IO and the power supply and ground are both in an off state, so that no leakage current exists. In practical application, however, in order to achieve a low power consumption mode, a system often turns off some modules, and power supplies of the turned-off modules are usually low in resistance or pulled to the ground, so that a loop is formed between an input/output port IO of the turned-off module and the power supply, a large current or leakage occurs, and the current to a certain extent will consume devices in the whole loop, resulting in a functional failure of the module.

The invention prevents electrostatic discharge ESD from protecting a circuit which causes leakage current under the condition of power supply turn-off, solves the problem of large current or leakage current under the turn-off mode, and can also ensure the protective capability of electrostatic discharge ESD.

Disclosure of Invention

The purpose of the invention is as follows:

the invention provides a circuit for preventing electrostatic discharge ESD protection from causing leakage current under the condition of power supply turn-off, and aims to cut off a loop from input/output IO to a power supply under the condition of chip turn-off and ensure the electrostatic discharge ESD protection capability and circuit performance.

The technical scheme is as follows:

a circuit for preventing electrostatic discharge ESD protection from causing leakage current under power supply turn-off comprises two switch circuits and a capacitor, wherein the two switch circuits are connected between input/output IO and a power supply, the first switch circuit is formed by connecting a resistor and a switch tube PMOS in series, the grid electrode of the switch tube PMOS is connected with a power supply end through a resistor, one end of the switch circuit is connected with the input/output IO, and the other end of the switch circuit is connected with a substrate of the electrostatic discharge tube PMOS, and the switch circuit is used for conducting a PMOS tube serving as a switch under a power supply turn-off (pulled to ground potential) mode to enable two ends of a parasitic PN junction of the electrostatic discharge tube PMOS to be equipotential and reliably cut off, so that a path from the input/output IO to the substrate of the electrostatic discharge tube PMOS is disconnected, and almost no leakage current is generated.

And the second switching tube circuit is composed of an NMOS tube, the grid electrode of the NMOS tube which plays a role of a switch is connected with a power supply end through a resistor, one end of the switching circuit is connected with the substrate of the ESD tube PMOS, and the other end of the switching circuit is connected with the power supply end. The ESD protection device is used for completely disconnecting the path of the PMOS substrate of the electrostatic discharge ESD tube from the power supply by switching the NMOS tube to an off state in a power supply off (pulled to the ground potential) mode.

One end of the capacitor is connected with the PMOS substrate of the electrostatic discharge ESD tube, and the other end of the capacitor is connected with the power supply.

Under the power supply turn-off mode, when a positive static discharge ESD transient pulse occurs, because the equivalent RC of the first switch circuit and the capacitor is larger, the static discharge path is a static discharge ESD tube PMOS and a second switch tube, flows to a power supply end and is discharged through the static discharge ESD circuit of the power supply. The electrostatic discharge ESD protection capability under the power off mode is ensured.

Further, the electrostatic discharge path at this time is: and the input and output IO is transmitted to the substrate of the static electricity discharge tube PMOS, then to the second switch tube and finally to the static electricity discharge ESD circuit of the power supply, so that the static electricity discharge is completed.

When the power supply recovers to a normal voltage state, the switch PMOS tube is cut off, the switch NMOS tube is conducted, the static electricity release tube PMOS substrate is connected with the power supply, and the static electricity release ESD normally works, so that the maximum input and output swing of the input and output IO is ensured, the resistance value of the switch PMOS tube in series is large, the parasitic effect is small, and the performance of the circuit is not influenced.

The invention achieves the following beneficial effects:

the circuit for preventing the electrostatic discharge ESD protection from causing the leakage current under the condition of power supply turn-off, provided by the invention, avoids the phenomenon of large current or leakage current from input/output IO to the power supply under the condition of power supply turn-off, and does not influence the electrostatic protection level; when the power supply voltage is in a normal state, the output swing of the input/output IO and the electrostatic discharge protection capability are not influenced, the performance of the circuit is ensured, and the method has significant significance for low power consumption of a chip!

Drawings

FIG. 1-a shows a conventional ESD protection circuit;

FIG. 1-b illustrates the protection mechanism under a positive ESD transient pulse;

FIG. 1-c is a diagram illustrating a protection mechanism under a negative ESD transient pulse

FIG. 1-d shows the leakage current generation mechanism under the power-off condition

FIG. 2-a is a circuit for preventing ESD protection from ESD leakage current under power-off condition, according to the present invention;

FIG. 2-b illustrates the leakage current formation mechanism and prevention in the case of power-off;

2-c is the protection mechanism of the invented circuit under the condition of power-off under the transient pulse of forward electrostatic discharge ESD;

Detailed Description

The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.

As shown in fig. 1-a, the ESD protection circuit for electrostatic discharge of integrated circuit, which is a conventional circuit in the prior art, is composed of ggNMOS _1, ggPMOS _1 and ESD circuit for electrostatic discharge of power supply, where node 1-1 represents input/output IO, and is connected to drain node PD _1 of ggPMOS _1 and drain node ND _1 of ggNMOS _1, node NG _1 represents the gate of ggNMOS _1, node NS _1 represents the source of ggNMOS _1, node NB _1 represents the substrate of ggNMOS _1, node PG _1 represents the gate of ggPMOS _1, node PS _1 represents the source of ggPMOS _1, and node PB _1 represents the substrate of ggPMOS _ 1. Node NG _1, node NS _1, and node NB _1 are connected to ground GND, and node PG _1, node PS _1, and node PB _1 are connected to power supply VDD.

When a forward electrostatic discharge (ESD) transient pulse (with respect to ground) occurs at the node 1-1, as shown in fig. 1-b, the diode ND _1 is a reverse biased diode formed by the drain node ND _1 of the ggNMOS _1 and the substrate NB _1, the transistor NQ _1 is a parasitic lateral NPN transistor, and the resistor RN _1 is a substrate parasitic resistor of the ggNMOS _ 1. At this time, the reverse bias voltage of the reverse biased diode ND _1 starts to increase to a certain level, an avalanche breakdown multiplication effect occurs, a large number of electron-hole pairs are generated, and holes flow to the ground through the substrate resistance RN _1, so that a voltage difference VRN _1 is established in the substrate parasitic resistance RN _ 1. As the source node NS _1 is grounded, the voltage VRN _1 is also added to the BE junction of the parasitic NPN tube NQ _1 of the ggNMOS _1, once the voltage VRN _1 is greater than the conduction voltage of the BE junction, the parasitic horizontal NPN enters a positive active working area, the voltage of the collector node ND _1 begins to drop, a low-impedance discharge path is formed, ESD transient current is discharged, and meanwhile, the input and output IO node 1-1 is clamped to a low-back holding voltage, so that the dielectric breakdown of an oxide layer of a rear-stage internal circuit is avoided. In this case, as shown in fig. 1-c, diode PD _1 is a forward biased diode transistor formed by drain node PD _1 and substrate node PB _1 of ggPMOS _1, and is turned on in the forward direction to form a parallel discharge path for discharging VDD.

When a negative ESD transient (with respect to ground) occurs at node 1-1, the roles of transistors ggNMOS _1 and ggPMOS _1 are interchanged.

Therefore, the ESD protection circuit shown in fig. 1-a can provide ESD protection capability in both forward and reverse directions, one direction providing ESD protection by means of the parasitic bipolar transistor, and the other direction providing ESD protection by means of the parasitic diode of the MOS transistor.

For the ESD protection circuit with electrostatic discharge described above, if the power supply is turned off (pulled to ground or low resistance), a positive voltage appears at the input/output IO node 1-1, as shown in fig. 1-d, the forward biased diode transistor PD _1 formed by the drain node PD _1 of the ggPMOS _1 and the substrate node PB _1 is turned on in the forward direction, and a large current IEAKP _1 flows to the power supply VDD through the substrate, so that the device ggPMOS _1 is damaged, and the whole circuit loses its function.

The invention provides a corresponding leakage current generation preventing circuit, as shown in fig. 2-a, which is composed of two switch circuits and a capacitor, wherein the first switch circuit is composed of a resistor R3_2 and a PMOS switch tube PMOS2_2 which are connected in series, a gate node PG2_2 of the switch tube PMOS2_2 is connected with a power supply VDD through the resistor R2_2, a substrate node PB2_2 of the switch tube PMOS2_2 is connected with one end of the resistor R3_2, one end of the switch circuit is connected with an input/output IO node 2_1, and the other end of the switch circuit is connected with a substrate node PB1_2 of an electrostatic discharge tube ggPMOS1_ 2.

The second switching tube circuit is composed of an NMOS switching tube NMOS2_2, a gate node NG2_2 of the switching tube NMOS2_2 is connected to the power supply terminal VDD through a resistor R1_2, one end of the switching circuit is connected to a substrate node PB1_2 of the electrostatic discharge tube ggPMOS1_2, and the other end is connected to the power supply VDD.

One end of the capacitor C1_2 is connected to the substrate node PB1_2 of the electrostatic discharge tube ggPMOS1_2, and the other end is connected to the power supply VDD.

The protection mechanism is as follows:

in a power supply off (pulled to the ground potential) mode, as shown in fig. 2-b, a gate node PG2_2 serving as a switching tube PMOS2_2 is connected with a power supply VDD through a resistor R2_2 and is also at the ground potential, when the voltage of an input/output IO node 2_1 starts to rise to a certain voltage, the switching tube PMOS2_2 is turned on, so that the two ends of a parasitic PN diode PD _2 of an electrostatic discharge tube ggPMOS1_2 are equipotential and reliably cut off, and a path from the input/output IO to a substrate node PB1_2 of the electrostatic discharge tube ggPMOS1_2 is cut off, and even if the voltage of the input/output IO node 2_1 continues to increase again, IEAKP _2 current is almost always 0; when the voltage of the input/output IO node 2_1 is small, the switching tube PMOS2_2 is not turned on, even if the voltage of the node PD1_2 of the electrostatic discharge tube ggPMOS1_2 exceeds the junction voltage of the parasitic PN diode PD _2, the gate PG2_2 of the switching tube NMOS2_2 is at the ground potential, the switching tube NMOS2_2 is at the off state, and the IEAKP _2 current is almost 0 because the substrate node PB1_2 of the electrostatic discharge tube ggPMOS1_2 is floating. For the possible voltages of two input/output IO, the circuit prevents the generation of leakage current from the input/output IO to a power supply end under a large voltage range.

In the power off (pulled to the ground potential) mode, if there is a positive ESD transient pulse at the IO node 2_1, as shown in fig. 2-C, in order to utilize a parallel discharge path for discharging the power supply terminal VDD through the ggPMOS1_2 as shown in fig. 1-b, R3_ 2_ C1_2>10 _ R4_ 2_ C2_2, R4_2 is taken as the resistance of the power supply ESD circuit, and C2_2 is the equivalent MOS capacitance of the power supply ESD circuit. Before the voltage of the first switching circuit mainly comprising the switching tube PMOS2_2 is established, the electrostatic discharge ESD path flows from the input/output IO node 2_1 to the substrate node PB1_2 of the electrostatic discharge tube ggPMOS1_2, and then an avalanche multiplication effect occurs through a PN diode ND _2 parasitic to the switching tube NMOS2_2, and an effective electrostatic discharge ESD path is formed as the electrostatic discharge principle shown in FIG. 1-b.

When the power supply recovers to a normal voltage state, the switch PMOS2_2 tube is cut off, the switch NMOS2_2 tube is conducted, the substrate node PB1_2 of the electrostatic discharge tube ggPMOS1_2 is connected with the power supply, and electrostatic discharge ESD normally works, so that the maximum input and output swing of input and output IO is ensured, the value of the resistor R3_2 is large, the parasitic effect is small, and the performance of the circuit is not influenced.

The circuit for preventing the electrostatic discharge ESD protection from causing the leakage current under the condition of power supply turn-off not only avoids the phenomenon of large current or leakage current from input/output IO to the power supply, but also does not influence the electrostatic protection grade; and when the power supply voltage is in a normal state, the output swing amplitude and the electrostatic discharge protection capability of the input/output IO are not influenced, the performance of the circuit is ensured, and the method has a remarkable significance for low power consumption of the chip.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims

1. The circuit is characterized by comprising two switching circuits and a capacitor, wherein the two switching circuits are connected between an input/output (IO) and a power supply; the second switch circuit is responsible for disconnecting the substrate of the electrostatic discharge ESD tube from the power supply end.

2. The circuit of claim 1, wherein the first switching transistor circuit comprises a first resistor and a switch PMOS connected in series.

3. The circuit for preventing ESD protection from leakage current under power-off as claimed in claim 2, wherein the gate of the switch PMOS is connected to the power source terminal through the second resistor.

4. The circuit of claim 1, wherein said second switching circuit comprises an NMOS transistor, the gate of said NMOS transistor being connected to the power supply terminal through a resistor.

5. The circuit of claim 1, wherein the capacitor is a passive on-chip capacitor, one end of the capacitor is connected to the ESD transistor substrate, and the other end of the capacitor is connected to a power supply terminal.