CN219740340U

CN219740340U - Reset circuit, chip and electronic equipment

Info

Publication number: CN219740340U
Application number: CN202223613553.3U
Authority: CN
Inventors: 王蒙; 白青刚
Original assignee: Shenzhen ICM Microelectronics Co Ltd
Current assignee: Shenzhen ICM Microelectronics Co Ltd
Priority date: 2022-12-30
Filing date: 2022-12-30
Publication date: 2023-09-22
Anticipated expiration: 2032-12-30

Abstract

The utility model discloses a reset circuit, a chip and electronic equipment. The reset circuit comprises a transistor, a zener diode, a capacitor and a comparator. The transistor is connected with the power end, the voltage stabilizing diode is arranged between the transistor and the capacitor, and the input end of the comparator is connected with the output end of the voltage stabilizing diode and the upper polar plate of the capacitor. The second end of the capacitor is grounded, the transistor is used for providing current for charging the capacitor, and the comparator is used for detecting the voltage of the capacitor and outputting a reset signal according to the voltage of the capacitor. The voltage stabilizing diode is used for keeping the voltage of the capacitor larger than a preset threshold value after the reset circuit is powered up, so that the comparator is prevented from outputting an abnormal reset signal. According to the reset circuit, the voltage stabilizing diode is connected between the transistor and the capacitor in series, the effect of preventing the capacitor from discharging charges to the power end is achieved, the upper polar plate of the capacitor shakes along with the shaking of the ground wire, the overturning voltage of the comparator cannot be reached, and abnormal reset after the reset circuit is powered on is avoided.

Description

Reset circuit, chip and electronic equipment

Technical Field

The present utility model relates to the field of chip application technologies, and in particular, to a reset circuit, a chip, and an electronic device.

Background

In many chip circuits, there is a power-on reset circuit. The power-on reset signal (POR) output by the power-on reset circuit controls the initial state of the whole chip. When the chip is powered on, the signal is ideally a power-on reset signal with stable output of '1'.

However, in real applications, the power or ground jitter may occur, which affects the capacitor voltage, and thus causes the power-on reset signal of the error "0" of the power-on reset signal POR to occur, and thus causes abnormal reset of the chip.

Disclosure of Invention

In view of this, the present utility model aims to solve, at least to some extent, one of the problems in the related art. To this end, an object of the present utility model is to provide a reset circuit, a chip, and an electronic device.

The embodiment of the utility model provides a reset circuit. The reset circuit comprises a transistor, a zener diode, a capacitor and a comparator; the transistor is connected with a power supply end; the zener diode is arranged between the transistor and the capacitor; the input end of the comparator is connected with the output end of the voltage stabilizing diode and the upper polar plate of the capacitor; the second end of the capacitor is grounded; the transistor is used for providing current for charging the capacitor; the comparator is used for detecting the voltage of the capacitor and outputting a reset signal according to the voltage of the capacitor; and the voltage stabilizing diode is used for keeping the voltage of the capacitor larger than a preset threshold value after the reset circuit is powered up, so as to prevent the comparator from outputting an abnormal reset signal.

Therefore, the reset circuit of the utility model realizes the effect of preventing the capacitor from discharging charges to the power supply end by connecting the voltage stabilizing diode in series between the transistor and the capacitor, and the upper polar plate of the capacitor shakes along with the shake of the ground wire, so that the overturning voltage of the comparator cannot be reached, that is, after the reset circuit is powered on, the comparator cannot output an abnormal reset signal because of the shake of the ground wire, and the abnormal reset of the chip after the reset circuit is powered on is avoided.

In some embodiments, the transistor is an N-channel transistor, a drain of the transistor is connected to the power supply terminal, and a source of the transistor is connected to the first pole of the zener diode.

Therefore, when the reset circuit is powered on for resetting, the transistor can avoid abnormal resetting caused by abnormal resetting signals output by the comparator due to shaking of the power supply end in the power-on process of the reset circuit.

In some embodiments, the preset threshold is a roll-over voltage of the comparator.

In this way, the reset circuit can determine whether the comparator outputs an abnormal reset signal according to the flip voltage of the comparator.

In some embodiments, a first terminal of the zener diode is connected to the source of the transistor, and a second terminal of the zener diode is connected to the upper plate of the capacitor and the input terminal of the comparator.

Therefore, the voltage stabilizing diode is used for preventing the charges of the upper polar plate of the capacitor from leaking to the power supply end when the ground wire shakes, and the comparator is prevented from outputting abnormal reset signals.

In some embodiments, the zener diode is configured to prevent the charge on the upper plate of the capacitor from leaking to the power supply terminal when the ground line shakes, so as to avoid the comparator from outputting an abnormal reset signal.

Therefore, the voltage stabilizing diode prevents the charges of the upper polar plate of the capacitor from leaking to the power supply end for the reset circuit, and avoids the comparator from outputting abnormal reset signals, thereby achieving the function of protecting the reset circuit.

In some embodiments, the zener diode is formed by the PN junction of a P-type transistor.

Therefore, the voltage stabilizing diode forms a characteristic element with unidirectional conduction through the PN node of the P-type transistor, so that the charge of the upper polar plate of the capacitor is prevented from leaking to the power end, and after the reset circuit is powered on, the comparator is prevented from outputting abnormal reset signals due to the shaking of the ground wire.

In some embodiments, the zener diode is formed by the PN junction of an N-type transistor.

Therefore, the voltage stabilizing diode forms a characteristic element with unidirectional conduction through the PN node of the N-type transistor, so that the charge of the upper polar plate of the capacitor is prevented from leaking to the power end, and after the reset circuit is powered on, the comparator is prevented from outputting abnormal reset signals due to the shaking of the ground wire.

In some embodiments, the comparator outputs a high level when detecting that the voltage of the capacitor is greater than a preset threshold after the reset circuit is powered on and reset.

Therefore, after the power-on reset of the reset circuit is completed, the comparator detects that the voltage of the capacitor is larger than a preset threshold value and outputs a high level so as to avoid abnormal reset of a chip containing the reset circuit.

The utility model also provides a chip. The chip comprises the reset circuit of any one of the embodiments, and the reset circuit is used for avoiding the chip from carrying out error reset after the power-on reset is completed.

Therefore, the chip comprises the reset circuit in the embodiment, the voltage-stabilizing diode is connected between the transistor and the capacitor in series, the effect of preventing the capacitor from discharging charges to the power supply end is realized, the upper polar plate of the capacitor shakes along with the shaking of the ground wire, the overturning voltage of the comparator cannot be reached, namely, after the reset circuit is powered on, the comparator cannot output an abnormal reset signal due to the shaking of the ground wire, and the abnormal reset of the chip after the reset circuit is powered on is avoided.

The utility model further provides electronic equipment. The electronic device comprises the chip described in the above embodiment mode.

Therefore, the electronic equipment comprises the chip in the embodiment, the chip comprises the reset circuit in the embodiment, the effect of preventing the capacitor from discharging charges to the power supply end is realized by connecting the voltage stabilizing diode in series between the transistor and the capacitor, the upper polar plate of the capacitor shakes along with the shaking of the ground wire, the overturning voltage of the comparator cannot be reached, namely, after the reset circuit is powered on, the comparator cannot output an abnormal reset signal due to the shaking of the ground wire, and the abnormal reset of the chip after the reset circuit is powered on is avoided.

Additional aspects and advantages of the utility model will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model.

Drawings

The foregoing and/or additional aspects and advantages of the utility model will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a power-on reset circuit in the related art;

fig. 2 is a waveform diagram of an abnormality of a power-on reset signal caused by a ground line jitter of a power-on reset circuit in the related art;

FIG. 3 is a schematic diagram of a reset circuit in some embodiments of the utility model;

fig. 4 is a waveform diagram of a normal power-on reset signal generated by a ground line jitter of a reset circuit in some embodiments of the present utility model.

Detailed Description

Embodiments of the present utility model are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present utility model and are not to be construed as limiting the present utility model.

In the description of the present utility model, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present utility model, the meaning of "a plurality" is two or more, unless specifically defined otherwise.

In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; may be mechanically connected, may be electrically connected, or may be in communication with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.

The following disclosure provides many different embodiments, or examples, for implementing different features of the utility model. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the utility model. Furthermore, the present utility model may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed.

In many circuits, there is a power-on reset circuit. The power-on reset circuit has the function that the power supply voltage slowly rises during the power-on process. If jitter occurs during the rising, the circuit is in an indeterminate state, causing the power-up process of the chip to operate erroneously, which can seriously damage the chip and its peripheral circuitry.

The specific method is that during the power-on process, the power-on reset signal defaults to logic low, namely '0'; meanwhile, the capacitor is charged through a current, and when the voltage of the capacitor reaches a certain voltage, the power-on reset signal becomes logic high, namely '1'. When the power-on reset signal is 0, the places where the chip needs to be reset are reset, namely the initial state is achieved. When the power-on reset signal is changed into 1, the chip works normally. As shown in fig. 1.

Where VCC is the power supply and GND is ground. C1 is the capacitance. Q1 is a PMOS tube for providing charge current to capacitor C1. SMIT is a voltage used to detect capacitor C1, and when above a certain value, the SMIT output toggles, i.e., changes from "0" to "1". Of course, the SMIT may be a conventional buffer, schmitt trigger, or the like.

In practical application, as shown in fig. 2, when the ground GND shakes upward, the voltage across the capacitor C1 will not be suddenly changed, and therefore, the voltage at VCAP will rise along with the ground GND shaking upward, as shown in t 1-t 2. Since the PMOS transistor connected to the capacitor C1 has a parasitic diode (parasitic diode) of VCAP to the power terminal VCC inside, when the voltage at VCAP rises to the sum of the voltage of the power terminal VCC and the voltage of the parasitic diode, it is stabilized at this voltage. During this process, the upper plate charge of capacitor C1 is drained onto supply terminal VCC. At time t2, ground GND falls, and the voltage across capacitor C1 does not change abruptly, so the voltage at VCAP falls with ground GND, as indicated by t2 to t 3. And then, the ground wire is stable, and the upper polar plate of the capacitor C1 slowly charges the capacitor C1 through the PMOS tube. In this process, if the voltage at VCAP drops below the threshold voltage of SMIT, the power-on reset signal POR is abnormal, SMIT outputs an abnormally low level, and resets the chip error.

In view of this, referring to fig. 3, the present utility model provides a reset circuit 10. The reset circuit 10 includes a transistor Q1, a zener diode D1, a capacitor C1, and a comparator SMIT. The transistor Q1 is connected to the power supply terminal VCC, and the zener diode D1 is disposed between the transistor Q1 and the capacitor C1. The input e of the comparator SMIT is connected to the output b of the zener diode D1 and to the upper plate C of the capacitor C1. The second end d of the capacitor C1 is grounded GND.

Transistor Q1 is used to provide current for charging capacitor C1. The transistor Q1 of the utility model avoids abnormal reset in the power-on process caused by abnormal reset signals output by the jitter of the power supply end VCC during the power-on reset.

The comparator SMIT is configured to detect a voltage of the capacitor C1 and output a reset signal according to the voltage of the capacitor C1. The comparator SMIT may be a voltage comparator. That is, the comparator SMIT compares the voltage magnitude of the capacitor C1 with the voltage magnitude preset in the comparator SMIT to output the reset signal.

The zener diode D1 is configured to keep the voltage of the capacitor C1 greater than a preset threshold after the reset circuit 10 is powered up, so as to avoid the comparator SMIT from outputting an abnormal reset signal. The zener diode D1 in the embodiment of the present utility model is a unidirectional conductive electronic element, and allows current to flow only in a single direction. That is, the zener diode D1 corresponds to a unidirectional switch, and can conduct forward current and cannot conduct reverse current.

As can be appreciated, during the power-on process of the reset circuit 10, the zener diode D1 prevents the capacitor C1 from discharging the charge to the power supply terminal VCC by utilizing the unidirectional conductive characteristic, so as to realize the function of stabilizing the voltage of the capacitor C1 and avoid the comparator SMIT from outputting an abnormal reset signal.

Therefore, the reset circuit 10 of the present utility model realizes the effect of preventing the capacitor C1 from discharging the charge to the power supply terminal VCC by connecting a zener diode D1 in series between the transistor Q1 and the capacitor C1, and the upper plate C of the capacitor C1 shakes along with the shake of the ground line GND, so as not to reach the flip voltage of the comparator SMIT, that is, after the reset circuit 10 is powered up, the comparator SMIT will not output an abnormal reset signal due to the shake of the ground line GND, thereby avoiding the abnormal reset of the chip after the reset circuit 10 is powered up.

In some embodiments, the transistor Q1 is an N-channel transistor, the drain D of the transistor Q1 is connected to the power supply terminal VCC, and the source S of the transistor Q1 is connected to the first pole a of the zener diode D1.

Specifically, the transistor Q1 is a solid-state semiconductor transistor device. The transistor Q1 of the present utility model may be used to provide current for charging the capacitor C1. That is, the transistor Q1 avoids outputting an abnormal reset signal due to the jitter of the power supply terminal VCC during the power-on reset, resulting in abnormal reset during the power-on process.

In this way, the transistor Q1 can avoid outputting an abnormal reset signal due to the jitter of the power supply terminal VCC when the reset circuit 10 performs the power-on reset, which results in abnormal reset during the power-on process of the reset circuit 10.

In some embodiments, the preset threshold is a flip voltage of the comparator SMIT.

Specifically, the preset threshold may be, for example, 300mV, or may be another value, which is not limited herein. That is, the flip voltage of the comparator SMIT may be 300mV, for example. When the power-on reset of the reset circuit 10 is completed, if the voltage at VCAP is lower than the flip voltage of the comparator SMIT, the output terminal f of the comparator SMIT will output a low level and output an abnormal reset signal, so that the chip including the reset circuit 10 is damaged due to abnormal reset. Similarly, if the voltage at VCAP is higher than the flip voltage of the comparator SMIT, the output terminal f of the comparator SMIT will output a high level and a normal reset signal, and the chip will work normally. That is, the reset circuit 10 may determine whether the comparator SMIT outputs an abnormal reset signal according to the flip voltage of the comparator SMIT.

In this manner, the reset circuit 10 can determine whether the comparator SMIT outputs an abnormal reset signal according to the flip voltage of the comparator SMIT.

In some embodiments, a first terminal a of the zener diode D1 is connected to the source S of the transistor Q1, and a second terminal b of the zener diode D1 is connected to the upper plate C of the capacitor C1 and the input e of the comparator SMIT.

Specifically, the zener diode D1 is a unidirectional conductive electronic component. That is, the current in the reset circuit 10 may flow from the first terminal a of the zener diode D1 to the second terminal b of the zener diode D1, but cannot flow reversely. That is, the zener diode D1 is configured to prevent the charge on the upper plate C of the capacitor C1 from leaking to the power supply terminal VCC when the ground GND shakes, so as to avoid the comparator SMIT from outputting an abnormal reset signal.

In this way, the zener diode D1 is configured to prevent the charge on the upper plate C of the capacitor C1 from leaking to the power supply terminal VCC when the ground GND shakes, so as to avoid the comparator SMIT from outputting an abnormal reset signal.

In some embodiments, the zener diode D1 is used to prevent the charge on the upper plate C of the capacitor C1 from leaking to the power supply terminal VCC when the ground GND is jittered, so as to avoid the comparator SMIT from outputting an abnormal reset signal.

Specifically, referring to fig. 4, when the ground GND is dithered, the upper plate C of the capacitor C1 will not bleed the charge to the power supply terminal VCC because the charge cannot reverse through the zener diode D1.

It can be understood that, when the ground GND shakes, the upper plate C of the capacitor C1 of the present utility model shakes along with the ground GND, as shown by t 1-t 2 in fig. 4, the voltage at VCAP will rise along with the rise of the ground GND, and at time t 2-t 3, although the voltage at VCAP is dropping due to the ground GND shake by the reset circuit 10, the upper plate C of the capacitor C1 can be prevented from leaking charges to the power supply terminal VCC due to the effect of the zener diode D1, so that the voltage of the upper plate C of the capacitor C1 will not drop below the threshold voltage VTH of the comparator SMIT, and the comparator SMIT is prevented from outputting an abnormal reset signal.

In this way, the zener diode D1 prevents the charge on the upper plate C of the capacitor C1 from leaking to the power supply terminal VCC for the reset circuit 10, so as to prevent the comparator SMIT from outputting an abnormal reset signal, thereby protecting the reset circuit 10.

In some embodiments, zener diode D1 is formed by the PN junction of a P-type transistor.

In particular, the P-type transistors may include depletion-type P-channel transistors and enhancement-type P-channel transistors. The depletion type P channel transistor is conducted at a low level, and no external voltage is needed. The enhancement P-channel transistor is turned on at a high level, requiring an applied voltage. The working principle of the P-type transistor is mainly embodied in the polarity of the conductive carriers and the supply voltage. Specifically, the conductive carriers of the P-type transistor are mostly holes, and the gate voltage of the P-type transistor is negative.

In this way, the zener diode D1 forms a characteristic element with unidirectional conduction through the PN junction of the P-type transistor, so as to avoid leakage of the charge of the upper electrode plate C of the capacitor C1 to the power supply terminal VCC, and avoid the comparator SMIT outputting an abnormal reset signal due to the jitter of the ground line GND after the reset circuit 10 is powered up.

In some embodiments, zener diode D1 is formed by the PN junction of an N-type transistor.

In particular, the N-type transistors may include depletion-mode N-channel transistors and enhancement-mode N-channel transistors. The depletion type N channel transistor is conducted at a low level, and no external voltage is needed. The enhancement N-channel transistor is turned on at a high level and requires an applied voltage. The working principle of the N-type transistor is exactly the same as that of the P-type transistor, and only the polarity of the conductive carriers and the polarity of the power supply voltage are different. Specifically, the N-type transistor has electron carriers, and the gate voltage of the N-type transistor has positive polarity.

In this way, the zener diode D1 forms a characteristic element with unidirectional conduction through the PN junction of the N-type transistor, so as to avoid leakage of the charge of the upper electrode plate C of the capacitor C1 to the power supply terminal VCC, and avoid the comparator SMIT outputting an abnormal reset signal due to the jitter of the ground line GND after the reset circuit 10 is powered up.

In some embodiments, the comparator SMIT outputs a high level when the voltage of the detection capacitor C1 is greater than the preset threshold after the reset circuit 10 is powered up and reset.

Specifically, when the power-on reset of the reset circuit 10 is completed, it is assumed that the preset threshold voltage of the comparator SMIT may be 300mV, for example. If the voltage of the comparator SMIT detecting capacitor C1 is greater than the preset threshold voltage 300mV, it indicates that the voltage at VCAP does not drop below the preset threshold voltage of the comparator SMIT, and the comparator SMIT avoids outputting an abnormal power-on reset signal. That is, the reset circuit 10 operates normally.

In this way, after the reset circuit 10 is powered on and reset, the comparator SMIT detects that the voltage of the capacitor C1 is greater than the preset threshold and outputs a high level, so as to avoid abnormal reset of the chip including the reset circuit 10.

The utility model also provides a chip. The chip comprises the reset circuit 10 of any one of the above embodiments, and the reset circuit 10 is configured to avoid the chip from performing an erroneous reset after the power-on reset is completed.

In this way, the chip of the present utility model includes the reset circuit 10 in the above embodiment, by connecting a zener diode D1 in series between the transistor Q1 and the capacitor C1, the effect of preventing the capacitor C1 from discharging the charge to the power supply terminal VCC is achieved, and the upper plate C of the capacitor C1 shakes along with the shake of the ground line GND, so that the flip voltage of the comparator SMIT is not reached, that is, after the reset circuit 10 is powered up, the comparator SMIT will not output an abnormal reset signal due to the shake of the ground line GND, and abnormal reset of the chip after the reset circuit 10 is powered up is avoided.

The utility model further provides electronic equipment. The electronic device includes the chip in the above embodiment.

In this way, the electronic device of the present utility model includes the chip in the above embodiment, and the chip includes the reset circuit 10 in the above embodiment, and the effect of preventing the capacitor C1 from discharging the charge to the power supply terminal VCC is achieved by connecting in series a zener diode D1 between the transistor Q1 and the capacitor C1, and the upper plate C of the capacitor C1 shakes along with the shake of the ground line GND, so that the flip voltage of the comparator SMIT is not reached, that is, after the reset circuit 10 is powered up, the comparator SMIT will not output an abnormal reset signal due to the shake of the ground line GND, so that the abnormal reset of the chip after the power up of the reset circuit 10 is avoided.

The foregoing examples illustrate only a few embodiments of the utility model, which are described in detail and are not to be construed as limiting the scope of the utility model. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the utility model, which are all within the scope of the utility model. Accordingly, the scope of protection of the present utility model is to be determined by the appended claims.

Claims

1. The reset circuit is characterized by comprising a transistor, a zener diode, a capacitor and a comparator; the transistor is connected with a power supply end; the zener diode is arranged between the transistor and the capacitor; the input end of the comparator is connected with the output end of the voltage stabilizing diode and the upper polar plate of the capacitor; the second end of the capacitor is grounded;

the transistor is used for providing current for charging the capacitor;

the comparator is used for detecting the voltage of the capacitor and outputting a reset signal according to the voltage of the capacitor;

and the voltage stabilizing diode is used for keeping the voltage of the capacitor larger than a preset threshold value after the reset circuit is powered up, so as to prevent the comparator from outputting an abnormal reset signal.

2. The reset circuit of claim 1 wherein the transistor is an N-channel transistor, a drain of the transistor is connected to the power supply terminal, and a source of the transistor is connected to the first pole of the zener diode.

3. The reset circuit of claim 1 wherein the predetermined threshold is a flip voltage of the comparator.

4. The reset circuit of claim 1 wherein a first terminal of the zener diode is connected to the source of the transistor and a second terminal of the zener diode is connected to the upper plate of the capacitor and the input terminal of the comparator.

5. The reset circuit of claim 1 wherein said zener diode is configured to prevent leakage of charge from an upper plate of said capacitor to said power supply terminal during ground line jitter to avoid said comparator outputting an abnormal reset signal.

6. The reset circuit of claim 1 wherein the zener diode is comprised of a PN junction of a P-type transistor.

7. The reset circuit of claim 1 wherein the zener diode is comprised of a PN junction of an N-type transistor.

8. The reset circuit of claim 1 wherein the comparator outputs a high level when detecting that the voltage of the capacitor is greater than a preset threshold after the reset circuit is powered up.

9. A chip comprising a reset circuit according to any one of claims 1 to 8 for avoiding erroneous reset of the chip after a power-on reset is completed.

10. An electronic device comprising the chip of claim 9.