CN102222891B - Power clamping ESD (electro-static discharge) protection circuit utilizing current mirror - Google Patents
Power clamping ESD (electro-static discharge) protection circuit utilizing current mirror Download PDFInfo
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- CN102222891B CN102222891B CN 201110166467 CN201110166467A CN102222891B CN 102222891 B CN102222891 B CN 102222891B CN 201110166467 CN201110166467 CN 201110166467 CN 201110166467 A CN201110166467 A CN 201110166467A CN 102222891 B CN102222891 B CN 102222891B
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Abstract
The invention discloses a power clamping ESD (electro-static discharge) protection circuit utilizing a current mirror, and relates to the technical field of ESD protection of an integrated circuit chip. The power clamping ESD protection circuit comprises a capacitor-resistor module (1), a clamping transistor turn-on module (2) and a clamping transistor (4) which are connected in series, and also comprises a clamping transistor turn-off module (3) which is connected with the capacitor-resistor module (1) and the clamping transistor (4) respectively. A current mirror structure is introduced in the power clamping ESD protection circuit, thus a capacitor in the capacitor-resistor module is increased by multiple times equivalently, the turn-on time of the clamping transistor is prolonged, and the reliability of ESD protection is improved; in addition, the circuit structure adopts a novel inverter instead of the traditional inverter so that the turn-on time of the clamping transistor is prolonged so as to meet the requirement when the integrated circuit dissipates electrostatic charges and ensure that the discharging capacity of the clamping transistor is stabilized at an extremely highlevel in the ESD protection period.
Description
Technical field
The present invention relates to integrated circuit (IC) chip static discharge (Electronic Static Discharge, ESD) resist technology field, particularly a kind of power supply clamper esd protection circuit that utilizes current mirror.
Background technology
Along with constantly dwindling of integrated circuit technology characteristic size, the antistatic relieving capacity of chip has become the key factor that guarantees the internal circuit reliably working.The electrostatic leakage phenomenon refers to: when two with not iso-electric object near or when contact, the transient process that electrostatic charge shifts occurs between the two.Under advanced person's integrated circuit technology level, the gate oxide of device is very thin, and its equivalent gate oxide electric capacity is very little, when electrostatic charge is accumulated on the gate oxide, can form very large equivalent grid voltage, causes the inefficacy of device or circuit.For integrated circuit (IC) chip, electrostatic impact has different patterns, and correspondence also has different protective circuits.To ground pin or I/O pin under the conflicting model to the I/O pin, the electrostatic charge inner function circuit module of can flowing through causes the damage of internal circuit in power pin.Power supply clamper esd protection circuit mainly is for above-mentioned two kinds of conflicting models, impacts temporarily, provides the effective electrostatic charge path of releasing to chip, guarantees the damage that the chip internal functional circuit is not hit.
The design of existing power supply clamper esd protection circuit need to be satisfied following condition: impact temporarily at ESD, provide a useful signal by electric capacity-resistance or the resistance-capacitance module of protective circuit, open clamp transistor with the static electricity discharge electric charge.Charging normal voltage temporarily, clamp transistor requires not to be opened.Dwindling of characteristic size faces the challenge power supply clamper esd protection circuit: at first; electric capacity-resistance or resistance-capacitance time constant have does little requirement, but electric capacity-resistance or resistance-capacitance time constant are done the little clamp transistor enough opening times under ESD impacts that need to guarantee afterwards.Secondly, charging normal voltage has very short situation of rise time, and power supply clamper esd protection circuit is wanted effectively to prevent to be charged normal the voltage false triggering by zooming.Again, even protective circuit, needs mechanism that breaks away from false triggering of design by false triggering, so that circuit is avoided the impact of breech lock problem.
Figure 1 shows that a kind of power supply clamper esd protection circuit of prior art, wherein Mbig is clamp transistor.Its operation principle is as follows: when an esd pulse is applied to the VDD pin, the voltage of R1-C11 intersection point (being the tie point of R1 and C11) draws on can not be immediately, remain low level in the incipient stage of impacting, this low level is transmitted to the grid of Mp13 through the two-stage inverter that is made of Mp11, Mn11 and Mp12, Mn12, Mp13 is conducting thus, and the grid voltage of Mbig1 is pulled to the voltage levvl of VDD pin, and then Mbig1 starts, and the ESD that begins to release impacts the electrostatic charge of accumulation.By the time the time constant of R1 and C11 in the past after, the change in voltage that the voltage of R1-C11 intersection point has been caught up with the VDD pin becomes logic high, this high level arrives the grid of Mp13 through the two-stage inverter, and with its shutoff.Simultaneously, the high level of R1-C11 intersection point is opened Mp14 through the grid of one-level inverter arrival Mp14.After Mp14 opens, capacitor C 12 begins charging, and Mp14 can equivalence be a resistance, then passes through after the equivalent time constant of Mp14 and C12, the top crown voltage of C12 is drawn high, the anti-phase grid that is transmitted to Mp16 of inverter that this high level forms via Mp15 and Mn15.Open from This Side for Mp16, and the same with the analysis of C12 part with Mp14, after the equivalent time constant via Mp16 and C13, the top crown voltage of C13 is drawn high, and then Mn13 opens, and the grid voltage of clamp transistor Mbig1 is dragged down, and finishes the esd protection process.
When the charging voltage that normally powers on was applied to the VDD pin, the voltage one that the voltage of R1-C11 intersection point can be followed the VDD pin changed.When R1-C11 intersection point and VDD were low level, inverter can't work, and the Mbig1 grid voltage is in low level state.When the voltage of the intersection point of R1-C11 structure and VDD pin was drawn high simultaneously, Mp13 turn-offed, Mn13 opens, and has guaranteed that Mbig1 is in the state of shutoff, has guaranteed that namely Mbig1 is not triggered when normally powering on.
The advantage of circuit shown in Figure 1 is: the circuit that the control clamp transistor is opened and turn-offed has separated, the time constant of relative R1 and C11 is done the equivalent time constant sum of equivalent time constant and Mp16 and the C13 of large Mp14 and C12 so artificially, ignore the time constant of R1 and C11 for the impact of clamp transistor opening thereby be similar to, do little nargin for the time constant of R1 and C11.Secondly; even circuit shown in Figure 1 is by false triggering; Mbig1 also can be turned off after through the specific time constant of breaking circuit part; can not enter latch mode; but it can't be when integrated circuit need to be released more electrostatic charge; guarantee the sufficiently long opening time of clamp transistor, namely there is the space that promotes in circuit protection performance reliability shown in Figure 1.
Summary of the invention
The technical problem that (one) will solve
The technical problem to be solved in the present invention is: how further to prolong the opening time of clamp transistor, improve the reliability of esd protection.
(2) technical scheme
For solving the problems of the technologies described above; the invention provides a kind of power supply clamper esd protection circuit that utilizes current mirror; described power supply clamper esd protection circuit comprises: the electric capacity-resistive module, clamp transistor opening module and the clamp transistor that connect successively; also comprise: clamp transistor turn-offs module; be connected with clamp transistor with described electric capacity-resistive module respectively
Described electric capacity-resistive module, whether the pulse for the power pin VDD that identifies described power supply clamper esd protection circuit is electrostatic discharge pulses, if, then send the first response signal to described clamp transistor opening module, through behind the equivalent time constant of described electric capacity-resistive module, send the second response signal to described clamp transistor and turn-off module;
Described clamp transistor opening module is used for starting described clamp transistor according to described the first response signal;
Described clamp transistor turn-offs module, is used for turn-offing described clamp transistor according to described the second response signal;
Described clamp transistor is used for when starting the electrostatic charge that the described electrostatic discharge pulses of releasing is brought.
Preferably; described electric capacity-resistive module comprises: current lens unit; capacitor C 21; and resistance R 2; described current lens unit is connected with the first end that the first end of described capacitor C 21 is connected with resistance R respectively; described current lens unit is connected module with described clamp transistor opening module with clamp transistor respectively with the tie point of resistance R 2 and is connected; the second end of described capacitor C 21 is connected with the power pin VDD of described power supply clamper esd protection circuit; the second end ground connection of described resistance R 2, described current lens unit is connected with the power pin VDD of described power supply clamper esd protection circuit.
Preferably; described current lens unit comprises: nmos pass transistor Mns1; Mns2; the grid of described nmos pass transistor Mns1; the drain electrode of described nmos pass transistor Mns1; and the grid of described nmos pass transistor Mns2 interconnects; and tie point is connected with the first end of described capacitor C 21; the second end of described capacitor C 21 is connected with the drain electrode of described nmos pass transistor Mns2; and tie point is connected with the power pin VDD of described power supply clamper esd protection circuit; the source electrode of described nmos pass transistor Mns1 is connected with the source electrode of described nmos pass transistor Mns2, and tie point is connected with the first end of described resistance R 2.
Preferably; described clamp transistor is nmos pass transistor Mbig2; the drain electrode of described nmos pass transistor Mbig2 is connected with the power pin VDD of described power supply clamper esd protection circuit; the source ground of described nmos pass transistor Mbig2, the grid of described nmos pass transistor Mbig2 are connected module with described clamp transistor opening module with clamp transistor respectively and are connected.
Preferably; described clamp transistor opening module comprises: PMOS transistor Mp2-1; Mp2-2; Mp23; and nmos pass transistor Mn22; the grid of described PMOS transistor Mp2-2 is connected with drain electrode; and tie point is connected with the source electrode of described PMOS transistor Mp2-1; the source electrode of described PMOS transistor Mp2-2 is connected with the power pin VDD of described power supply clamper esd protection circuit; the grid of described PMOS transistor Mp2-1 is connected with described electric capacity-resistive module; the drain electrode of described PMOS transistor Mp2-1 is connected with the drain electrode of described nmos pass transistor Mn22; and tie point is connected with the grid of described PMOS transistor Mp23; the grid of described nmos pass transistor Mn22 is connected with the power pin VDD of described power supply clamper esd protection circuit; the source ground of described nmos pass transistor Mn22; the drain electrode of described PMOS transistor Mp23 is connected with described clamp transistor, and the source electrode of described PMOS transistor Mp23 is connected with the power pin VDD of described power supply clamper esd protection circuit.
Preferably; described clamp transistor turn-offs module and comprises: PMOS transistor Mp24; Mp25; Mp26; nmos pass transistor Mn23; Mn25; and capacitor C 22; C23; the grid of described PMOS transistor Mp24 is connected with described electric capacity-resistive module; the source electrode of described PMOS transistor Mp24 is connected with the power pin VDD of described power supply clamper esd protection circuit; the drain electrode of described PMOS transistor Mp24 is connected with an end of capacitor C 22; and tie point respectively with the grid of described PMOS transistor Mp25 be connected the grid of nmos pass transistor Mn25 and be connected; the other end ground connection of described capacitor C 22; the source electrode of described PMOS transistor Mp25 is connected with the power pin VDD of described power supply clamper esd protection circuit; the drain electrode of described PMOS transistor Mp25 be connected the drain electrode of nmos pass transistor Mn25 and connect; and tie point is connected with the grid of described PMOS transistor Mp26; the source ground of described nmos pass transistor Mn25; the source electrode of described PMOS transistor Mp26 is connected with the power pin VDD of described power supply clamper esd protection circuit; the drain electrode of described PMOS transistor Mp26 is connected with an end of capacitor C 23; and tie point is connected with the grid of described nmos pass transistor Mn23; the other end ground connection of described capacitor C 23; the source ground of described nmos pass transistor Mn23, the drain electrode of described nmos pass transistor Mn23 is connected with described clamp transistor.
(3) beneficial effect
The present invention is by introducing current-mirror structure in power supply clamper esd protection circuit; so that the capacitor equivalent in electric capacity-resistive module increases several times; and prolonged opening time of clamp transistor; improved the reliability of esd protection; in addition; the circuit structure that the present invention proposes uses novel invertor to substitute the opening time that conventional inverter has also prolonged clamp transistor; demand when satisfying integrated circuit static electricity discharge electric charge has guaranteed that clamp transistor relieving capacity during esd protection is stabilized in a high level.
Description of drawings
Fig. 1 is the concrete structure schematic diagram of existing power supply clamper esd protection circuit;
Fig. 2 is the schematic block circuit diagram according to the power supply clamper esd protection circuit that utilizes current mirror of one embodiment of the present invention;
Fig. 3 is the concrete structure schematic diagram of the power supply clamper esd protection circuit that utilizes current mirror shown in Figure 2;
Fig. 4 is the structural representation of electric capacity-resistive module in the power supply clamper esd protection circuit that utilizes current mirror shown in Figure 2;
Fig. 5 is used for simulating the pulse voltage temporal evolution schematic diagram that ESD impacts in the Hspice software emulation process;
Fig. 6 is that R1-C11 adds inverter structure, C21-R2 structure and C21-R2 and adds separately output voltage temporal evolution schematic diagram of current-mirror structure under ESD shown in Figure 5 impacts;
Fig. 7 is that C21-R2 adds the output voltage of current-mirror structure under ESD impacts as the input voltage of novel invertor and conventional counter device, both output voltage temporal evolution schematic diagrames;
Fig. 8 be power supply clamper esd protection circuit shown in Figure 1 under ESD shown in Figure 5 impacts, its clamper clamp transistor grid voltage temporal evolution schematic diagram;
Fig. 9 be power supply clamper esd protection circuit shown in Figure 3 under ESD shown in Figure 5 impacts, its clamper clamp transistor grid voltage temporal evolution schematic diagram.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used for explanation the present invention, but are not used for limiting the scope of the invention.
Core concept of the present invention is: by introduce current-mirror structure in power supply clamper esd protection circuit; so that the capacitor equivalent in electric capacity-resistive module increases several times; so just can do the electric capacity in electric capacity-resistive module littlely, thereby not affect in theory the opening time of clamp transistor.Simultaneously; the circuit structure that the present invention proposes uses novel invertor to substitute conventional inverter and has also brought the prolongation of clamp transistor open-interval, and the existence of novel invertor has guaranteed that also clamp transistor relieving capacity during esd protection is stabilized in a high level.
Fig. 2 is the power supply clamper esd protection circuit structural representation that utilizes current mirror according to one embodiment of the present invention; described power supply clamper esd protection circuit comprises: the electric capacity-resistive module 1, clamp transistor opening module 2 and the clamp transistor 4 that connect successively; also comprise: clamp transistor turn-offs module 3; are connected with clamp transistor with described electric capacity-resistive module 1 respectively and are connected
Described electric capacity-resistive module 1, whether the pulse for the power pin VDD that identifies described power supply clamper esd protection circuit is electrostatic discharge pulses, if, then send the first response signal to described clamp transistor opening module 2, through behind the equivalent time constant of described electric capacity-resistive module 1, send the second response signal to described clamp transistor and turn-off module 3;
Described clamp transistor opening module 2 is used for starting described clamp transistor 4 according to described the first response signal;
Described clamp transistor turn-offs module 3, is used for turn-offing described clamp transistor 4 according to described the second response signal;
Described clamp transistor 4 is used for when starting the electrostatic charge that the described electrostatic discharge pulses of releasing is brought.
Described electric capacity-resistive module 1 comprises: current lens unit 1-1; capacitor C 21; and resistance R 2; described current lens unit 1-1 is connected with the first end that the first end of described capacitor C 21 is connected with resistance R respectively; described current lens unit 1-1 is connected module 3 with described clamp transistor opening module 2 respectively with the tie point of resistance R 2 and is connected with clamp transistor; the second end of described capacitor C 21 is connected with the power pin VDD of described power supply clamper esd protection circuit; the second end ground connection of described resistance R 2, described current lens unit 1-1 is connected with the power pin VDD of described power supply clamper esd protection circuit.
Described current lens unit 1-1 comprises: nmos pass transistor Mns1; Mns2; the grid of described nmos pass transistor Mns1; the drain electrode of described nmos pass transistor Mns1; and the grid of described nmos pass transistor Mns2 interconnects; and tie point is connected with the first end of described capacitor C 21; the second end of described capacitor C 21 is connected with the drain electrode of described nmos pass transistor Mns2; and tie point is connected with the power pin VDD of described power supply clamper esd protection circuit; the source electrode of described nmos pass transistor Mns1 is connected with the source electrode of described nmos pass transistor Mns2, and tie point is connected with the first end of described resistance R 2.
Described clamp transistor 4 is nmos pass transistor Mbig2; the drain electrode of described nmos pass transistor Mbig2 is connected with the power pin VDD of described power supply clamper esd protection circuit; the source ground of described nmos pass transistor Mbig2, the grid of described nmos pass transistor Mbig2 are connected module 3 with described clamp transistor opening module 2 respectively and are connected with clamp transistor.
Described clamp transistor opening module 2 comprises: PMOS transistor Mp2-1; Mp2-2; Mp23; and nmos pass transistor Mn22; the grid of described PMOS transistor Mp2-2 is connected with drain electrode; and tie point is connected with the source electrode of described PMOS transistor Mp2-1; the source electrode of described PMOS transistor Mp2-2 is connected with the power pin VDD of described power supply clamper esd protection circuit; the grid of described PMOS transistor Mp2-1 is connected with described electric capacity-resistive module 1; the drain electrode of described PMOS transistor Mp2-1 is connected with the drain electrode of described nmos pass transistor Mn22; and tie point is connected with the grid of described PMOS transistor Mp23; the grid of described nmos pass transistor Mn22 is connected with the power pin VDD of described power supply clamper esd protection circuit; the source ground of described nmos pass transistor Mn22; the drain electrode of described PMOS transistor Mp23 is connected with described clamp transistor 4, and the source electrode of described PMOS transistor Mp23 is connected with the power pin VDD of described power supply clamper esd protection circuit.
Described clamp transistor turn-offs module 3 and comprises: PMOS transistor Mp24; Mp25; Mp26; nmos pass transistor Mn23; Mn25; and capacitor C 22; C23; the grid of described PMOS transistor Mp24 is connected with described electric capacity-resistive module 1; the source electrode of described PMOS transistor Mp24 is connected with the power pin VDD of described power supply clamper esd protection circuit; the drain electrode of described PMOS transistor Mp24 is connected with an end of capacitor C 22; and tie point respectively with the grid of described PMOS transistor Mp25 be connected the grid of nmos pass transistor Mn25 and be connected; the other end ground connection of described capacitor C 22; the source electrode of described PMOS transistor Mp25 is connected with the power pin VDD of described power supply clamper esd protection circuit; the drain electrode of described PMOS transistor Mp25 be connected the drain electrode of nmos pass transistor Mn25 and connect; and tie point is connected with the grid of described PMOS transistor Mp26; the source ground of described nmos pass transistor Mn25; the source electrode of described PMOS transistor Mp26 is connected with the power pin VDD of described power supply clamper esd protection circuit; the drain electrode of described PMOS transistor Mp26 is connected with an end of capacitor C 23; and tie point is connected with the grid of described nmos pass transistor Mn23; the other end ground connection of described capacitor C 23; the source ground of described nmos pass transistor Mn23, the drain electrode of described nmos pass transistor Mn23 is connected with described clamp transistor 4.
The power supply clamper esd protection circuit that utilizes current mirror that present embodiment proposes is with respect to first improvements of circuit shown in Figure 1: described electric capacity-resistive module adds current-mirror structure with C21-R2 and has replaced original R1-C11 to add inverter structure (namely being comprised of R1, C11, Mp11 and Mn11 among Fig. 1).
At first, (be about to the position that C21 places R1 with the C21-R2 structure, R2 is placed the position of C11, and the structure after Mp11 and Mn11 removed) substituting the benefit that R1-C11 adds inverter structure is: C21-R2 structure and R1-C11 structure are under the ESD impact, the voltage of its output node is opposite in synchronization logic value, and the voltage of output node (being the drain electrode of Mp11 among Fig. 1) that C21-R2 structure output node (being C21 and the tie point of R2) and R1-C11 add inverter structure is identical in synchronization logic value.So only be to have changed the electric capacity-electric capacity of resistive module part and the position of resistance, the benefit of the circuit inverter structure decrease one-level that just can be protected.Secondly; there is a logic threshold voltage in conventional inverter; when input voltage equals logic threshold voltage; output voltage has a very large saltus step; so it is larger than the drop-down slope of the output voltage of C21-R2 structure that R1-C11 adds the output voltage of inverter under ESD impacts; so adopt in the protective circuit of C21-R2 structure, the opening time of clamp transistor unlatching path the inside Mp23 is longer, causes the clamp transistor open-interval to prolong.
Secondly, the C21-R2 structure adds current-mirror structure (being the structure of electric capacity-resistive module) and replaces the benefit of C21-R2 structure to be: as shown in Figure 4, establish X that Mns2 is of a size of Mns1 doubly, because Mns1 is identical with the grid source current of Mns2, being similar to has: I
Mns2=X*I
Mns1=X*I
C21, wherein, I
Mns2Refer to the electric current that flows through the Mns2 branch road, I
Mns1Refer to the electric current that flows through the Mns1 branch road, because Mns1 and capacitor C 21 are on a branch road, so I
Mns1=I
C21So the electric current that A is ordered is: I
A=(X+1) * I
C21By the relation of electric capacity both end voltage and electric current, the electric current of the capacitor C of flowing through as can be known 21 is: I
C21=C21*dV
C21/ dt, simultaneously I
A=C
AB* dV
AB/ dt, C
ABBe the equivalent capacity between A point and the B point.The I that has derived
AWith I
C21Relation with two the formula simultaneous in front, have: C
AB* dV
AB/ dt=(X+1) * C21*dV
C21/ dt is as approximate dV
AB/ dt ≈ dV
C21So/dt is C
AB=(X+1) * C21.In the present embodiment, get X=9, so in theory, circuit shown in Figure 2 only needs the capacitance size setting of C11/10 in the circuit shown in Figure 1 just can under ESD impacts, obtain the reaction effect same with Fig. 1.
Fig. 6 has showed the output waveform of the three kinds of structures in front under ESD shown in Figure 5 impacts.V1 represents that R1-C11 adds the output waveform of inverter structure among the figure, and V2 represents the output waveform of C21-R2 structure, and V3 represents that C21-R2 adds the output waveform of current-mirror structure (being the voltage that B is ordered among Fig. 4).Result among the figure can find out: from upper tentering degree, V1 is maximum, and V2 takes second place, and V3 is minimum.Drop-down speed after voltage reaches amplitude, V1 is maximum, and V2 takes second place, and V3 is minimum.In the analysis here, drop-down speed upper tentering degree than voltage itself in the opening time of control clamp transistor accounts for leading, so C21-R2 adds logic threshold voltages of that grade inverter before the more late Mp3 of reaching of the more front two kinds of structures of the output waveform of current-mirror structure, so adding current-mirror structure, C21-R2 can effectively prolong the opening time of clamp transistor under ESD impacts.
What be worth explanation a bit is: C21-R2 adds current-mirror structure to be done little 10 times to electric capacity and not to reach later the ESD reaction effect the same with original C21-R2 structure.This is because the theory derivation of front itself just has the processing of two step approximation relations, so theoretical analysis does not have the result of accurately predicting emulation, but in the approximate situation qualitatively prediction effect still reached.The upper tentering degree that result from Fig. 6: C21-R2 adds current-mirror structure is large not as good as the C21-R2 structure, this is because the voltage that C21-R2 adds current mirror structure output node equals the drain-source voltage that the lower step voltage of C21 deducts Mns1, and the output voltage of C21-R2 structure directly is exactly the lower step voltage of C21.Simultaneously, it is a lot of slowly that C21-R2 adds the drop-down speed ratio C21-R2 structure that current-mirror structure reaches after the voltage magnitude, this is because C21-R2 adds in the current-mirror structure, R2 will be subjected to stopping of current-mirror structure to the effect of releasing of the upper stored charge of C21, and R2 directly releases to the electric charge of the upper accumulation of C21 in the C21-R2 structure.
The power supply clamper esd protection circuit that utilizes current mirror that present embodiment proposes is with respect to second improvements of circuit shown in Figure 1: use the novel invertor that is comprised of Mp2-1, Mp2-2 and Mn22 to substitute the conventional inverter that Mp12 and Mn12 form.Fig. 7 has showed that at same input voltage (be the grid voltage of Mp2-1 to novel reverser, be the grid voltage of Mp12 to the conventional counter device, shown in the Vin among the figure) under, the novel invertor output voltage (is the drain voltage of Mp2-1, shown in Vout2 among the figure) with the difference of conventional inverter output voltage (being the drain voltage of Mp12, shown in Vout1 among the figure).As can be seen from the figure: the output voltage of novel invertor compares to conventional inverter and more draws evening, and the amplitude of drawing on the novel invertor output voltage is large not as good as conventional inverter.On draw time lag so that Mbig opens the more late shutoff of path, the amplitude of drawing on the voltage simultaneously is large so that the shutoff of Mp3 is more weak not as good as conventional inverter, these two conditions all so that the clamp transistor opening time prolong.More noticeablely be: although novel invertor draws on beginning than conventional inverter is more late, by the pulling rate rate is very fast thereon, so reach a stable amplitude than conventional inverter is more Zao.
The novel invertor output voltage than the reason of drawing time lag on the conventional inverter output voltage is: novel invertor has adopted the Mp2-2 of diode connection as the load of Mp2-1.Because in the novel invertor, Mn22 is permanent conducting, approximate analysis can be thought: when the grid voltage of Mp2-1 reached VDD-2|Vthp|, the grid voltage of Mp23 was just dragged down.For conventional inverter, the grid voltage of Mp22 reaches VDD-|Vthp|, the grid voltage of Mp23 just begins to be dragged down, so the input voltage of novel invertor needs a longer time to reach the twice to VDD naturally | the offset level of Vthp|, so that the prolongation of clamp transistor opening time.Wherein, Vthp represents the transistorized threshold voltage of PMOS
The novel invertor output voltage than the reason that the tentering degree is little on the conventional inverter output voltage is: novel invertor has adopted the transistor Mn22 of permanent conducting to make the current source of novel invertor, because there is a drop-down effect in permanent conducting Mn22 for the grid voltage of Mp23 always, so that even the grid voltage of Mp23 also can't reach the VDD level in equivalent C21-R2 time constant in the past, cause the clamp transistor opening time to prolong.Want above-mentioned novel invertor and realize correct logic function, the relative size of pipe is very important, and the size of Mn22 arranges little much than the size of Mp2-1 and Mp2-2 here.
Fig. 8 is the variation of primary circuit structure Mbig1 grid voltage under ESD impacts; Fig. 9 is the variation of the circuit structure that proposes of the present invention Mbig2 grid voltage under ESD impacts.As can be seen from Figure 8: the grid voltage of Mbig1 is also unstable between whole impact epoch, this is because after Mp13 turn-offs and before the Mn13 unlatching, the grid voltage of Mbig1 is suspended in Mp13 and turn-offs state constantly, but exists by the leakage current of Mn13 or the drop-down path of subthreshold voltage.After Mn13 opened, the grid voltage of Mbig1 was just dragged down fully by Mn13, and this is the source of two drop-down areas among Fig. 8.After for the first time drop-down, the grid voltage of Mbig1 still is enough to so that Mbig1 opens among Fig. 8, but strong when its relieving capacity for electrostatic charge has been not so good as just to have triggered.The result of Fig. 9 shows: by the improvement principle of front surface analysis, the opening time of Mbig2 is effectively prolonged, and the grid voltage open period of Mbig2 is stable at the VDD level basically always simultaneously, and these 2 all is the strong performance of protective value Reliability Enhancement.For the ease of relatively, opening time of Mbig2 is quantized, with the threshold voltage of 0.4V as Mbig2.The opening time of Mbig1 is in the circuit structure shown in Figure 1: 340.9nS, the opening time of Mbig2 is in the circuit structure shown in Figure 3: 585.1nS.
The operation principle of the power supply clamper esd protection circuit that utilizes current mirror that present embodiment proposes is: when the esd pulse that is nanosecond or tens of nanosecond orders when a rise time is added to power pin VDD; the power pin VDD that the source voltage of described nmos pass transistor Mns1 can be followed high reliability power supply clamper esd protection circuit in the present embodiment comparatively fast reaches a high value; at this moment PMOS transistor Mp2-1 turn-offs; the grid of PMOS transistor Mp23 is pulled down to low level by nmos pass transistor Mn22; then PMOS transistor Mp23 opens; the grid voltage of clamp transistor Mbig2 is moved to high level; clamp transistor Mbig2 starts, the Mbig2 electrostatic charge that described electrostatic impact brings that begins to release.
Next the source voltage of described nmos pass transistor Mns1 can descend with a slope that is determined by equivalent C21-R2 time constant, in the approximate situation, the source voltage of described nmos pass transistor Mns1 drops to after the VDD-2|Vthp|, Mp2-1 and Mp2-2 will open, drawing on the grid voltage of PMOS transistor Mp23, so that Mp23 turn-offs, this moment, the grid step voltage of clamp transistor Mbig2 can be suspended in level before, so Mbig2 can continue to open.
Meanwhile, when the source voltage of described nmos pass transistor Mns1 dropped to VDD-|Vthp|, PMOS transistor Mp24 entered opening, and the drain voltage of Mp24 is drawn high.Because PMOS transistor Mp24 and capacitor C 22 have formed the R-C delay structure of an equivalence, thus the drain voltage of Mp24 on draw and have a corresponding R-C time delay.After this time delay, the drain voltage of Mp24 reaches a higher level, by the inverter of Mp25 and Mn25 composition, so that the grid voltage of Mp26 becomes low level, then Mp26 conducting, through the time delay that is determined by Mp26 and capacitor C 23, the grid voltage of Mn23 by on draw and be high level, like this Mn23 conducting drags down the grid voltage of clamp transistor Mbig2, it is turn-offed, the action of the esd pulse that finishes to release.
In the situation about normally powering on, power pin VDD with a slower slope by on draw, the electric charge of C1 accumulation can be released timely by R like this, so the source voltage of described nmos pass transistor Mns1 is in a lower level value always, so that the grid of Mp23 is in high level state all the time, so not conducting of Mp23, so that the grid voltage of Mbig2 can't on draw, in this case, Mbig2 can not be triggered, and has guaranteed correct work-based logic.
In a word, the circuit that the present invention proposes was prolonged greatly with respect to the opening time of circuit shown in Figure 1 clamp transistor under ESD impacts, this point given C21-R2 do hour between the larger nargin of constant.The C21-R2 time constant is done little, has both met the trend of scaled down, has also improved the prevention ability of circuit for false triggering.Simultaneously, between impact epoch, the ducting capacity of clamp transistor is stabilized in a stronger level to the circuit that the present invention proposes at ESD, and this circuit that is the present invention proposes improves the another one aspect of esd protection performance reliability.
Above execution mode only is used for explanation the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; in the situation that does not break away from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (3)
1. power supply clamper esd protection circuit that comprises current mirror; it is characterized in that; described power supply clamper esd protection circuit comprises: the electric capacity-resistive module (1), clamp transistor opening module (2) and the clamp transistor (4) that connect successively; also comprise: clamp transistor turn-offs module (3); be connected 4 with described electric capacity-resistive module (1) with clamp transistor respectively) be connected
Described electric capacity-resistive module (1), whether the pulse for the power pin VDD that identifies described power supply clamper esd protection circuit is electrostatic discharge pulses, if, then send the first response signal to described clamp transistor opening module (2), behind the equivalent time constant through described electric capacity-resistive module (1), send the second response signal to described clamp transistor and turn-off module (3);
Described clamp transistor opening module (2) is used for starting described clamp transistor (4) according to described the first response signal;
Described clamp transistor turn-offs module (3), is used for turn-offing described clamp transistor (4) according to described the second response signal;
Described clamp transistor (4) is used for when starting the electrostatic charge that the described electrostatic discharge pulses of releasing is brought;
Described electric capacity-resistive module (1) comprising: current lens unit (1-1), capacitor C 21, and resistance R 2, described current lens unit (1-1) is connected with the first end that the first end of described capacitor C 21 is connected with resistance R respectively, described current lens unit (1-1) is connected module (3) with described clamp transistor opening module (2) respectively with the tie point of resistance R 2 and is connected with clamp transistor, the second end of described capacitor C 21 is connected with the power pin VDD of described power supply clamper esd protection circuit, the second end ground connection of described resistance R 2, described current lens unit (1-1) is connected with the power pin VDD of described power supply clamper esd protection circuit;
Described current lens unit (1-1) comprising: nmos pass transistor Mns1, Mns2, the grid of described nmos pass transistor Mns1, the drain electrode of described nmos pass transistor Mns1, and the grid of described nmos pass transistor Mns2 interconnects, and tie point is connected with the first end of described capacitor C 21, the second end of described capacitor C 21 is connected with the drain electrode of described nmos pass transistor Mns2, and tie point is connected with the power pin VDD of described power supply clamper esd protection circuit, the source electrode of described nmos pass transistor Mns1 is connected with the source electrode of described nmos pass transistor Mns2, and tie point is connected with the first end of described resistance R 2;
Described clamp transistor opening module (2) comprising: PMOS transistor Mp2-1; Mp2-2; Mp23; and nmos pass transistor Mn22; the grid of described PMOS transistor Mp2-2 is connected with drain electrode; and tie point is connected with the source electrode of described PMOS transistor Mp2-1; the source electrode of described PMOS transistor Mp2-2 is connected with the power pin VDD of described power supply clamper esd protection circuit; the grid of described PMOS transistor Mp2-1 is connected with described electric capacity-resistive module (1); the drain electrode of described PMOS transistor Mp2-1 is connected with the drain electrode of described nmos pass transistor Mn22; and tie point is connected with the grid of described PMOS transistor Mp23; the grid of described nmos pass transistor Mn22 is connected with the power pin VDD of described power supply clamper esd protection circuit; the source ground of described nmos pass transistor Mn22; the drain electrode of described PMOS transistor Mp23 is connected with described clamp transistor (4), and the source electrode of described PMOS transistor Mp23 is connected with the power pin VDD of described power supply clamper esd protection circuit.
2. the power supply clamper esd protection circuit that comprises current mirror as claimed in claim 1; it is characterized in that; described clamp transistor (4) is nmos pass transistor Mbig2; the drain electrode of described nmos pass transistor Mbig2 is connected with the power pin VDD of described power supply clamper esd protection circuit; the source ground of described nmos pass transistor Mbig2, the grid of described nmos pass transistor Mbig2 are connected module (3) with described clamp transistor opening module (2) respectively and are connected with clamp transistor.
3. the power supply clamper esd protection circuit that comprises current mirror as claimed in claim 1 or 2; it is characterized in that; described clamp transistor turn-offs module (3) and comprising: PMOS transistor Mp24; Mp25; Mp26; nmos pass transistor Mn23; Mn25; and capacitor C 22; C23; the grid of described PMOS transistor Mp24 is connected with described electric capacity-resistive module (1); the source electrode of described PMOS transistor Mp24 is connected with the power pin VDD of described power supply clamper esd protection circuit; the drain electrode of described PMOS transistor Mp24 is connected with an end of capacitor C 22; and tie point respectively with the grid of described PMOS transistor Mp25 be connected the grid of nmos pass transistor Mn25 and be connected; the other end ground connection of described capacitor C 22; the source electrode of described PMOS transistor Mp25 is connected with the power pin VDD of described power supply clamper esd protection circuit; the drain electrode of described PMOS transistor Mp25 be connected the drain electrode of nmos pass transistor Mn25 and connect; and tie point is connected with the grid of described PMOS transistor Mp26; the source ground of described nmos pass transistor Mn25; the source electrode of described PMOS transistor Mp26 is connected with the power pin VDD of described power supply clamper esd protection circuit; the drain electrode of described PMOS transistor Mp26 is connected with an end of capacitor C 23; and tie point is connected with the grid of described nmos pass transistor Mn23; the other end ground connection of described capacitor C 23; the source ground of described nmos pass transistor Mn23, the drain electrode of described nmos pass transistor Mn23 is connected with described clamp transistor (4).
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102543963B (en) * | 2012-02-09 | 2013-10-09 | 浙江大学 | Electronic static discharge (ESD) detection clamping circuit based on multi-stage current mirrors |
| CN102723702A (en) * | 2012-06-20 | 2012-10-10 | 上海华力微电子有限公司 | Dual-feedback power supply clamp used for on-chip electrostatic discharge protection |
| CN103001200B (en) * | 2012-12-14 | 2015-04-22 | 北京大学 | Multiple RC triggered power supply clamp electro-static discharge (ESD) protective circuit |
| CN103107528B (en) * | 2012-12-26 | 2014-12-10 | 北京大学 | Power clamping electrostatic discharge protection circuit |
| CN103078305B (en) * | 2013-01-09 | 2015-02-04 | 北京大学 | Anti-false-triggering power supply clamp ESD (Electro-Static Discharge) protection circuit |
| CN104242280A (en) * | 2013-06-09 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic protection circuit |
| TWI511400B (en) * | 2014-05-02 | 2015-12-01 | Univ Nat Chiao Tung | Active guard ring and ring circuit to improve latch-up immunity |
| CN106451396B (en) * | 2016-11-30 | 2018-10-16 | 上海华力微电子有限公司 | A kind of power supply clamp ESD protection circuit structure |
| CN107706896A (en) * | 2017-10-19 | 2018-02-16 | 丹阳恒芯电子有限公司 | A kind of latch electrostatic discharge protective circuit in Internet of Things |
| CN109245078A (en) * | 2018-10-22 | 2019-01-18 | 深圳讯达微电子科技有限公司 | A kind of power clamp circuit for ESD protection |
| CN110855277B (en) * | 2019-12-02 | 2021-07-23 | 思瑞浦微电子科技（苏州）股份有限公司 | Adjustable clamping circuit |
| CN112289788B (en) * | 2020-10-16 | 2022-01-21 | 福建省晋华集成电路有限公司 | MOS transistor electrostatic protection circuit and electronic device |
| CN115083475A (en) * | 2022-06-09 | 2022-09-20 | 华中科技大学 | High-speed large-current pulse circuit, phase change memory operation circuit and operation method |
| CN116388136B (en) * | 2023-06-01 | 2023-07-28 | 盈力半导体(上海)有限公司 | Surge current limiting circuit and chip |
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| CN1658388A (en) * | 2004-02-18 | 2005-08-24 | 富士通株式会社 | Electrostatic discharge protection circuit |
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| JP2002328732A (en) * | 2001-05-07 | 2002-11-15 | Texas Instr Japan Ltd | Reference voltage generating circuit |
| US7102864B2 (en) * | 2004-06-14 | 2006-09-05 | King Billion Electronics Co., Ltd. | Latch-up-free ESD protection circuit using SCR |
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| CN1658388A (en) * | 2004-02-18 | 2005-08-24 | 富士通株式会社 | Electrostatic discharge protection circuit |
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