CN112289788B - MOS transistor electrostatic protection circuit and electronic device - Google Patents

MOS transistor electrostatic protection circuit and electronic device Download PDF

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Publication number
CN112289788B
CN112289788B CN202011111682.5A CN202011111682A CN112289788B CN 112289788 B CN112289788 B CN 112289788B CN 202011111682 A CN202011111682 A CN 202011111682A CN 112289788 B CN112289788 B CN 112289788B
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mos transistor
module
logic gate
resistance
electrically connected
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CN112289788A (en
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朴珉晧
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Fujian Jinhua Integrated Circuit Co Ltd
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Fujian Jinhua Integrated Circuit Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Abstract

The application provides a MOS transistor electrostatic protection circuit and an electronic device. The MOS transistor electrostatic protection circuit includes: a MOS transistor; and a control unit wired or wirelessly connected to the MOS transistor, for extending a time of a predetermined amount of charge flowing through the MOS transistor such that the amount of charge flowing through the MOS transistor per unit time is reduced such that a maximum value of a voltage applied to the MOS transistor is smaller than a breakdown voltage of the MOS transistor. The control unit is adopted to prolong the time of the preset charge quantity flowing through the MOS transistor so as to reduce the charge quantity flowing through the MOS transistor in unit time, so that the maximum value of the voltage loaded on the MOS transistor is smaller than the breakdown voltage of the MOS transistor, even if the electrostatic voltage is larger, the MOS transistor cannot be broken down, and the protection of the MOS transistor when the electrostatic voltage is larger is realized.

Description

MOS transistor electrostatic protection circuit and electronic device
Technical Field
The present disclosure relates to the field of electrostatic protection of MOS transistors, and more particularly, to an electrostatic protection circuit of MOS transistors and an electronic device.
Background
In the prior art, since the peak voltage generated by the electrostatic discharge is high and is often higher than the breakdown voltage of the MOS transistor, so that the MOS transistor is broken down, as shown in fig. 1, the electrostatic protection circuit of the GCNMOS is a conventional electrostatic protection circuit, which is composed of a resistor R1, a capacitor C1, a GCPMOS transistor P1, a GCNMOS transistor N1 and a GCNMOS transistor N2, when the static electricity is generated at the a terminal, the protection of the GCNMOS transistor N4 is realized, as shown in fig. 2, but when the static voltage Vpeak is large, the peak value of the voltage applied between the gate and the source of the GCNMOS transistor N4 is still higher than the breakdown voltage V of the MOS transistorBDSo that the MOS transistor is broken down.
Disclosure of Invention
The present disclosure provides an electrostatic protection circuit and an electronic device for MOS transistors, so as to solve the problem in the prior art that when the electrostatic voltage is large, the MOS transistor is still broken down.
In order to achieve the above object, according to one aspect of the present application, there is provided a MOS transistor electrostatic protection circuit including: a MOS transistor; and a control unit connected to the MOS transistor by wire or wirelessly, for extending a time of a predetermined amount of charge flowing through the MOS transistor such that the amount of charge flowing through the MOS transistor per unit time is reduced such that a maximum value of a voltage applied to the MOS transistor is smaller than a breakdown voltage of the MOS transistor.
Further, the control unit includes: the first resistance-capacitance unit comprises a first resistance module and a first capacitance module, and the first resistance module is electrically connected with the first capacitance module; the second resistance-capacitance unit comprises a second resistance module and a second capacitance module, and the second resistance module is electrically connected with the second capacitance module; and the logic gate unit is electrically connected with the first resistance-capacitance unit and the second resistance-capacitance unit respectively and is used for controlling whether the first resistance-capacitance unit and the second resistance-capacitance unit are connected into the control unit or not.
Further, the logic gate unit includes: the first logic gate module is provided with an input end and an output end, the input end of the first logic gate module is electrically connected with the first resistor module, the output end of the first logic gate module is electrically connected with the MOS transistor, and the first logic gate module is used for reversing the phase of an output signal of the second end of the first resistor module by 180 degrees; and the second logic gate module is provided with an input end and an output end, the input end of the second logic gate module is electrically connected with the second resistor module, the output end of the second logic gate module is electrically connected with the grid electrode of the MOS transistor, and the second logic gate module is used for controlling whether the second resistor-capacitor unit is connected into the control unit or not.
Further, the first logic gate module is a first inverter, the second logic gate module is a first nand gate, the first nand gate has a first input end, a second input end and an output end, the first input end of the first nand gate is electrically connected to the second end of the second resistor module, the second input end of the first nand gate inputs an enable signal, the output end of the first nand gate is electrically connected to the gate of the MOS transistor, and the enable signal is a pulse signal.
Further, the first logic gate module comprises a second inverter and a first buffer, the second inverter is connected in series with the first buffer, the second logic gate module comprises a second nand gate and a second buffer, and the second nand gate is connected in series with the second buffer.
Further, under the condition that the second end of the first resistor module is connected with the second end of the second resistor module, the resistance value of the second resistor module is larger than that of the first resistor module.
Further, the first resistance module comprises one or more first resistances, the second resistance module comprises one or more second resistances, the first capacitance module comprises one or more first capacitances, and the second capacitance module comprises one or more second capacitances.
Further, the plurality of first resistors are connected in series or in parallel, the plurality of second resistors are connected in series or in parallel, the plurality of first capacitors are connected in series or in parallel, and the plurality of second capacitors are connected in series or in parallel.
According to another aspect of the present application, there is provided an electronic device including an MOS transistor electrostatic protection circuit and a pulse signal generator, the pulse signal generator being electrically connected to the MOS transistor electrostatic protection circuit, the MOS transistor electrostatic protection circuit being any one of the MOS transistor electrostatic protection circuits.
By applying the technical scheme of the application, the control unit is adopted to prolong the time of the preset charge quantity flowing through the MOS transistor, so that the charge quantity flowing through the MOS transistor in unit time is reduced, the maximum value of the voltage loaded on the MOS transistor is smaller than the breakdown voltage of the MOS transistor, even if the electrostatic voltage is larger, the MOS transistor cannot be broken down, and the protection of the MOS transistor when the electrostatic voltage is larger is realized.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 is a schematic diagram of an electrostatic protection circuit of a MOS transistor in the prior art;
FIG. 2 is a diagram illustrating the relationship between breakdown voltage and electrostatic voltage of a MOS transistor in the prior art;
FIG. 3 is a schematic diagram of an electrostatic protection circuit of a MOS transistor according to an embodiment of the present application;
FIG. 4 is a schematic diagram of another electrostatic protection circuit for MOS transistors according to an embodiment of the present application.
Wherein the figures include the following reference numerals:
01. a first resistance module; 02. a first capacitive module; 03. a second resistance module; 04. a second capacitive module; 05. a first inverter; 06. a first NAND gate; 10. MOS transistors.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background, in the prior art MOS transistor electrostatic protection circuit, when the electrostatic voltage is larger, the MOS transistor still breaks down, and in order to solve the problem that, as the MOS transistor electrostatic protection circuit, when the electrostatic voltage is larger, the MOS transistor still breaks down, embodiments of the present application provide a MOS transistor electrostatic protection circuit and an electronic device.
FIG. 3 is a schematic diagram of an electrostatic protection circuit of a MOS transistor according to an embodiment of the present application. As shown in fig. 3, the circuit includes:
a MOS transistor 10;
and a control unit wired or wirelessly connected to the MOS transistor 10, specifically, electrically connected to a gate of the MOS transistor 10, for extending a time of a predetermined charge amount flowing through the MOS transistor 10 so that the charge amount flowing through the MOS transistor 10 per unit time is reduced so that a maximum value of a voltage applied to the MOS transistor 10 is smaller than a breakdown voltage of the MOS transistor 10.
In the above-mentioned solution, the control unit is adopted to extend the time of the predetermined amount of charge flowing through the MOS transistor, so that the amount of charge flowing through the MOS transistor per unit time is reduced, so that the maximum value of the voltage applied to the MOS transistor is smaller than the breakdown voltage of the MOS transistor, and even if the electrostatic voltage is large, the MOS transistor is not broken down, thereby realizing the protection of the MOS transistor when the electrostatic voltage is large.
In an embodiment of the present application, as shown in fig. 3, the control unit includes a first resistance-capacitance unit, a second resistance-capacitance unit, and a logic gate unit, the first resistance-capacitance unit includes a first resistance module 01 and a first capacitance module 02, and the first resistance module 01 is electrically connected to the first capacitance module 02; the first resistor module 01 has a first end and a second end, the first end of the first resistor module 01 is electrically connected to a first power terminal VDD1, the first capacitor module 02 has a first end and a second end, the second end of the first resistor module 01 is electrically connected to the first end of the first capacitor module 02, and the second end of the first capacitor module 02 is grounded VSS; the second resistance-capacitance unit comprises a second resistance module 03 and a second capacitance module 04, and the second resistance module 03 is electrically connected with the second capacitance module 04; the second resistor module 03 has a first end and a second end, the first end of the second resistor module 03 is electrically connected to a second power terminal VDD2, the second end of the first resistor module 01 is connected or not connected to the second end of the second resistor module 03, the second capacitor module 04 has a first end and a second end, the second end of the second resistor module 03 is electrically connected to the first end of the second capacitor module 04, and the second end of the second capacitor module 04 is grounded VSS; the logic gate unit is electrically connected to the first resistance-capacitance unit and the second resistance-capacitance unit, and has a first input end, a second input end, and an output end, where the first input end of the logic gate unit is electrically connected to the second end of the first resistance module 01, the second input end of the logic gate unit is electrically connected to the second end of the second resistance module 03, the output end of the logic gate unit is electrically connected to the gate of the MOS transistor 10, and the logic gate unit is configured to control whether to connect the first resistance-capacitance unit and the second resistance-capacitance unit to the control unit. Under the combined action of the first resistance-capacitance unit, the second resistance-capacitance unit and the logic gate unit, the time of the preset charge quantity flowing through the MOS transistor is prolonged, so that the charge quantity flowing through the MOS transistor in unit time is reduced, the maximum value of the voltage loaded on the MOS transistor is smaller than the breakdown voltage of the MOS transistor, and the MOS transistor is protected when the electrostatic voltage is larger.
In another embodiment of the present application, the logic gate unit includes a first logic gate module and a second logic gate module, the first logic gate module has an input end and an output end, the input end of the first logic gate module is electrically connected to the second end of the first resistor module, the output end of the first logic gate module is electrically connected to the gate of the MOS transistor, the drain of the MOS transistor is electrically connected to the third power source, the source of the MOS transistor is grounded, the first logic gate module is a second logic gate module for inverting the phase of the output signal of the second end of the first resistor module by 180 °, and has an input end and an output end, the input end of the second logic gate module is electrically connected to the second end of the second resistor module, the output end of the second logic gate module is electrically connected to the gate of the MOS transistor, and the second logic gate module is used for controlling whether the second resistor-capacitor unit is connected to the control unit . Specifically, the first logic gate module may be any circuit component and combination of circuit components that can invert the output signal of the second end of the first resistor module, for example, a not gate, a combination of a transistor and a resistor, and the like. Whether the second resistance-capacitance unit is connected into the control unit or not is adaptively controlled according to the actual electrostatic voltage, namely the first resistance-capacitance unit has a time delay function and can prolong the time of the preset charge quantity flowing through the MOS transistor, but when the electrostatic voltage is larger, the second resistance-capacitance unit is connected into the control unit only by means of the fact that the first resistance-capacitance unit cannot enable the maximum value of the voltage loaded on the MOS transistor to be smaller than the breakdown voltage of the MOS transistor, in order to ensure the safety of the MOS transistor, under the condition that the first resistance-capacitance unit cannot meet the requirement, the second resistance-capacitance unit also plays a time delay function, the first resistance-capacitance unit and the second resistance-capacitance unit are combined to enable the time of the preset charge quantity flowing through the MOS transistor to be longer, and therefore the maximum value of the voltage loaded on the MOS transistor is smaller than the breakdown voltage of the MOS transistor, the protection of the MOS transistor is realized.
Specifically, fig. 3 shows a case where the second terminal of the first resistor module 01 is connected to the second terminal of the second resistor module 03, and fig. 4 shows a case where the second terminal of the first resistor module 01 is not connected to the second terminal of the second resistor module 03, and both the first resistor-capacitor unit and the second resistor-capacitor unit are connected or not connected to each other to perform a delay function. Only, when the second end of the first resistor module is connected to the second end of the second resistor module, the resistance of the second resistor module is much larger than that of the first resistor module, for example, the resistance of the second resistor module is ten times that of the first resistor module, and the fast delay pulse and the slow delay pulse are mixed into a smooth pulse; when the second end of the first resistor module is not connected with the second end of the second resistor module, the first resistor-capacitor unit and the second resistor-capacitor unit are separately controlled, and electrostatic protection of the MOS transistor is also realized.
In another embodiment of the present application, as shown in fig. 3 and 4, the first logic gate module is a first inverter 05, the second logic gate module is a first nand gate 06, the first nand gate 06 has a first input terminal, a second input terminal and an output terminal, the first input terminal of the first nand gate 06 is electrically connected to the second terminal of the second resistor module 03, the second input terminal of the first nand gate 06 inputs an enable signal, the output terminal of the first nand gate 06 is electrically connected to the gate of the MOS transistor 10, and the enable signal EN is a pulse signal (oscillation signal). Under the combined action of the first inverter 05 and the first nand gate 06, electrostatic protection of the MOS transistor 10 is realized.
In yet another embodiment of the present application, the control unit further includes an adder, an output end of the first inverter is electrically connected to a first input end of the adder, an output end of the first nand gate is electrically connected to a second input end of the adder, an output end of the adder is electrically connected to a gate of the MOS transistor, the adder is configured to superimpose an output signal of the first inverter and an output signal of the first nand gate, and under a combined action of the first inverter, the first nand gate, and the adder, electrostatic protection of the MOS transistor is achieved.
In yet another embodiment of the present application, the first logic gate module includes a second inverter and a first buffer, the second inverter is connected in series with the first buffer, an output terminal of the second inverter is electrically connected to an input terminal of the first buffer, the output end of the first buffer is electrically connected with the grid of the MOS transistor, the second logic gate module comprises a second NAND gate and a second buffer, the second NAND gate is provided with a first input end, a second input end and an output end, the first input end of the second NAND gate is electrically connected with the second end of the second resistance module, the second input end of the second NAND gate inputs an enable signal, the output end of the second NAND gate is electrically connected with the input end of the second buffer, the output terminal of the second buffer is electrically connected to the gate of the MOS transistor, and the enable signal EN is a pulse signal. The first buffer plays a role of buffering an output signal of the second inverter; the second buffer functions to buffer the output signal of the second nand gate.
In an embodiment of the present invention, when the second end of the first resistor module is connected to the second end of the second resistor module, the resistance of the second resistor module is greater than the resistance of the first resistor module, so that the maximum value of the voltage applied to the MOS transistor is smaller than the breakdown voltage of the MOS transistor, thereby protecting the MOS transistor.
In a specific embodiment of the present application, the first resistor module includes one or more first resistors, the second resistor module includes one or more second resistors, the first capacitor module includes one or more first capacitors, and the second capacitor module includes one or more second capacitors.
In one embodiment of the present application, the plurality of first resistors are connected in series or in parallel, the plurality of second resistors are connected in series or in parallel, the plurality of first capacitors are connected in series or in parallel, and the plurality of second capacitors are connected in series or in parallel.
An exemplary embodiment of the present application provides an electronic device, including an MOS transistor electrostatic protection circuit and a pulse signal generator, where the pulse signal generator is electrically connected to the MOS transistor electrostatic protection circuit, and the MOS transistor electrostatic protection circuit is any one of the MOS transistor electrostatic protection circuits. The electronic device adopts the MOS transistor electrostatic protection circuit to prolong the time of the preset charge quantity flowing through the MOS transistor, so that the charge quantity flowing through the MOS transistor in unit time is reduced, the maximum value of the voltage loaded on the MOS transistor is smaller than the breakdown voltage of the MOS transistor, even if the electrostatic voltage is larger, the MOS transistor can not be broken down, and the protection of the MOS transistor when the electrostatic voltage is larger is realized.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) the MOS transistor electrostatic protection circuit adopts the control unit to prolong the time of the preset charge quantity flowing through the MOS transistor, so that the charge quantity flowing through the MOS transistor in unit time is reduced, the maximum value of the voltage loaded on the MOS transistor is smaller than the breakdown voltage of the MOS transistor, even if the electrostatic voltage is larger, the MOS transistor cannot be broken down, and the MOS transistor is protected when the electrostatic voltage is larger.
2) The electronic device adopts the MOS transistor electrostatic protection circuit to prolong the time of the preset charge quantity flowing through the MOS transistor, so that the charge quantity flowing through the MOS transistor in unit time is reduced, the maximum value of the voltage loaded on the MOS transistor is smaller than the breakdown voltage of the MOS transistor, even if the electrostatic voltage is larger, the MOS transistor cannot be broken down, and the protection of the MOS transistor when the electrostatic voltage is larger is realized.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (5)

1. An electrostatic protection circuit for MOS transistor, comprising:
a MOS transistor;
a control unit connected to the MOS transistor by wire or wirelessly, for extending a time of a predetermined amount of charge flowing through the MOS transistor such that the amount of charge flowing through the MOS transistor per unit time is reduced such that a maximum value of a voltage applied to the MOS transistor is smaller than a breakdown voltage of the MOS transistor;
the control unit includes:
the first resistance-capacitance unit comprises a first resistance module and a first capacitance module, and the first resistance module is electrically connected with the first capacitance module;
the second resistance-capacitance unit comprises a second resistance module and a second capacitance module, and the second resistance module is electrically connected with the second capacitance module;
the logic gate unit is electrically connected with the first resistance-capacitance unit and the second resistance-capacitance unit respectively, and is used for controlling whether the first resistance-capacitance unit and the second resistance-capacitance unit are connected into the control unit or not;
the logic gate unit includes:
the first logic gate module is provided with an input end and an output end, the input end of the first logic gate module is electrically connected with the first resistor module, the output end of the first logic gate module is electrically connected with the MOS transistor, and the first logic gate module is used for reversing the phase of an output signal of the second end of the first resistor module by 180 degrees;
the second logic gate module is provided with an input end and an output end, the input end of the second logic gate module is electrically connected with the second resistor module, the output end of the second logic gate module is electrically connected with the grid electrode of the MOS transistor, and the second logic gate module is used for controlling whether the second resistor-capacitor unit is connected into the control unit or not;
the first logic gate module is a first inverter, the second logic gate module is a first nand gate, the first nand gate is provided with a first input end, a second input end and an output end, the first input end of the first nand gate is electrically connected with the second end of the second resistor module, the second input end of the first nand gate inputs an enable signal, the output end of the first nand gate is electrically connected with the grid of the MOS transistor, and the enable signal is a pulse signal;
the first logic gate module comprises a second inverter and a first buffer, the second inverter is connected with the first buffer in series, the second logic gate module comprises a second NAND gate and a second buffer, and the second NAND gate is connected with the second buffer in series.
2. The MOS transistor ESD protection circuit of claim 1, wherein the second resistor block has a resistance greater than the first resistor block when the second terminal of the first resistor block is connected to the second terminal of the second resistor block.
3. The electrostatic protection circuit of MOS transistor as claimed in claim 1, wherein said first resistor module comprises one or more first resistors, said second resistor module comprises one or more second resistors, said first capacitor module comprises one or more first capacitors, and said second capacitor module comprises one or more second capacitors.
4. The electrostatic protection circuit of MOS transistor as claimed in claim 2, wherein a plurality of said first resistors are connected in series or in parallel, a plurality of said second resistors are connected in series or in parallel, a plurality of said first capacitors are connected in series or in parallel, and a plurality of said second capacitors are connected in series or in parallel.
5. An electronic device, comprising a MOS transistor electrostatic protection circuit and a pulse signal generator, wherein the pulse signal generator is electrically connected to the MOS transistor electrostatic protection circuit, and the MOS transistor electrostatic protection circuit is the MOS transistor electrostatic protection circuit according to any one of claims 1 to 4.
CN202011111682.5A 2020-10-16 2020-10-16 MOS transistor electrostatic protection circuit and electronic device Active CN112289788B (en)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI237893B (en) * 2004-12-10 2005-08-11 Richtek Technology Corp Booster-type power management chip containing electrostatic discharge protection mechanism of output electrode
KR20060135225A (en) * 2005-06-24 2006-12-29 주식회사 하이닉스반도체 Esd protective power clamp circuit for semiconductor circuit
CN102222891A (en) * 2011-06-20 2011-10-19 北京大学 Power clamping ESD (electro-static discharge) protection circuit utilizing current mirror
JP2014207412A (en) * 2013-04-16 2014-10-30 株式会社東芝 ESD protection circuit
CN105633072A (en) * 2014-11-25 2016-06-01 精工爱普生株式会社 Electrostatic protection circuit and semiconductor integrated circuit apparatus
CN110967568A (en) * 2018-09-30 2020-04-07 奇景光电股份有限公司 Electrostatic discharge detection device
CN111697549A (en) * 2019-03-14 2020-09-22 中芯国际集成电路制造(上海)有限公司 ESD protection circuit and electronic device
CN213635988U (en) * 2020-10-16 2021-07-06 福建省晋华集成电路有限公司 MOS transistor electrostatic protection circuit and electronic device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI237893B (en) * 2004-12-10 2005-08-11 Richtek Technology Corp Booster-type power management chip containing electrostatic discharge protection mechanism of output electrode
KR20060135225A (en) * 2005-06-24 2006-12-29 주식회사 하이닉스반도체 Esd protective power clamp circuit for semiconductor circuit
CN102222891A (en) * 2011-06-20 2011-10-19 北京大学 Power clamping ESD (electro-static discharge) protection circuit utilizing current mirror
JP2014207412A (en) * 2013-04-16 2014-10-30 株式会社東芝 ESD protection circuit
CN105633072A (en) * 2014-11-25 2016-06-01 精工爱普生株式会社 Electrostatic protection circuit and semiconductor integrated circuit apparatus
CN110967568A (en) * 2018-09-30 2020-04-07 奇景光电股份有限公司 Electrostatic discharge detection device
CN111697549A (en) * 2019-03-14 2020-09-22 中芯国际集成电路制造(上海)有限公司 ESD protection circuit and electronic device
CN213635988U (en) * 2020-10-16 2021-07-06 福建省晋华集成电路有限公司 MOS transistor electrostatic protection circuit and electronic device

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