CN106451396B - A kind of power supply clamp ESD protection circuit structure - Google Patents
A kind of power supply clamp ESD protection circuit structure Download PDFInfo
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- CN106451396B CN106451396B CN201611076587.XA CN201611076587A CN106451396B CN 106451396 B CN106451396 B CN 106451396B CN 201611076587 A CN201611076587 A CN 201611076587A CN 106451396 B CN106451396 B CN 106451396B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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Abstract
A kind of power supply clamp ESD protection circuit structure comprising filter, odd number reverser and clamping transistor；Filter is connected between VDD power supplys and the ground GND, and a filtering voltage is generated on node for being filtered at one；Odd number reverser accepts filter voltage as an input, is exported as one for generating a control node；Wherein, first order reverser includes the first PMOS transistor, the first, second, and third NMOS transistor；First PMOS transistor, the first NMOS transistor and the second NMOS transistor common gate；The source electrode of first PMOS transistor and third NMOS transistor connects positive pole；The grid of third NMOS transistor, the drain electrode of the first PMOS transistor and the source electrode of the second NMOS transistor connect the output end as first order reverser altogether；The grounded drain of first NMOS transistor；The drain electrode of the source electrode, third NMOS transistor of first NMOS transistor is connected with the drain electrode of the second NMOS transistor；The grid of clamping transistor is connected with the output of odd number reverser.
Description
Technical field
The invention belongs to electronic circuit fields, are related to the power supply clamp ESD of control circuit more particularly to a kind of high reliability
Protect circuit.
Background technology
ESD protections in circuit are meant " Electro-static Driven Comb ".Integrated circuit device be operated in certain voltage, electric current and
Power consumption limits in range, and the electrostatic charge largely assembled is suitably in condition just will produce electrion, and static discharge passes through device
The high pressure instant transmission of lead, may be such that oxide layer disconnects, and cause the malfunction of device.
The generation of electrostatic includes mainly：Triboelectrification, electrification by induction and contact electrification.The principle of ESD protective device, ESD
Protection diode is a kind of novel integrated electrostatic protection device, inside be the equal of a Zener diode regulator,
, will be breakdown when input current is more than its rated voltage, excessive electric flux is led back to the earth, to play protection circuit
Effect.
Referring to Fig. 1, Fig. 1 is shown as the power supply and ground with active R-C (resistance capacitance) clamps of a prior art
Between esd protection circuit schematic diagram.As shown, capacitor 22 and resistor 20 form a R-C sensing element, three concatenations
Reverser (reverser 10, reverser 12, reverser 14) receive and induced electricity between changeover condenser 22 and resistor 20
Pressure, and the grid of n- raceway grooves clamping transistor 18 is driven to work.
Its operation principle is as follows：
Under normal operation, resistor 20 drives the input of reverser 10 supreme, generates a low voltage drive n- raceway groove
The grid of clamping transistor 18 so that it is turned off.When a voltage pulse is applied on Vdd, for example, a HBM esd pulse,
It is low that capacitor 22, which keeps the input of reverser 10, while maintaining a period of time, which is determined by R-C time constants.Reversely
The grid of the low input driving n- raceway grooves clamping transistor 18 of device 10 is supreme, will be electric to open n- raceway grooves clamping transistor 18
For stream from power source diverter to ground, shunting is applied to the esd pulse of power cord.
It is easily affected by noise although above-mentioned active esd protection circuit is very useful, especially during chip powers on.
If active esd protection circuit is triggered during powering on, it will lead to Vdd declines or even latch (latch-up), need
Illustrate, low supply voltage circuit may be more vulnerable to influence (as shown in Figure 5).
Referring to Fig. 2, Fig. 2 is standard【JEDEC_HBM_JESD22-A114-B】The EOS curve synoptic diagrams of page five.
In page five, the concept of EOS (ESD over stress) is described；The curve includes main esd pulse, the second esd pulse and ESD
The coda wave of test caused tight it will be apparent to those skilled in the art that the coda wave twice of ESD tests can excessively press to test circuit
Evaluation.
It is clamped with source R-C (resistance capacitance) referring to Fig. 3, Fig. 3 show Chinese invention patent (CN 101902039B)
Power supply and ground between esd protection circuit schematic diagram.
As shown in figure 3, the technical solution of the invention is identical with prior art in Fig. 1 is：It includes capacitor 46
Form a R-C sensing element with resistor 44, the reversers of three concatenations receive and changeover condenser 46 and resistor 44 it
Between induced voltage VF, and the grid of n- raceway grooves clamping transistor 40 is driven to work.
The technical solution of the invention is unlike prior art in Fig. 1：First in the reverser of three concatenations
Grade reverser is made of the PMOS transistor 30 and a NMOS transistor 32 of common gate, and the source electrode of PMOS transistor 30 connects
The anode of power supply, PMOS transistor 30 drain electrode with and NMOS transistor 32 source electrode be connected become first order reverser output
End；The drain electrode of NMOS transistor 32 is connected with the source electrode of NMOS transistor 50；The grounded drain of NMOS transistor 50；NMOS crystal
The grid of pipe 50 connects the output end of second level reverser, and further includes being attempted by first order inverter input and the second level is reversed
The feedback resistance 52 of device output end.
Second level reverser is made of the PMOS transistor 34 and a NMOS transistor 36 of common gate, PMOS crystal
The source electrode of pipe 34 connects the anode of power supply, drain with and the source electrode of NMOS transistor 36 be connected；The grounded drain of NMOS transistor 36.
Third level reverser is made of the PMOS transistor 38 and a NMOS transistor 42 of common gate, PMOS crystal
The source electrode of pipe 38 connects the anode of power supply, drain with and the source electrode of NMOS transistor 42 be connected；The grounded drain of NMOS transistor 42.
The grid work of the output end driving n- raceway grooves clamping transistor 40 of third level reverser.
That is, the opening time of n- raceway grooves clamping transistor 40 can be extended by the feedback of feedback resistance 52, from
And allow to use a smaller capacitor 44, and discharge time can fully be extended.
Specifically, when Vdd power supplys are powered or IC is just when normal condition is run, since voltage VF is drawn by filter resistor 44
Height, feedback resistance 52 draw high voltage V2 (output voltage of second level reverser).
However, in the embodiment of the invention, if the numerical value of feedback resistance 52 is too high, voltage V2 will not be pulled to foot
Enough height.If the numerical value of feedback resistance 52 is too low, ESD apply when clamping transistor 40 opening time will reduce, so, if
Window very little is counted, and is influenced by technological fluctuation.Therefore, 40 discharge time of clamping crystal can fully be extended by how designing one
High reliability clamp ESD protection circuit be current industry problem to be solved.
Invention content
In order to overcome problem above, the present invention is intended to provide it is a kind of, by increasing on 0~VDD in first order reverser
It rises threshold value and raises design partial circuit, reached the abundant high reliability clamp ESD protection for extending clamping transistor discharge time
Technical solution.
To achieve the above object, technical scheme is as follows：
The present invention provides a kind of power supply clamp ESD protection circuit structure comprising：
One VDD power supply；
One GND；
One filter, is connected between VDD power supplys and the ground GND, and a filter is generated on node for being filtered at one
Wave voltage；
N number of reverser receives the filtering voltage and is inputted as one, defeated as one for generating a control node
Go out, wherein N is strange positive integer；First order reverser in N number of reverser includes the first PMOS transistor, the first NMOS
Transistor, the second NMOS transistor and third NMOS transistor, first PMOS transistor, the first NMOS transistor and second
The source electrode of NMOS transistor common gate, first PMOS transistor and third NMOS transistor connects positive pole, the third
The source electrode of the grid of NMOS transistor, the drain electrode of the first PMOS transistor and the second NMOS transistor connects reversed as the first order altogether
The output end of device；The grounded drain of first NMOS transistor；Source electrode, the 3rd NMOS crystal of first NMOS transistor
The drain electrode of pipe is connected with the drain electrode of the second NMOS transistor；
One clamping transistor, for by electric current from VDD power supplys with being transmitted to GND；The grid of the clamping transistor with
The output of N number of reverser is connected.
Preferably, the filter is to be serially connected in VDD power supplys to be made of a resistance and a capacitance between the ground GND
RC filters, wherein the resistance be connected to VDD power supply nodes and filtering node between, the capacitance connection is in trap
Between point and the ground GND.
Preferably, the N be 3, the filter be serially connected in VDD power supplys between the ground GND by a resistance and one
The RC filters of a capacitance composition, wherein the resistance is connected between VDD power supply nodes and filtering node, and the capacitance connects
It is connected between filtering node and the ground GND；Wherein, the first order reverser accepts filter node as an input, and drives
First node is exported as one；Second level reverser receives first node and is inputted as one, and drives second node conduct
One output；Third level reverser receives second node and is inputted as one, and the clamping transistor gate node is driven to make
For output.
Preferably, the RC filter time constants are that capacitance is multiplied by resistance value；Wherein, the clamping transistor is protected
The time for holding conducting is at least 10 times longer than RC time constant.
Preferably, the second level reverser includes the second PMOS transistor and the 4th NMOS transistor, and the 2nd PMOS is brilliant
The source electrode of body pipe and the 4th NMOS transistor common gate, the second PMOS transistor connects positive pole, second PMOS transistor
Drain electrode connect the output end as second level reverser altogether with the source electrode of the 4th NMOS transistor, the 4th NMOS transistor
Grounded drain.
Preferably, the third level reverser includes third PMOS transistor and the 5th NMOS transistor, and the 3rd PMOS is brilliant
The source electrode of body pipe and the 5th NMOS transistor common gate, third PMOS transistor connects positive pole, the third PMOS transistor
Drain electrode connect the output end as third level reverser altogether with the source electrode of the 5th NMOS transistor, the 5th NMOS transistor
Grounded drain.
It can be seen from the above technical proposal that power supply clamp ESD protection circuit structure provided by the invention, has following excellent
Point：
(1) fully extend the high reliability clamp ESD protection circuit of clamping crystal discharge time：
Compared with the circuit in Fig. 3, the design of feedback resistance is eliminated, the numerical values recited of feedback resistance no longer influences voltage
The opening time of clamping transistor, makes design window become larger, and do not influenced by technological fluctuation when V2 values and ESD apply.
(2) simple in structure：
Compared with the circuit in Fig. 1, two NMOS transistors are increased only in circuit of the present invention.Due to the substrate of transistor
Bias voltage acts on, and the transformation threshold voltage of 0~VDD of first order reverser is lifted by the operation principle of foregoing circuit
Height also means that the time that ESD clamping transistors are opened has obtained maximum extension.
Description of the drawings
ESD is protected between Fig. 1 is shown as the power supply and ground with Active RC (resistance capacitance) clamp of a prior art
Circuit diagram
Fig. 2 is standard【JEDEC_HBM_JESD22-A114-B】The EOS curve synoptic diagrams of page 5
Fig. 3, which show Chinese invention patent (CN 101902039B), has the power supply and ground of source R-C (resistance capacitance) clamps
Between esd protection circuit schematic diagram
Fig. 4 is power supply clamp ESD protection circuit structural schematic diagram in the embodiment of the present invention
Fig. 5 is power supply esd protection circuit course of work curve and universal power supply shown in FIG. 1 in the embodiment of the present invention
Esd protection circuit course of work curve synoptic diagram
Specific implementation mode
Embodying the embodiment of feature of present invention and advantage will in detail describe in the explanation of back segment.It should be understood that the present invention
Can have various variations in different examples, neither depart from the scope of the present invention, and it is therein explanation and be shown in
Substantially regard purposes of discussion, rather than to limit the present invention.
Below in conjunction with attached drawing, by specific embodiment to a kind of power supply clamp ESD protection circuit structure of the present invention make into
One step is described in detail.It should be noted that the present invention is also a kind of power supply and ground with active R-C (resistance capacitance) clamps
Between esd protection circuit.
Referring to Fig. 4, Fig. 4 is power supply clamp ESD protection circuit structural schematic diagram in the embodiment of the present invention.As shown,
The power supply clamp ESD protection circuit structure comprising a VDD power supply, GND, a filter, N number of reverser and
One clamping transistor.
In an embodiment of the present invention, filter is connected between VDD power supplys and the ground GND, for filtering node at one
One filtering voltage of upper generation.In general, filter may include a resistance and a capacitance, filter can be to be serially connected in
VDD power supplys are to the RC filters being made of a resistance and a capacitance between the ground GND；Wherein, resistance is connected to VDD power supply sections
Between point and filtering node, capacitance connection is between filtering node and the ground GND.
When ESD occurs, resistance and capacitance are connected between power supply and ground, and a filtering is generated on its crosspoint
Voltage VF, VF are low level, by being high level VG after follow-up N grades of reverser.High level VG is the grid of clamping transistor N6
Voltage, when high level VG is high, clamping transistor N6 is opened, and ESD electric currents are diverted to ground GND from power vd D.
N number of reverser receives the filtering voltage and is inputted as one, defeated as one for generating a control node
Go out, wherein N is strange positive integer.Preferably, N is 3.
In following embodiments of the present invention, illustrated so that N is equal to 3 as an example.As shown in figure 5, capacitance C and resistance R
A RC sensing element is formed, the reverser of three concatenations receives and the induced voltage between changeover condenser C and resistor R,
And the grid of n- raceway groove clamping transistors N6 is driven to work.
Wherein, resistance R is connected between VDD power supply nodes and filtering node, and capacitance C is with being connected to filtering node and GND
Between；First order reverser accepts filter node as an input, and first node is driven to be exported as one；The second level is anti-
First node is received to device to input as one, and second node is driven to be exported as one；Third level reverser receives second
Node is inputted as one, and drives clamping transistor gate node as output.
In an embodiment of the present invention, the first order reverser in three-level reverser may include the first PMOS transistor
P1, the first NMOS transistor N1, the second NMOS transistor N2 and third NMOS transistor N3.Wherein, the first PMOS transistor P1,
First NMOS transistor N1 and the second NMOS transistor N2 common gates, the source of the first PMOS transistor P1 and third NMOS transistor
Pole connects positive pole, and the drain electrode of the grid of third NMOS transistor, the second PMOS transistor P2 is with the first NMOS transistor N1's
Source electrode connects the output end as first order reverser altogether；The grounded drain of first NMOS transistor N1；First NMOS transistor N1
The drain electrode of source electrode, third NMOS transistor N3 be connected with the drain electrode of the second NMOS transistor N2.
In an embodiment of the present invention, second level reverser may include the second PMOS transistor P2 and the 4th NMOS crystal
Pipe, the second PMOS transistor P2 and the 4th NMOS transistor N4 common gates, the source electrode of the second PMOS transistor P2 connect positive pole,
The drain electrode of second PMOS transistor P2 and the source electrode of the 4th NMOS transistor connect the output end as second level reverser altogether, described
The grounded drain of 4th NMOS transistor.
Also, third level reverser may include third PMOS transistor N3 and the 5th NMOS transistor N5, the 3rd PMOS
The source electrode of transistor and the 5th NMOS transistor N5 common gates, third PMOS transistor connects positive pole, third PMOS transistor
The drain electrode of N3 and the source electrode of the 5th NMOS transistor N5 connect the output end as third level reverser, the 5th NMOS crystal altogether
The grounded drain of pipe.
It is clear that compared with the prior art circuits in Fig. 1, the first order reverser in above structure of the present invention increases by 0
~VDD ascending thresholds raise design partial circuit.Second level reverser and third level reverser can use in the prior art
What reverser, details are not described herein.
Clamping transistor N6 be used for by electric current from VDD power supplys with being transmitted to GND；The grid of clamping transistor N6 and three
Total output of reverser is connected.
It is as follows for power supply clamp ESD protection circuit operation principle in the embodiment of the present invention：
After esd event starts, ESD clamp protection circuits are in open state, can continue for some time, when this continues
Between be approximately equal to RC time constants, which is mainly determined by the capacitance of the resistance value of filter resistance R and capacitance C, by
It is that capacitance is multiplied by resistance value in RC filter time constants.If using the scheme of the prior art in Fig. 1, held to this
After the continuous time, which is closed.
Referring to Fig. 5, Fig. 5 is power supply esd protection circuit course of work curve and shown in FIG. 1 logical in the embodiment of the present invention
With type power supply esd protection circuit course of work curve synoptic diagram.In the embodiment of invention, when VF is low level, the ESD pincers
When being in open state of position protection circuit, the first NMOS transistor N1 and the second NMOS transistor N2N2 of first order reverser
It is closed, third NMOS transistor N3 is opened；The drain terminal voltage of third NMOS transistor N3 is VDD-VTH_N3；Its
In, VTH_N3 is the threshold voltage of third NMOS transistor N3.
The duration is equal to after RC time constants, and filter resistance charges to filter capacitor, to filtering voltage
VF starts to increase.With the raising of VF voltages, the first NMOS transistor N1 is begun to turn on, the drain terminal electricity of third NMOS transistor N3
Pressure is begun to decline, and subsequent second NMOS transistor N2 is gradually turned on, and third NMOS transistor N3 is closed.
It should be readily apparent to one skilled in the art that the Substrate bias voltage due to transistor acts on, first order reverser 0~
Transformation operation principle of the threshold voltage by foregoing circuit of VDD, is raised, also means that ESD clamping transistors are opened
The time opened has obtained maximum extension.
As shown in figure 5, in an embodiment of the present invention, when the time that clamping transistor N6 is held at least can be than RC
Between constant grow 10 times.
Above is only the embodiment of the present invention, to limit the scope of patent protection of the present invention, therefore embodiment is not
Equivalent structure variation, similarly should be included in the protection of the present invention made by every specification and accompanying drawing content with the present invention
In range.
Claims (6)
1. a kind of power supply clamp ESD protection circuit structure, which is characterized in that including：
One VDD power supply；
One GND；
One filter, is connected between VDD power supplys and the ground GND, and a filtered electrical is generated on node for being filtered at one
Pressure；
N number of reverser receives the filtering voltage and is inputted as one, is exported as one for generating a control node,
Wherein, N is strange positive integer；First order reverser in N number of reverser includes the first PMOS transistor, the first NMOS crystal
Pipe, the second NMOS transistor and third NMOS transistor, first PMOS transistor, the first NMOS transistor and the 2nd NMOS
The source electrode of transistor common gate, first PMOS transistor and third NMOS transistor meets positive pole, the 3rd NMOS
The grid of transistor, the drain electrode of the first PMOS transistor and the source electrode of the second NMOS transistor are connect altogether as first order reverser
Output end；The grounded drain of first NMOS transistor；The source electrode of first NMOS transistor, third NMOS transistor
Drain electrode is connected with the drain electrode of the second NMOS transistor；
One clamping transistor, for by electric current from VDD power supplys with being transmitted to GND；The grid of the clamping transistor and the N
The output of a reverser is connected.
2. power supply clamp ESD protection circuit structure according to claim 1, which is characterized in that the filter is string
VDD power supplys are connected on to the RC filters being made of a resistance and a capacitance between the ground GND, wherein the resistance is connected to
Between VDD power supply nodes and filtering node, the capacitance connection is between filtering node and the ground GND.
3. power supply clamp ESD protection circuit structure according to claim 2, which is characterized in that the N is 3, the filter
Wave device is to be serially connected in VDD power supplys to the RC filters being made of a resistance and a capacitance between the ground GND, wherein the electricity
Resistance is connected between VDD power supply nodes and filtering node, and the capacitance connection is between filtering node and the ground GND；Wherein, described
First order reverser accepts filter node as an input, and first node is driven to be exported as one；Second level reverser,
It receives first node to input as one, and second node is driven to be exported as one；Third level reverser receives second node
It is inputted as one, and drives the clamping transistor gate node as output.
4. power supply clamp ESD protection circuit structure according to claim 2 or 3, which is characterized in that the RC filters
Time constant is that capacitance is multiplied by resistance value；Wherein, the time that the clamping transistor is held on is at least than RC time constant
It is 10 times long.
5. power supply clamp ESD protection circuit structure according to claim 3, which is characterized in that the second level reverser
Including the second PMOS transistor and the 4th NMOS transistor, the second PMOS transistor and the 4th NMOS transistor common gate, second
The source electrode of PMOS transistor connects positive pole, and the drain electrode of second PMOS transistor and the source electrode of the 4th NMOS transistor connect altogether
As the output end of second level reverser, the grounded drain of the 4th NMOS transistor.
6. power supply clamp ESD protection circuit structure according to claim 3, which is characterized in that the third level reverser
Including third PMOS transistor and the 5th NMOS transistor, third PMOS transistor and the 5th NMOS transistor common gate, third
The source electrode of PMOS transistor connects positive pole, and the drain electrode of the third PMOS transistor and the source electrode of the 5th NMOS transistor connect altogether
As the output end of third level reverser, the grounded drain of the 5th NMOS transistor.
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| CN201611076587.XA CN106451396B (en) | 2016-11-30 | 2016-11-30 | A kind of power supply clamp ESD protection circuit structure |
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| CN201611076587.XA CN106451396B (en) | 2016-11-30 | 2016-11-30 | A kind of power supply clamp ESD protection circuit structure |
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| CN106451396B true CN106451396B (en) | 2018-10-16 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US11088540B2 (en) * | 2018-10-30 | 2021-08-10 | Semiconductor Components Industries, Llc | Switch circuit with high voltage protection that reduces leakage currents |
| CN109450432B (en) * | 2018-12-18 | 2024-04-02 | 珠海泰芯半导体有限公司 | Radio frequency input port protection circuit |
| CN111193249B (en) * | 2020-01-06 | 2022-02-22 | 西安理工大学 | Clamping circuit capable of being used for electrostatic discharge and surge protection simultaneously |
| CN112103932A (en) * | 2020-09-07 | 2020-12-18 | 海光信息技术股份有限公司 | Electrostatic clamping circuit and chip structure |
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|---|---|---|---|---|
| CN101060754A (en) * | 2006-04-20 | 2007-10-24 | 矽统科技股份有限公司 | A static discharge protective circuit with the feedback technology |
| CN101902039A (en) * | 2010-06-08 | 2010-12-01 | 香港应用科技研究院有限公司 | One is used for the chip power supply clamp ESD protection circuit based on NMOS feedback |
| CN102222891A (en) * | 2011-06-20 | 2011-10-19 | 北京大学 | Power clamping ESD (electro-static discharge) protection circuit utilizing current mirror |
| CN102723702A (en) * | 2012-06-20 | 2012-10-10 | 上海华力微电子有限公司 | Dual-feedback power supply clamp used for on-chip electrostatic discharge protection |
| CN103219718A (en) * | 2012-01-18 | 2013-07-24 | 三星电子株式会社 | Electrostatic discharge protection circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6965503B2 (en) * | 2003-09-30 | 2005-11-15 | International Business Machines Corporation | Electro-static discharge protection circuit |
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- 2016-11-30 CN CN201611076587.XA patent/CN106451396B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101060754A (en) * | 2006-04-20 | 2007-10-24 | 矽统科技股份有限公司 | A static discharge protective circuit with the feedback technology |
| CN101902039A (en) * | 2010-06-08 | 2010-12-01 | 香港应用科技研究院有限公司 | One is used for the chip power supply clamp ESD protection circuit based on NMOS feedback |
| CN102222891A (en) * | 2011-06-20 | 2011-10-19 | 北京大学 | Power clamping ESD (electro-static discharge) protection circuit utilizing current mirror |
| CN103219718A (en) * | 2012-01-18 | 2013-07-24 | 三星电子株式会社 | Electrostatic discharge protection circuit |
| CN102723702A (en) * | 2012-06-20 | 2012-10-10 | 上海华力微电子有限公司 | Dual-feedback power supply clamp used for on-chip electrostatic discharge protection |
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