CN106098683A - A kind of esd protection circuit - Google Patents

A kind of esd protection circuit Download PDF

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Publication number
CN106098683A
CN106098683A CN201610529742.2A CN201610529742A CN106098683A CN 106098683 A CN106098683 A CN 106098683A CN 201610529742 A CN201610529742 A CN 201610529742A CN 106098683 A CN106098683 A CN 106098683A
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CN
China
Prior art keywords
circuit
scale
esd
pmos
esd protection
Prior art date
Application number
CN201610529742.2A
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Chinese (zh)
Inventor
陆让天
Original Assignee
芯海科技(深圳)股份有限公司
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Publication date
Application filed by 芯海科技(深圳)股份有限公司 filed Critical 芯海科技(深圳)股份有限公司
Priority to CN201610529742.2A priority Critical patent/CN106098683A/en
Publication of CN106098683A publication Critical patent/CN106098683A/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection

Abstract

The invention discloses a kind of esd protection circuit, this circuit includes PMOS and NMOS tube, and described PMOS is large scale PMOS, and described NMOS tube is large scale NMOS tube;Described circuit also includes testing circuit, and described testing circuit is connected to described large scale PMOS and large scale NMOS tube.Esd protection circuit avoids device breakdown by large scale NMOS or large scale PMOS; electrostatic can be discharged timely and effectively; greatly strengthen the ESD performance of circuit, can also be for there is the application scenario of relatively positive nagative potential in this circuit between node, it is provided that ESD protects.

Description

A kind of esd protection circuit

Technical field

The invention belongs to technical field of integrated circuits, particularly to the esd protection circuit of a kind of integrated circuit.

Background technology

Electrostatic discharge (ESD) protection (ESD protection) is to be specifically used on integrated circuit do electrostatic discharge protective, this electrostatic Discharge prevention provides ESD current drain loop, in order to avoid esd discharge, ESD electric current flows into IC portion circuit and causes damage.

In some application scenario, relatively positive nagative potential occurs between the power supply ground of integrated circuit or between I/O port, or Between the power supply in many power supply chips, relatively positive nagative potential occurs between ground wire, generally use the esd protection structure of Fig. 1.This structure Relating to device breakdown discharge process, trigger voltage is the highest, and ESD protective capability is relatively low, needs to expend large area.

As patent application 201110108194.3 discloses a kind of power supply clamp ESD protection circuit, including: power pin; Ground pin;R-C circuit, is used for sensing ESD voltage, including the impedor being connected between power pin and primary nodal point and The capacitive reactive element being connected between primary nodal point and secondary nodal point, wherein, secondary nodal point is not directly connected to ground pin;Touch Power Generation Road, it is connected between power pin, ground pin and R-C circuit, for according to primary nodal point and the electricity of secondary nodal point The raw ESD that shows no increases in output triggers signal;Biasing circuit, it is connected between power pin and ground pin, is used for as secondary nodal point One bias voltage is provided;And, clamp circuit, it is connected between power pin, ground pin and triggering circuit, is used for Receive after ESD triggers signal and provide a low impedance path between power supply and ground, with static electricity discharge electric current.This circuit can have The leakage current of effect suppression electrostatic discharge protective circuit, effectively protection internal circuit is not by electrostatic damage.It is complicated that this circuit constitutes structure, Components and parts are many, and cost is high, are also required to consume large area simultaneously.Prior, this circuit cannot be applied between node to be occurred relatively The occasion of positive nagative potential.

Summary of the invention

Based on this, therefore the present invention provides a kind of esd protection circuit, and this circuit protection is protected the circuit from by outside quiet The electrostatic damage that electricity causes, solves the ESD protection problem occurring relatively positive nagative potential application scenario between node, and solves ESD The problem that trigger voltage is high, has little circuit area simultaneously.

Another mesh ground of the present invention is to provide a kind of esd protection circuit, and this circuit constitutes simple, it is easy to accomplish, become This is cheap.

For achieving the above object, the technical scheme is that

A kind of esd protection circuit, this circuit includes PMOS and NMOS tube, it is characterised in that described PMOS is big chi Very little PMOS, described NMOS tube is large scale NMOS tube;Described circuit also includes testing circuit, and described testing circuit is connected to Described large scale PMOS and large scale NMOS tube.Esd protection circuit is avoided by large scale NMOS or large scale PMOS Device breakdown, it is possible to discharged timely and effectively by electrostatic, greatly strengthen the ESD performance of circuit.

Described testing circuit is made up of together with resistant series electric capacity.

Described electric capacity includes C1 and C2, and described resistance includes R1 and R2.Resistance R1 and R2 can be multiple equivalence shape Formula, such as polycrystalline resistor, diffusion resistance, pinch off resistance, transistor equivalent resistance etc..Electric capacity C1 and C2 can also be multiple equivalence Form, such as well electric capacity, mos capacitance, polycrystalline electric capacity, metal capacitance etc..Wherein R1 and C1 be cascaded composition an ESD Testing circuit, and R2 and C2 be cascaded the second esd detection circuit of composition, both RC time constant designs 0.01~ 1.0us, in order to distinguish esd event and normally to power on.

Further, resistance R1 electric capacity C1 forms the first esd detection circuit;R1 one end is connected with the drain electrode of large scale MP1, another End is connected with C1, is connected with MP1 grid simultaneously;C1 one end is connected with current potential VA, and the other end is connected with R1;MP1 grid is connected to The connection node of R1 and C1, MP1 source electrode is connected with VA, and MP1 drain electrode is connected with R1 one end, is connected with the drain electrode of large scale MN1 simultaneously, MP1 body end is connected with self drain electrode.

Resistance R2 and electric capacity C2 forms the second esd detection circuit;R2 one end is connected with VB, and the other end is connected with C2;C2 mono- End is connected with VA, and the other end is connected with R2;Large scale MN1 grid be connected to the connection node of R2 and C2, MN1 source electrode and body end with VB connects, and MN1 drain electrode is connected with MP1 drain electrode.

The esd protection circuit that the present invention is realized, its large scale NMOS or large scale PMOS, in esd event, for leading Logical state, it is to avoid device breakdown, trigger voltage is the lowest, is discharged timely and effectively by electrostatic, greatly strengthen the ESD of circuit Energy;Compared with conventional method, will reach equal ESD level, required NMOS and PMOS area greatly reduces.

Can also be for there is the application scenario of relatively positive nagative potential in this circuit between node, it is provided that ESD protects.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of the esd protection circuit that prior art is implemented.

Fig. 2 is the circuit diagram of the esd protection circuit that the present invention is implemented.

Detailed description of the invention

In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, right The present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, and It is not used in the restriction present invention.

As in figure 2 it is shown, the esd protection circuit that the present invention is realized includes: resistance R, electric capacity C, large scale NMOS, big chi Very little PMOS.Resistance R and electric capacity C constitutes testing circuit, it is possible to detection esd event.Large scale NMOS or large scale PMOS, In esd event, for conducting state, it is to avoid device breakdown, trigger voltage is the lowest, is discharged timely and effectively by electrostatic, increases greatly The strong ESD performance of circuit;Compared with conventional method, will reach equal ESD level, required NMOS and PMOS area is greatly Reduce.

Resistance R1 and R2, can be multiple equivalents, such as polycrystalline resistor, diffusion resistance, pinch off resistance, transistor etc. Effect resistance etc..Electric capacity C1 and C2, it is also possible to for multiple equivalents, such as well electric capacity, mos capacitance, polycrystalline electric capacity, metal capacitance Deng.First esd detection circuit of R1 and C1 composition, and the second esd detection circuit of R2 and C2 composition, both RC time constants Design is 0.01~1.0us, in order to distinguish esd event and normally to power on.

Resistance R1 electric capacity C1 forms the first esd detection circuit;R1 one end is connected with the drain electrode of large scale MP1, the other end and C1 Connect, be connected with MP1 grid simultaneously;C1 one end is connected with current potential VA, and the other end is connected with R1.MP1 grid is connected to R1 and C1 Connection node, MP1 source electrode is connected with VA, MP1 drain electrode is connected with R1 one end, while with large scale MN1 drain be connected, MP1 body Hold and be connected with self drain electrode.

Resistance R2 and electric capacity C2 forms the second esd detection circuit;R2 one end is connected with VB, and the other end is connected with C2;C2 mono- End is connected with VA, and the other end is connected with R2.Large scale MN1 grid be connected to the connection node of R2 and C2, MN1 source electrode and body end with VB connects, and MN1 drain electrode is connected with MP1 drain electrode.

When VA occurs VB positive polarity ESD, due to RC circuit transient state effect so that the grid of large scale MN1 obtains height Voltage, MN1 is in the conduction state during esd event, and the electrostatic on VA is by the parasitic diode of MP1, again by conducting MN1 is discharged into VB timely and effectively.

When VA occurs VB negative polarity ESD, due to RC circuit transient state effect so that the grid of large scale MP1 obtains low Voltage, MP1 is in the conduction state during esd event, and the electrostatic on VA is by the MP1 of conducting, again by parasitism two pole of MN1 Pipe is discharged into VB timely and effectively.

In sum, large scale MN1 and large scale MP1, in esd event, for conducting state, it is to avoid device breakdown, Trigger voltage is the lowest, is discharged timely and effectively by electrostatic, greatly strengthen the ESD performance of circuit;Compared with conventional method, reach To equal ESD level, required NMOS and PMOS area greatly reduces.

The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all essences in the present invention Any amendment, equivalent and the improvement etc. made within god and principle, should be included within the scope of the present invention.

Claims (6)

1. an esd protection circuit, this circuit includes PMOS and NMOS tube, it is characterised in that described PMOS is large scale PMOS, described NMOS tube is large scale NMOS tube;Described circuit also includes testing circuit, and described testing circuit is connected to institute State large scale PMOS and large scale NMOS tube.
2. esd protection circuit as claimed in claim 1, it is characterised in that described testing circuit by electric capacity and resistant series one Rise and constitute.
3. esd protection circuit as claimed in claim 2, it is characterised in that described electric capacity includes C1 and C2, described resistance bag Include R1 and R2.
4. esd protection circuit as claimed in claim 3, it is characterised in that wherein R1 and C1 is cascaded the first of composition Esd detection circuit, and R2 and C2 be cascaded composition the second esd detection circuit, both RC time constant design exist 0.01~1.0us, in order to distinguish esd event and normally to power on.
5. esd protection circuit as claimed in claim 4, it is characterised in that resistance R1 electric capacity C1 forms the first esd detection circuit; R1 one end is connected with the drain electrode of large scale MP1, and the other end is connected with C1, is connected with MP1 grid simultaneously;C1 one end is with current potential VA even Connecing, the other end is connected with R1;MP1 grid is connected to the connection node of R1 and C1, and MP1 source electrode is connected with VA, MP1 drain electrode and R1 mono- End connects, is connected with the drain electrode of large scale MN1 simultaneously, and MP1 body end is connected with self drain electrode.
6. esd protection circuit as claimed in claim 4, it is characterised in that resistance R2 and electric capacity C2 composition the 2nd ESD detection electricity Road;R2 one end is connected with VB, and the other end is connected with C2;C2 one end is connected with VA, and the other end is connected with R2;Large scale MN1 grid Being connected to the connection node of R2 and C2, MN1 source electrode and body end be connected with VB, MN1 drain electrode is connected with MP1 drain electrode.
CN201610529742.2A 2016-07-06 2016-07-06 A kind of esd protection circuit CN106098683A (en)

Priority Applications (1)

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CN201610529742.2A CN106098683A (en) 2016-07-06 2016-07-06 A kind of esd protection circuit

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CN201610529742.2A CN106098683A (en) 2016-07-06 2016-07-06 A kind of esd protection circuit

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106992511A (en) * 2017-05-30 2017-07-28 长沙方星腾电子科技有限公司 A kind of ESD protection circuit
CN108878416A (en) * 2018-06-28 2018-11-23 武汉新芯集成电路制造有限公司 ESD protection circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05102475A (en) * 1991-10-09 1993-04-23 Ricoh Co Ltd Semiconductor device and manufacture thereof
US20050237681A1 (en) * 2004-04-21 2005-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage ESD protection circuit with low voltage transistors
CN102593122A (en) * 2011-01-10 2012-07-18 英飞凌科技股份有限公司 Semiconductor ESD circuit and method
CN105049027A (en) * 2015-06-18 2015-11-11 深圳市芯海科技有限公司 IO circuit used for enhancing ESD performance

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05102475A (en) * 1991-10-09 1993-04-23 Ricoh Co Ltd Semiconductor device and manufacture thereof
US20050237681A1 (en) * 2004-04-21 2005-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage ESD protection circuit with low voltage transistors
CN102593122A (en) * 2011-01-10 2012-07-18 英飞凌科技股份有限公司 Semiconductor ESD circuit and method
CN105049027A (en) * 2015-06-18 2015-11-11 深圳市芯海科技有限公司 IO circuit used for enhancing ESD performance

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106992511A (en) * 2017-05-30 2017-07-28 长沙方星腾电子科技有限公司 A kind of ESD protection circuit
CN108878416A (en) * 2018-06-28 2018-11-23 武汉新芯集成电路制造有限公司 ESD protection circuit

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Application publication date: 20161109