CN109684762A - The setting circuit of chip and its pin - Google Patents
The setting circuit of chip and its pin Download PDFInfo
- Publication number
- CN109684762A CN109684762A CN201811652719.8A CN201811652719A CN109684762A CN 109684762 A CN109684762 A CN 109684762A CN 201811652719 A CN201811652719 A CN 201811652719A CN 109684762 A CN109684762 A CN 109684762A
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- Prior art keywords
- chip
- phase inverter
- pin
- output end
- electrically connected
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
Abstract
The invention discloses a kind of chip and its setting circuits of pin, and it includes switching tube, the first NAND gate module, the first phase inverter, the second phase inverter and circuit output end that circuit, which is arranged,；The drain electrode of switching tube is electrically connected with the input terminal of the input pin of chip, the first phase inverter respectively, and the grid of switching tube is electrically connected with the output end of the first NAND gate module, the source electrode ground connection of switching tube；The output end of first phase inverter is electrically connected with the input terminal of the second phase inverter；The first input end of first NAND gate module is electrically connected with the electrification reset end of chip, and the second input terminal of the first NAND gate module is electrically connected with the output end of the second phase inverter, circuit output end respectively.The present invention realizes the function of needing huge chip area to be just able to achieve in the past with small number of analog device and lesser chip area, chip area has been saved in the case where guaranteeing that the default value of chip pin sets 0 function, it is high and at low cost to have many advantages, such as integrated level, and quiescent dissipation is substantially zeroed.
Description
Technical field
The present invention relates to technical field of circuit design, in particular to the setting circuit of a kind of chip and its pin.
Background technique
With the development of integrated circuit technique, electrically erasable programmable read-only memory (Electrically Erase
Programmable ROM, EEPROM) it has been obtained for being widely applied.It is adopted as between the eeprom chip and host of slave
Data are exchanged with a kind of I2C (Inter-Integrated Circuit, bidirectional two-line synchronous serial bus) agreement.Due to
I2C agreement allows the multiple slaves of carry in bus, it requires that each slave has required oneself independent slave identification ground
Location is for host identification.Usual eeprom chip possesses 3 identification addresses, so that in bus at most can and meanwhile carry 8
Chips, and this 3 identification address pins need to be arranged default value (i.e. the default value of chip pin) to guarantee that pin is not having
Identification address is 000 when receiving external signal, i.e., so that the quiescent dissipation of chip pin is 0, to realize the mesh for reducing power consumption
's.
Currently, as shown in Figure 1, by using a large amount of resistance (R1-Rn) to connect at chip input pin (PIN_IN)
The mode of ground connection makes the identification address of chip pin be 000；As shown in Fig. 2, by chip input pin (PIN_IN)
Use the mode of a large amount of MOS (Metal-oxide-semicondutor) pipe (M1-Mn) series connection ground connection with making the identification of chip pin
Location is 000.In order to achieve the purpose that chip pin is almost 0 quiescent dissipation, above two mode is required using many devices
Part greatly reduces the integrated level and higher cost of chip so that a large amount of chip area can be occupied.
Summary of the invention
The technical problem to be solved by the present invention is to the setting circuits of chip pin in the prior art by using a large amount of electricity
The mode of resistance or metal-oxide-semiconductor series connection ground connection makes the default value of chip pin be 0, and higher cost low there are integrated level etc. lacks
Fall into the setting circuit, and it is an object of the present invention to provide a kind of chip and its pin.
The present invention is to solve above-mentioned technical problem by following technical proposals:
The present invention provides a kind of setting circuit of chip pin, and the setting circuit includes switching tube, the first NAND gate mould
Block, the first phase inverter, the second phase inverter and circuit output end；
The drain electrode of the switching tube is electrically connected with the input terminal of the input pin of chip, first phase inverter respectively, institute
The grid for stating switching tube is electrically connected with the output end of the first NAND gate module, the source electrode ground connection of the switching tube；
The output end of first phase inverter is electrically connected with the input terminal of second phase inverter；
The first input end of the first NAND gate module is electrically connected with the electrification reset end of chip, first NAND gate
Second input terminal of module is electrically connected with the output end of second phase inverter, the circuit output end respectively.
Preferably, the setting circuit further includes the second NAND gate module, third phase inverter and the 4th phase inverter；
The input terminal of the third phase inverter is electrically connected with the pulse signal end of chip, the output end of the third phase inverter
It is electrically connected with the third input terminal of the second NAND gate module；
4th input terminal of the second NAND gate module is electrically connected with the electrification reset end of chip, second NAND gate
The output end of module is electrically connected with the input terminal of the 4th phase inverter；
The output end of 4th phase inverter is electrically connected with the first input end of the first NAND gate module.
Preferably, the circuit output end exports high level when the input of the input pin of chip is high level；
When the input pin of chip is in the input pin input low level of vacant state or chip, the circuit is defeated
Outlet exports low level.
Preferably, the switching tube is metal-oxide-semiconductor.
Preferably, the switching tube is NMOS (N-type Metal-oxide-semicondutor) pipe.
The present invention also provides a kind of chip, the chip includes the setting circuit of above-mentioned chip pin.
The positive effect of the present invention is that:
In the present invention, instead of traditional circuit design being grounded with a large amount of resistance or metal-oxide-semiconductor series connection, by fewer
The analog device matching timing control of amount and lesser chip area realize the function for needing huge chip area to be just able to achieve in the past
Can, guarantee chip pin default value set 0 function in the case where saved chip area, realize more high integration and
More inexpensive purpose；In power consumption, so that instantaneous power consumption is substantially zeroed in whole work process, to reach static function
The purpose that consumption is 0, significantly reduces power consumption.
Detailed description of the invention
Fig. 1 is the first structure diagram of the setting circuit of existing chip pin.
Fig. 2 is the second structural schematic diagram of the setting circuit of existing chip pin.
Fig. 3 is the structural schematic diagram of the setting circuit of the chip pin of the embodiment of the present invention 1.
Fig. 4 is the structural schematic diagram of the setting circuit of the chip pin of the embodiment of the present invention 2.
Fig. 5 is the clock signal schematic diagram in the setting circuit of the chip pin of the embodiment of the present invention 2.
Specific embodiment
The present invention is further illustrated below by the mode of embodiment, but does not therefore limit the present invention to the reality
It applies among a range.
Embodiment 1
As shown in figure 3, the setting circuit of the chip pin of the present embodiment includes switching tube M, the first NAND gate module I 1,
One phase inverter I2, the second phase inverter I3 and circuit output end OUT.Wherein, switching tube M is metal-oxide-semiconductor.
The drain electrode of switching tube M is electrically connected with the input terminal of the input pin PIN_IN of chip, the first phase inverter I2 respectively, is opened
The grid for closing pipe M is electrically connected with the output end of the first NAND gate module I 1, the source electrode ground connection of switching tube M；
The output end of first phase inverter I2 is electrically connected with the input terminal of the second phase inverter I3；
The first input end of first NAND gate module I 1 is electrically connected with the electrification reset end POR of chip, the first NAND gate mould
The second input terminal of block I1 is electrically connected with the output end of the second phase inverter I3, circuit output end OUT respectively.
The circuit of the present embodiment can be realized: when the input pin PIN_IN of chip input is high level, circuit output
OUT is held to export high level；When the input pin PIN_IN that the input pin PIN_IN of chip is in vacant state or chip is defeated
When entering low level, circuit output end OUT exports low level.
The setting circuit of the present embodiment, instead of it is traditional with a large amount of resistance or metal-oxide-semiconductor series connection ground connection circuit design,
Huge chip area was needed in the past just by the control of small number of analog device matching timing and the realization of lesser chip area
The function being able to achieve has been saved chip area in the case where guaranteeing that the default value of chip pin sets 0 function, has been realized higher
Integrated level and more inexpensive purpose；In power consumption, so that instantaneous power consumption is substantially zeroed in whole work process, thus
Achieve the purpose that quiescent dissipation is 0, significantly reduces power consumption.
Embodiment 2
As shown in figure 4, the setting circuit of the chip pin of the present embodiment is the further improvement to embodiment 1, specifically:
Switching tube M is NMOS tube.
It further includes the second NAND gate module I 4, third phase inverter I5 and the 4th phase inverter I6 that circuit, which is arranged,.
The input terminal of third phase inverter I5 is electrically connected with the pulse signal end SIGNAL of chip, the output of third phase inverter I5
End is electrically connected with the third input terminal of the second NAND gate module I 4；
Wherein, the pulse signal of pulse signal end SIGNAL can be START stage (incipient stage) generation in I2C agreement
Detection signal, be also possible to other self-control pulse signals, as long as in the input pin PIN_IN of system detection chip
Before input state.
4th input terminal of the second NAND gate module I 4 is electrically connected with the electrification reset end POR of chip, the second NAND gate mould
The output end of block I4 is electrically connected with the input terminal of the 4th phase inverter I6；
The output end of 4th phase inverter I6 is electrically connected with the first input end of the first NAND gate module I 1.
Wherein, the first NAND gate module I 1, the first phase inverter I2, the second phase inverter I3, the second NAND gate module I 4, third
Phase inverter I5 and the 4th phase inverter I6 can use CMOS (complementary metal oxide semiconductor) device.
The working principle of the setting circuit of the present embodiment is specifically described below:
As shown in figure 5, the clock signal of the electrification reset end POR of respectively chip, the I2C association of pulse signal end SIGNAL
The START stage of view corresponding system detection clock signal and the corresponding clock signal of switching tube M.
In view of only using electrification reset end POR when the parasitic capacitance of the input pin PIN_IN of chip is bigger
Reset signal to discharge time of parasitic capacitance may be inadequate situation, using chip in the upper of power up phase in the present embodiment
The reset signal of reset end POR turns on the switch pipe M (a stage in corresponding diagram 5), recycles the START stage of I2C agreement
System detection signaling switch pipe M (b-stage in corresponding diagram 5), i.e., by successively turning on the switch pipe M using two signals come more preferable
Drop-down be in floating state (vacant state) chip input pin PIN_IN.
Wherein, the first NAND gate module I 1, the first phase inverter I2, the second phase inverter I3 constitute the latch knot exported in the same direction
Structure so that the level signal of the input pin PIN_IN of chip is equal to the level signal of circuit output end OUT, and sets this
Circuits can only latch the state of PIN_IN=0.
By rationally designing the breadth length ratio of switching tube M, guarantee that the level signal of the input pin PIN_IN of chip is VDD
Circuit output end OUT will not be pulled down down GND (low level) when (high level), and be in the input pin PIN_IN of chip
Circuit output end OUT can be forgotten about it GND down completely when floating state, it may be assumed that
Work as PIN_IN=VDD, after switching tube M is opened and is ended, OUT=VDD；
Work as PIN_IN=floating, after switching tube M is opened and is ended, OUT=GND；
Work as PIN_IN=GND, after switching tube M is opened and is ended, OUT=GND.
Therefore, the setting circuit of the present embodiment in the case where the input pin PIN_IN of chip is in above-mentioned three kinds of input conditions all
There is no DC channels, to achieve the purpose that quiescent dissipation is zero.
The setting circuit of the present embodiment, instead of it is traditional with a large amount of resistance or metal-oxide-semiconductor series connection ground connection circuit design,
Huge chip area ability was needed in the past with the control of small number of analog device matching timing and the realization of lesser chip area
The function of realization has saved chip area in the case where guaranteeing that the default value of chip pin sets 0 function, has realized Geng Gaoji
Cheng Du and more inexpensive purpose；In power consumption, so that instantaneous power consumption is substantially zeroed in whole work process, to reach
The purpose for being 0 to quiescent dissipation, significantly reduces power consumption.
Embodiment 3
The chip of the present embodiment includes the setting circuit of embodiment 1 or the chip pin in embodiment 2.
Chip in the present embodiment includes the setting circuit of chip pin, ensure that the default value of the pin of the chip sets 0
Function, while having many advantages, such as to improve chip integration, reduce costs.
Although specific embodiments of the present invention have been described above, it will be appreciated by those of skill in the art that these
It is merely illustrative of, protection scope of the present invention is defined by the appended claims.Those skilled in the art is not carrying on the back
Under the premise of from the principle and substance of the present invention, various changes or modifications can be made to these embodiments, but these are changed
Protection scope of the present invention is each fallen with modification.
Claims (6)
1. a kind of setting circuit of chip pin, which is characterized in that the setting circuit includes switching tube, the first NAND gate mould
Block, the first phase inverter, the second phase inverter and circuit output end；
The drain electrode of the switching tube is electrically connected with the input terminal of the input pin of chip, first phase inverter respectively, described to open
The grid for closing pipe is electrically connected with the output end of the first NAND gate module, the source electrode ground connection of the switching tube；
The output end of first phase inverter is electrically connected with the input terminal of second phase inverter；
The first input end of the first NAND gate module is electrically connected with the electrification reset end of chip, the first NAND gate module
The second input terminal be electrically connected respectively with the output end of second phase inverter, the circuit output end.
2. the setting circuit of chip pin as described in claim 1, which is characterized in that the setting circuit further include second with
NOT gate module, third phase inverter and the 4th phase inverter；
The input terminal of the third phase inverter is electrically connected with the pulse signal end of chip, the output end of the third phase inverter and institute
State the third input terminal electrical connection of the second NAND gate module；
4th input terminal of the second NAND gate module is electrically connected with the electrification reset end of chip, the second NAND gate module
Output end be electrically connected with the input terminal of the 4th phase inverter；
The output end of 4th phase inverter is electrically connected with the first input end of the first NAND gate module.
3. the setting circuit of chip pin as described in claim 1, which is characterized in that when the input pin input of chip is height
When level, the circuit output end exports high level；
When the input pin of chip is in the input pin input low level of vacant state or chip, the circuit output end
Export low level.
4. the setting circuit of chip pin as described in claim 1, which is characterized in that the switching tube is metal-oxide-semiconductor.
5. the setting circuit of chip pin as described in claim 1, which is characterized in that the switching tube is NMOS tube.
6. a kind of chip, which is characterized in that the chip includes setting for chip pin described in any one of claim 1-5
Circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811652719.8A CN109684762B (en) | 2018-12-28 | 2018-12-28 | Chip and setting circuit of pin thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811652719.8A CN109684762B (en) | 2018-12-28 | 2018-12-28 | Chip and setting circuit of pin thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109684762A true CN109684762A (en) | 2019-04-26 |
| CN109684762B CN109684762B (en) | 2023-03-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811652719.8A Active CN109684762B (en) | 2018-12-28 | 2018-12-28 | Chip and setting circuit of pin thereof |
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| Country | Link |
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| CN (1) | CN109684762B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112218513A (en) * | 2020-10-13 | 2021-01-12 | Oppo广东移动通信有限公司 | Chip, antenna module and terminal |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2785260Y (en) * | 2005-03-22 | 2006-05-31 | 苏州市华芯微电子有限公司 | Low power-consuming, high reliability remote controller chip keystroke input port circuit |
| US20120105107A1 (en) * | 2010-11-02 | 2012-05-03 | Samsung Electronics Co., Ltd. | Voltage detection device and semiconductor device including the same |
| CN103023484A (en) * | 2012-12-03 | 2013-04-03 | 无锡海威半导体科技有限公司 | Ultra-low power consumption key scanning state selection circuit |
-
2018
- 2018-12-28 CN CN201811652719.8A patent/CN109684762B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2785260Y (en) * | 2005-03-22 | 2006-05-31 | 苏州市华芯微电子有限公司 | Low power-consuming, high reliability remote controller chip keystroke input port circuit |
| US20120105107A1 (en) * | 2010-11-02 | 2012-05-03 | Samsung Electronics Co., Ltd. | Voltage detection device and semiconductor device including the same |
| CN103023484A (en) * | 2012-12-03 | 2013-04-03 | 无锡海威半导体科技有限公司 | Ultra-low power consumption key scanning state selection circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112218513A (en) * | 2020-10-13 | 2021-01-12 | Oppo广东移动通信有限公司 | Chip, antenna module and terminal |
| CN112218513B (en) * | 2020-10-13 | 2023-08-22 | Oppo广东移动通信有限公司 | Chip, antenna module and terminal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109684762B (en) | 2023-03-24 |
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