CN208939812U - A kind of power supply monitoring management circuit of high-voltage starting circuit - Google Patents
A kind of power supply monitoring management circuit of high-voltage starting circuit Download PDFInfo
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- CN208939812U CN208939812U CN201821907484.8U CN201821907484U CN208939812U CN 208939812 U CN208939812 U CN 208939812U CN 201821907484 U CN201821907484 U CN 201821907484U CN 208939812 U CN208939812 U CN 208939812U
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Abstract
The utility model relates to microelectronics technology, the power supply monitoring of especially a kind of high-voltage starting circuit manages circuit；It includes resistance pressure-dividing network, threshold value comparison circuit and logic circuit；The circuit is mainly by resistance pressure-dividing network, threshold value comparison circuit composition, it is compared using the resistance pressure-dividing network output voltage changed with chip power voltage with the threshold value of N-type metal-oxide-semiconductor in technique, pass through the corresponding logic level of threshold value comparison circuit output, to realize over-voltage/under-voltage protection function, since the circuit does not need additional reference voltage source and comparator, greatly reduce device, simplify circuit structure, so that over-voltage/under-voltage protecting circuit area occupied is small, lower power consumption, simultaneously because of the reduction of device so that there is very big improvement in the corresponding time of protection circuit.
Description
Technical field
The utility model relates to microelectronics technology, the power supply monitoring of especially a kind of high-voltage starting circuit manages electricity
Road.
Background technique
High voltage integrated circuit is a kind of with functions such as various protection circuits, low-voltage control circuit, high voltage power devices
Gate driving circuit, power electronics in conjunction with semiconductor technology, is significantly improved the integrated level and stability of complete machine by it, tool
Have the advantages that integration density is high, small in size, speed is fast, low in energy consumption, gradually replaces traditional discrete device, more and more answered
Used in the drive area of MOSFET, IGBT.
In electric power management circuit, it is often necessary to which internal high-voltage starting obtains a band line by internal reference and pressure stabilizing
The burning voltage of wave is worked or is exported for power source internal.In general, needing high voltage startup before obtaining output burning voltage
Module provides a relatively rough voltage for internal integrated circuit, this voltage ripple is larger, is usually provided with to it under-voltage
(Under Voltage Lock Out, UVLO) and overvoltage protection (Over Voltage Protection, OVP) are protected, height is made
Pressing starting module is the continual and steady power supply of integrated circuit, it is ensured that the steady operation of this chip system.
Fig. 1 gives a kind of over-voltage/under-voltage protecting circuit of traditional integrated circuit, it includes providing the benchmark of reference voltage
It voltage source 1, the power supply bleeder circuit 2 with impedance mapping function, comparator 3 and is mainly patrolled by what some logical devices formed
Collect circuit 4.The input of power supply bleeder circuit terminates chip power voltage, output end, the power supply bleeder circuit 2 of reference voltage source 1
Output end connect respectively with the positive input of comparator 3 with reverse input end, the output end of comparator 3 and logic circuit 4
Input terminal connection, output end output overvoltage/UVP signal of logic circuit 4, which, which is sent to, is responsible for out
Logical, overvoltage protection signal is responsible for closing the module or voltage clamping module of high voltage startup, and control high voltage startup module prevents electricity
Press through height.
This over-voltage/under-voltage protecting circuit is mainly formed by datum mark potential source, comparator, power supply bleeder circuit, therefore is made
Component is more, area occupied is larger, the response time is compared with slow, power consumption is big and circuit design process is complicated.
Utility model content
In view of the deficiencies of the prior art, the utility model provides a kind of power supply monitoring management circuit of high-voltage starting circuit,
It has that structure is simple, device is few, area occupied is few, the response time is fast, and the advantages of small power consumption.
The technical solution of the utility model are as follows:
A kind of power supply monitoring management circuit of high-voltage starting circuit, it is characterised in that: it includes resistance pressure-dividing network, threshold value
Comparison circuit and logic circuit；
Wherein resistance pressure-dividing network includes the 4th resistance, the 5th resistance, the 6th resistance and the first MOS field effect transistor, the 4th electricity
It hinders first end and connects power end, the 4th resistance second end connects the 5th resistance first end, the second end of the 5th resistance
The first end of the 6th resistance is connected, the second end of the 6th resistance is separately connected the drain and gate of the first MOS field effect transistor；
Wherein threshold value comparison circuit includes the second MOS field effect transistor, third MOS field effect transistor, the 4th MOS field effect transistor, the 5th MOS field effect transistor, the 6th
MOS field effect transistor and the 7th MOS field effect transistor, the third MOS field effect transistor, the 4th MOS field effect transistor source electrode be all connected with another power end, the third field
The grid of effect pipe and the 4th MOS field effect transistor connects the drain electrode of the second MOS field effect transistor jointly, and the drain electrode of the third MOS field effect transistor connects second
Imitate the drain electrode of pipe, the drain electrode of the 5th MOS field effect transistor of drain electrode of the 4th MOS field effect transistor, the source electrode connection the 6th of the 5th MOS field effect transistor
The source electrode and drain electrode of MOS field effect transistor, the drain and gate of grid the second MOS field effect transistor of connection of the 6th MOS field effect transistor, described second
The source electrode of the source electrode, the 6th MOS field effect transistor of imitating pipe is grounded jointly；
The second end of 4th resistance connects the grid of the 5th MOS field effect transistor, the second end connection the 7th of the 5th resistance
The source electrode of MOS field effect transistor, the second end of the 6th resistance connect the drain electrode of the 7th MOS field effect transistor, and the grid of the 7th MOS field effect transistor connects
Connecing the drain electrode of the 5th MOS field effect transistor, the grid of first MOS field effect transistor is separately connected grid and the drain electrode of the second MOS field effect transistor, and described
The source electrode of one MOS field effect transistor connects the source electrode of the second MOS field effect transistor, and the drain electrode of the 5th MOS field effect transistor connects logic circuit, logic circuit
Output end output over-voltage protection signal.
Specifically, first MOS field effect transistor, the second MOS field effect transistor, the 5th MOS field effect transistor, the 6th MOS field effect transistor and the 7th MOS field effect transistor are equal
For N type metal-oxide-semiconductor.
Specifically, the third MOS field effect transistor and the 4th MOS field effect transistor are p-type metal-oxide-semiconductor.
The logic circuit includes the first phase inverter and the second phase inverter, the first phase inverter in one of the embodiments,
Output end connect the input terminal of the second phase inverter, the input terminal of the first phase inverter connects the drain electrode of the 5th MOS field effect transistor, and second is anti-
The output end output over-voltage protection signal of phase device.
In another embodiment, the logic circuit includes the first phase inverter, the second phase inverter, first capacitor and the 7th
Resistance, the output end of the first phase inverter connect the first end of the 7th resistance, and the second end of the 7th resistance is separately connected first capacitor
First end and the second phase inverter input terminal, the input terminal of the first phase inverter connects the drain electrode of the 5th MOS field effect transistor, first capacitor
Second end connect the 6th MOS field effect transistor source electrode, the output end output over-voltage protection signal of the second phase inverter.
The utility model has the following beneficial effects: the circuit is mainly made of resistance pressure-dividing network, threshold value comparison circuit, utilize
It is compared with the resistance pressure-dividing network output voltage of chip power voltage variation with the threshold value of N-type metal-oxide-semiconductor in technique, passes through threshold
It is worth comparison circuit and exports corresponding logic level, so that over-voltage/under-voltage protection function is realized, since the circuit does not need additionally
Reference voltage source and comparator, greatly reduce device, simplify circuit structure, so that over-voltage/under-voltage protecting circuit occupies
Area is small, lower power consumption, while because of the reduction of device so that there is very big improvement in the corresponding time of protection circuit.
Detailed description of the invention
Fig. 1 is traditional over-voltage/under-voltage protecting circuit figure；
Fig. 2 is the circuit diagram of the utility model；
Fig. 3 is the circuit diagram of embodiment 1；
Fig. 4 is the circuit diagram of embodiment 2；
Fig. 5 is over-voltage/UVP signal waveform diagram of the utility model output end output.
In figure, 1, reference voltage source；2, high-voltage end bleeder circuit；3, comparator；4, logic circuit；5, electric resistance partial pressure net
Network；6, threshold value comparison circuit.
Specific embodiment
Specific embodiment of the present utility model is described further with reference to the accompanying drawing:
Embodiment 1
As shown in Fig. 2,4,5, a kind of power supply monitoring of high-voltage starting circuit manages circuit, it include resistance pressure-dividing network 5,
Threshold value comparison circuit 6 and logic circuit 4；
Wherein resistance pressure-dividing network 5 includes the 4th resistance R4, the 5th resistance R5, the 6th resistance R6 and the first MOS field effect transistor M1,
The 4th resistance R4 first end connects power end VCC, and the 4th resistance R4 second end connects the 5th resistance R5 first end, institute
The second end for stating the 5th resistance R5 connects the first end of the 6th resistance R6, and the second end of the 6th resistance R6 is separately connected first
The drain and gate of MOS field effect transistor M1；
Wherein threshold value comparison circuit 6 includes the second MOS field effect transistor M2, third MOS field effect transistor M3, the 4th MOS field effect transistor M4, the 5th effect
Pipe M5, the 6th MOS field effect transistor M6 and the 7th MOS field effect transistor M7, the third MOS field effect transistor M3, the 4th MOS field effect transistor M4 source electrode be all connected with it is another
The grid of power end VDD, the third MOS field effect transistor M3 and the 4th MOS field effect transistor M4 connect the drain electrode of the second MOS field effect transistor M2, institute jointly
State the drain electrode of the second MOS field effect transistor M2 of drain electrode connection of third MOS field effect transistor M3, the 5th MOS field effect transistor M5 of drain electrode of the 4th MOS field effect transistor M4
Drain electrode, the source electrode of the 5th MOS field effect transistor M5 connects the source electrode and drain electrode of the 6th MOS field effect transistor M6, the 6th MOS field effect transistor M6's
Grid connects the drain and gate of the second MOS field effect transistor M2, and source electrode, the source electrode of the 6th MOS field effect transistor M6 of the second MOS field effect transistor M2 is total
With ground connection VSS；
The second end of the 4th resistance R4 connects the grid of the 5th MOS field effect transistor M5, and the second end of the 5th resistance R5 connects
Connecing the source electrode of the 7th MOS field effect transistor M7, the second end of the 6th resistance R6 connects the drain electrode of the 7th MOS field effect transistor M7, and described 7th
The grid for imitating pipe M7 connects the drain electrode of the 5th MOS field effect transistor M5, and the grid of the first MOS field effect transistor M1 is separately connected the second MOS field effect transistor M2
Grid and drain electrode, the source electrode of the first MOS field effect transistor M1 connect the source electrode of the second MOS field effect transistor M2, the 5th MOS field effect transistor M5's
Drain electrode connection logic circuit 4, the output end output over-voltage protection signal of logic circuit 4.
The first MOS field effect transistor M1, the second MOS field effect transistor M2, the 5th MOS field effect transistor M5, the 6th MOS field effect transistor M6 and the 7th MOS field effect transistor
M7 is N-type metal-oxide-semiconductor.
The third MOS field effect transistor M3 and the 4th MOS field effect transistor M4 is p-type metal-oxide-semiconductor.
The logic circuit 4 includes that the output end of the first phase inverter U1 and the second phase inverter U2, the first phase inverter U1 connects
The input terminal of second phase inverter U2, the input terminal of the first phase inverter U1 connect the drain electrode of the 5th MOS field effect transistor M5, the second phase inverter U2
Output end output over-voltage protection signal.
Embodiment 2
A kind of power supply monitoring management circuit of high-voltage starting circuit, it includes resistance pressure-dividing network 5, threshold value comparison circuit 6
With logic circuit 4；
Wherein resistance pressure-dividing network 5 includes the 4th resistance R4, the 5th resistance R5, the 6th resistance R6 and the first MOS field effect transistor M1,
The 4th resistance R4 first end connects power end VCC, and the 4th resistance R4 second end connects the 5th resistance R5 first end, institute
The second end for stating the 5th resistance R5 connects the first end of the 6th resistance R6, and the second end of the 6th resistance R6 is separately connected first
The drain and gate of MOS field effect transistor M1；
Wherein threshold value comparison circuit 6 includes the second MOS field effect transistor M2, third MOS field effect transistor M3, the 4th MOS field effect transistor M4, the 5th effect
Pipe M5, the 6th MOS field effect transistor M6 and the 7th MOS field effect transistor M7, the third MOS field effect transistor M3, the 4th MOS field effect transistor M4 source electrode be all connected with it is another
The grid of power end VDD, the third MOS field effect transistor M3 and the 4th MOS field effect transistor M4 connect the drain electrode of the second MOS field effect transistor M2, institute jointly
State the drain electrode of the second MOS field effect transistor M2 of drain electrode connection of third MOS field effect transistor M3, the 5th MOS field effect transistor M5 of drain electrode of the 4th MOS field effect transistor M4
Drain electrode, the source electrode of the 5th MOS field effect transistor M5 connects the source electrode and drain electrode of the 6th MOS field effect transistor M6, the 6th MOS field effect transistor M6's
Grid connects the drain and gate of the second MOS field effect transistor M2, and source electrode, the source electrode of the 6th MOS field effect transistor M6 of the second MOS field effect transistor M2 is total
With ground connection VSS；
The second end of the 4th resistance R4 connects the grid of the 5th MOS field effect transistor M5, and the second end of the 5th resistance R5 connects
Connecing the source electrode of the 7th MOS field effect transistor M7, the second end of the 6th resistance R6 connects the drain electrode of the 7th MOS field effect transistor M7, and described 7th
The grid for imitating pipe M7 connects the drain electrode of the 5th MOS field effect transistor M5, and the grid of the first MOS field effect transistor M1 is separately connected the second MOS field effect transistor M2
Grid and drain electrode, the source electrode of the first MOS field effect transistor M1 connect the source electrode of the second MOS field effect transistor M2, the 5th MOS field effect transistor M5's
Drain electrode connection logic circuit 4, the output end output over-voltage protection signal of logic circuit 4.
The first MOS field effect transistor M1, the second MOS field effect transistor M2, the 5th MOS field effect transistor M5, the 6th MOS field effect transistor M6 and the 7th MOS field effect transistor
M7 is N-type metal-oxide-semiconductor.
The third MOS field effect transistor M3 and the 4th MOS field effect transistor M4 is p-type metal-oxide-semiconductor.
The logic circuit 4 includes the first phase inverter U1, the second phase inverter U2, first capacitor C1 and the 7th resistance R7, the
The output end of one phase inverter U1 connects the first end of the 7th resistance R7, and the second end of the 7th resistance R7 is separately connected first capacitor
The input terminal of the first end of C1 and the second phase inverter U2, the input terminal of the first phase inverter U1 connect the drain electrode of the 5th MOS field effect transistor M5,
The second end of first capacitor C1 connects the source electrode of the 6th MOS field effect transistor M6, the output end output over-voltage protection letter of the second phase inverter U2
Number.
Compared with prior art, the utility model has the advantage of the circuits mainly by resistance pressure-dividing network, threshold value comparison
Circuit composition, does ratio with the threshold value of NMOS in technique using the resistance pressure-dividing network output voltage changed with chip power voltage
Compared with by the corresponding logic level of threshold value comparison circuit output, so that over-voltage/under-voltage protection function is realized, due to the circuit
Additional reference voltage source and comparator are not needed, device is greatly reduced, simplifies circuit structure, so that over-voltage/under-voltage guarantor
Protection circuit area occupied is small, lower power consumption, while because of the reduction of device so that there be very big change in the corresponding time of protection circuit
It is kind.
Fig. 2 is the under-voltage protecting circuit schematic diagram one of the utility model.
Over-voltage/under-voltage protecting circuit that the utility model is proposed mainly utilize the threshold voltage (Vth) of NMOS M5 as
Reference voltage, R4 and the output voltage (Vgs) of the junction R5 are connected to the grid of M5 in resistance pressure-dividing network, as Vgs > Vth,
It is at this time UVP signal as Vgs < Vth that overvoltage protection signal, which exports low level, and UVP signal exports high level.
Resistance pressure-dividing network output voltage Vgs value can realize by adjusting the parameter value of each component in resistance pressure-dividing network, Vgs >
The over-voltage voltage of overvoltage crowbar of the corresponding chip power voltage value V+ as the utility model, Vgs < Vth when Vth
When under-voltage protecting circuit as the utility model of corresponding chip power voltage value V- brownout voltage.To realize this reality
With novel over-voltage/under-voltage protecting circuit basic function.Here, protecting hysteresis voltage required for circuit in order to obtain, make
It is in parallel with the R6 in resistance pressure-dividing network with NMOS M7, after chip power voltage is reduced to V-, M7 conducting, so that output electricity
The ratio that pressure Vgs accounts for chip power voltage reduces, and when Vgs voltage is again raised to Vth, corresponding V+ is greater than V-, leads to
Required protection circuit hysteresis voltage can be obtained in the component parameter for crossing adjustment resistance pressure-dividing network.
NMOS M1 that resistance pressure-dividing network is connected by diode, resistance R4, resistance R5, resistance R6 are formed, the above component
The resistance pressure-dividing network of composition is connected to chip power between ground, and output voltage Vgs and supply voltage are arranged in certain ratio and closed
It is K, Vgs=K*VCC.NMOS M5 realization impedance transformation in parallel with R8, is reduced to the process of brownout voltage in chip power voltage
In, M5 shutdown, the ratio of output voltage Vgs and supply voltage is K1, Vgs=K1*VCC at this time, as Vgs < Vth, VCC <
Vth/K1, so brownout voltage V-=Vth/K1.During chip power voltage rises to over-voltage voltage, M5 conducting, this
When output voltage Vgs and supply voltage ratio be K2, Vgs=K2*VCC, as Vgs > Vth, VCC > Vth/K2, so mistake
Piezoelectricity presses V+=Vth/K2.K1 > K2, so V+ > V-, (V+)-(V-) is the hysteresis voltage for protecting circuit, by adjust K1,
The value of K2 can be designed required V+ and V-.
Threshold value comparison circuit forms current-mirror structure by NMOS M2, M5, M6, PMOS M3, M4 composition, M6, M2 and M1,
M3, M4 form current-mirror structure, by the current replication of resistance pressure-dividing network to M4, realize that the pull-up to protection signal acts on.When
M5 is turned off when Vgs < Vth, and it is at this time under-voltage condition that voltage protecting signal, which exports high level,；M5 is connected when Vgs > Vth, and voltage is protected
It protects signal and low level is pulled low to by M6, be at this time overvoltage condition.Voltage protecting signal is admitted to other circuit modules of chip, right
Output end executes corresponding operation.
It is appropriate by the larger of the sum of R4, R5, R6 resistance design in resistance pressure-dividing network design process, reduce circuit
Quiescent current.The mutual ratio between R4, R5, R6 is adjusted to determine over-voltage voltage V+ and brownout voltage V-.Adjust M7's
Breadth length ratio can be realized the short circuit to R6 in M7 conducting.In threshold value comparison circuit, by adjusting the breadth length ratio and M2, M6 of M1
At than column, wherein M6:M2=2:1, M3:M4=1:1, realize the pull-up effect of M4, and realize the strong pull-down effect of M6, in physics
M1 and M2, M6, the matching of M3 and M4 are paid attention in the design of layer.
Fig. 2 is that the utility model protects circuit, wherein there are also logic circuits 4 below.
Logic circuit 4, input terminal and the threshold value comparison circuit of logic circuit 4 are terminated in the output of threshold value comparison circuit
Output end connection.The output signal of threshold value comparison circuit is after the processing of logic circuit 4, via 4 output over-voltage protection of logic circuit
Signal.Logic circuit 4 is mainly made of phase inverter, for arranging the signal output waveform of threshold value comparison circuit, makes the signal
Rising edge failing edge becomes more precipitous, the relatively good needs for meeting subsequent conditioning circuit.It can also be added and make an uproar in logic circuit 4
Acoustic filter, to prevent the under-voltage protection false triggering of moment.
Such as Fig. 3, logic circuit 4 is made of two phase inverters U1, U2, and U1 inputs the output for connecing threshold value comparison circuit, and U1 is defeated
U2 input is connect out, and U2 output is over-voltage/UVP signal.
Such as Fig. 4, logic circuit 4 is made of to realize noise filtering function phase inverter U1, phase inverter U2, resistance R7, capacitor C1
Energy.
Fig. 5 gives over-voltage/under-voltage protecting circuit output end output over-voltage/UVP signal of the utility model
Waveform diagram.As can be seen from Figure 5 it rises on the supply voltage the stage, supply voltage crosses piezoelectricity less than voltage protection circuit
When pressure, overvoltage protection signal follows mains voltage variations, is not started to work by the controlled chip of overvoltage crowbar at this time, works as electricity
When source voltage rises to over-voltage voltage, overvoltage protection signal exports low level, which stop chip high voltage power supply module
Work.In the supply voltage decline stage, as long as supply voltage does not drop to the brownout voltage of voltage protection circuit, overvoltage protection
Signal keeps low level output, and when supply voltage drops to brownout voltage, overvoltage protection signal output follows supply voltage to become
Change, chip will open the power supply of high voltage supply end.The difference of over-voltage voltage and brownout voltage is the sluggishness electricity of overvoltage crowbar
Pressure.
The description of the embodiments and the specification only illustrate the principle of the present utility model and most preferred embodiment, is not taking off
Under the premise of from the spirit and scope of the utility model, the utility model also has various changes and improvements, these changes and improvements
It falls within the scope of the claimed invention.
Claims (5)
1. a kind of power supply monitoring of high-voltage starting circuit manages circuit, it is characterised in that: it includes resistance pressure-dividing network, threshold value ratio
Compared with circuit and logic circuit；
Wherein resistance pressure-dividing network includes the 4th resistance, the 5th resistance, the 6th resistance and the first MOS field effect transistor, the 4th resistance the
One end connects power end, and the 4th resistance second end connects the 5th resistance first end, the second end connection of the 5th resistance
The second end of the first end of 6th resistance, the 6th resistance is separately connected the drain and gate of the first MOS field effect transistor；
Wherein threshold value comparison circuit includes the second MOS field effect transistor, third MOS field effect transistor, the 4th MOS field effect transistor, the 5th MOS field effect transistor, the 6th effect
Pipe and the 7th MOS field effect transistor, the third MOS field effect transistor, the 4th MOS field effect transistor source electrode be all connected with another power end, the third MOS field effect transistor
Connect the drain electrode of the second MOS field effect transistor jointly with the grid of the 4th MOS field effect transistor, the drain electrode of the third MOS field effect transistor connects the second MOS field effect transistor
Drain electrode, the drain electrode of the 5th MOS field effect transistor of drain electrode of the 4th MOS field effect transistor, the source electrode of the 5th MOS field effect transistor connects the 6th effect
The source electrode and drain electrode of pipe, the grid of the 6th MOS field effect transistor connect the drain and gate of the second MOS field effect transistor, second MOS field effect transistor
Source electrode, the 6th MOS field effect transistor source electrode be grounded jointly；
The second end of 4th resistance connects the grid of the 5th MOS field effect transistor, and the second end of the 5th resistance connects the 7th effect
The source electrode of pipe, the second end of the 6th resistance connect the drain electrode of the 7th MOS field effect transistor, the grid connection of the 7th MOS field effect transistor the
The drain electrode of five MOS field effect transistors, the grid of first MOS field effect transistor are separately connected grid and the drain electrode of the second MOS field effect transistor, and described first
The source electrode for imitating pipe connects the source electrode of the second MOS field effect transistor, and the drain electrode of the 5th MOS field effect transistor connects logic circuit.
2. the power supply monitoring of high-voltage starting circuit according to claim 1 a kind of manages circuit, it is characterised in that: described the
One MOS field effect transistor, the second MOS field effect transistor, the 5th MOS field effect transistor, the 6th MOS field effect transistor and the 7th MOS field effect transistor are N-type metal-oxide-semiconductor.
3. the power supply monitoring of high-voltage starting circuit according to claim 2 a kind of manages circuit, it is characterised in that: described the
Three MOS field effect transistors and the 4th MOS field effect transistor are p-type metal-oxide-semiconductor.
4. a kind of power supply monitoring of high-voltage starting circuit according to claim 3 manages circuit, it is characterised in that: described to patrol
Collecting circuit includes the first phase inverter and the second phase inverter, and the output end of the first phase inverter connects the input terminal of the second phase inverter, the
The input terminal of one phase inverter connects the drain electrode of the 5th MOS field effect transistor.
5. a kind of power supply monitoring of high-voltage starting circuit according to claim 3 manages circuit, it is characterised in that: described to patrol
Collecting circuit includes the first phase inverter, the second phase inverter, first capacitor and the 7th resistance, the output end connection the 7th of the first phase inverter
The first end of resistance, the second end of the 7th resistance are separately connected the first end of first capacitor and the input terminal of the second phase inverter, the
The input terminal of one phase inverter connects the drain electrode of the 5th MOS field effect transistor, and the second end of first capacitor connects the source electrode of the 6th MOS field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821907484.8U CN208939812U (en) | 2018-11-20 | 2018-11-20 | A kind of power supply monitoring management circuit of high-voltage starting circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821907484.8U CN208939812U (en) | 2018-11-20 | 2018-11-20 | A kind of power supply monitoring management circuit of high-voltage starting circuit |
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| CN208939812U true CN208939812U (en) | 2019-06-04 |
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| CN201821907484.8U Active CN208939812U (en) | 2018-11-20 | 2018-11-20 | A kind of power supply monitoring management circuit of high-voltage starting circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109194099A (en) * | 2018-11-20 | 2019-01-11 | 广州市力驰微电子科技有限公司 | A kind of power supply monitoring management circuit of high-voltage starting circuit |
| CN110412338A (en) * | 2019-08-08 | 2019-11-05 | 电子科技大学 | A kind of high-voltage detecting circuit |
-
2018
- 2018-11-20 CN CN201821907484.8U patent/CN208939812U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109194099A (en) * | 2018-11-20 | 2019-01-11 | 广州市力驰微电子科技有限公司 | A kind of power supply monitoring management circuit of high-voltage starting circuit |
| CN110412338A (en) * | 2019-08-08 | 2019-11-05 | 电子科技大学 | A kind of high-voltage detecting circuit |
| CN110412338B (en) * | 2019-08-08 | 2021-03-30 | 电子科技大学 | High-voltage detection circuit |
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