JPH104144A - Electrostatic breakdown protective device in integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electrostatic breakdown protective device suitable for the utilization to the manufacturing process of a semiconductor to an extent of submicrons, by a method wherein the width of a gate is regulated and the punch-through voltage of a CMOS transistor is adjusted at such a low level that the voltage triggers a parasitic SCR and an ESD current can be by-passed. SOLUTION: A gate oxide film 23 is formed on the surfaces of a p-type silicon substrate 20 and an n-type well layer 21, a polysilicon layer 24 is formed on the film 23 and the film 23 is combined with the layer 24 to form a gate of a CMOS transistor. The width (d) of the layer 24 of the CMOS transistor is regulated to adjust the interval (s) between the layer 21 and an n<+> diffused region 26 so as to make the interval (s) narrow. As a result, the punch-through voltage of the transistor is reduced to lower a trigger voltage to a parasitic silicon controlled rectifier(SCR). Accordingly, the voltage triggers the SCR to turn the SCR on and it is made possible to adjust the voltage at such a low level as to be able to by-pass an ESD current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit (IC).
In particular, it is provided in an integrated circuit to protect the integrated circuit from electrostatic breakdown by providing a low trigger voltage to a silicon controlled rectifier (SCR), particularly by providing a low trigger voltage to a silicon controlled rectifier (SCR). The present invention relates to an ESD destruction prevention device.

[0002]

2. Description of the Related Art A circuit element such as a semiconductor in an IC may be destroyed by electrostatic discharge (ESD) generated by movement of static electricity from a nonconductive surface. For example, a person walking on a carpet carries a significant amount of electrostatic charge of up to several thousand volts under high humidity and 10,000 volts or more under low humidity. When an IC is touched by a hand, electrostatic charges flow from the human body to the IC and have an energy level of several million joules (MJ) and a short discharge time of only a few nanoseconds (ns) or microseconds (μs). ESD occurs. As a result, the instantaneous power levels of ESD can be as high as hundreds of kilowatts, with currents up to tens of amps, which can seriously damage the IC. C
MOS (complementary metal oxide semiconductor) logic ICs, in particular,
Susceptible to ESD. A conventional method for protecting a CMOS logic IC from ESD is to provide an ESD protection device in a chip.

[0003] Conditions basically required for an on-chip ESD destruction prevention device are a high fault threshold voltage, a narrow layout area, and a small RC (resistance-capacitor) delay. Silicon controlled rectifier (SCR)
Has a high current sink / source capability, extremely low turn-on impedance, low power consumption, and high heat dissipation coefficient, and is therefore the most widely used element for an on-chip ESD damage prevention device at present.

FIG. 3 is a schematic cross-sectional view showing a semiconductor structure of a conventional SCR. A p ⁺ type silicon substrate 10, an n type well layer (well) 11, a p ⁺ type diffusion region 12, an n ⁺ type diffusion region 13, An n ⁺ diffusion region 14, a p ⁺ diffusion region 15 and an input / output (I / O) pad 16 are shown. p
^The parasitic PNP bipolar transistor is formed by combining the ⁺ type silicon substrate 10, the n type well layer 11 and the p ⁺ type diffusion region 12, while the p ⁺ type silicon substrate 10, n
The parasitic NPN bipolar transistor is formed by combining the type well layer 11 and the n ⁺ type diffusion region 13.
The collector of the parasitic PNP bipolar transistor is electrically connected to the base of the parasitic NPN bipolar transistor, and similarly, the collector of the parasitic NPN bipolar transistor is electrically connected to the base of the parasitic PNP bipolar transistor. A parasitic SCR is configured by the circuit elements arranged as described above. n-type well layer 11
Via the n ⁺ -type diffusion region 14 is connected to the I / O pads 16, p ⁺ -type silicon substrate 10 is p ⁺ -type diffusion region 1
5 is connected to the ground potential Vss. Taking a 1 micrometer CMOS manufacturing method as an example, S
If the CR drain is a highly doped silicide diffusion region and the anode and cathode are 6 micrometers apart, the SCR trigger voltage is typically about 50V.

[0005]

In order to implement ESD protection, the trigger voltage of the ESD protection device must be lower than a critical voltage that damages an input buffer or an output driver. Therefore, the SC shown in FIG.
Although R is a widely used ESD protection device, its relatively high trigger voltage (typically above 30 V) is still unsuitable for use in submicron semiconductor manufacturing. C manufactured by submicron manufacturing method
MOS logic ICs generally have a thin gate oxide that lowers the breakdown voltage. As a result, the trigger voltage of the SCR exceeds the breakdown voltage of the CMOS transistor,
The D destruction prevention force will be weakened.

Accordingly, the present invention provides an ESD protection device with an SCR in a CMOS transistor integrated circuit that triggers the SCR with a relatively low punch-through voltage so as to provide improved ESD protection. It is in.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above and other objects, the present invention provides a new and improved ESD damage prevention device. This ESD destruction prevention device
(A) a silicon substrate, (b) a well layer formed on a silicon substrate, and (c) first and second layers formed on a well layer.
A diffusion region; (d) third and fourth diffusion regions formed on the silicon substrate outside the well layer; and (e) a gate formed covering the silicon substrate between the third diffusion region and the well layer. In the above structure, a CMOS transistor is configured by combining the gate, the well layer, and the third diffusion region. Furthermore, a parasitic silicon control rectifier (SC
R) is formed. By adjusting the width of the gate,
The punch-through voltage of the CMOS transistor can be adjusted to such a low level that the parasitic SCR can be triggered by that voltage to bypass the ESD current to prevent ESD damage to the integrated circuit.

[0008]

1 (A) to 1 (C) are schematic cross-sectional views illustrating steps involved in a process of manufacturing a CMOS integrated circuit provided with an ESD protection device according to the present invention. FIG.
To explain (A), in the first stage of the manufacturing process,
A silicon substrate on which a well layer, for example, an n-type well layer 21 is formed, for example, a p-type silicon substrate 20 is provided. Next, boundaries of the active region on the silicon substrate 20 are determined so that a plurality of field oxide films 22 can be formed. In the next stage, for example, a dry oxidation process (dry o
The gate oxide film 23 is formed on the surfaces of the p-type silicon substrate 20 and the n-type well layer 21 by the xidation process. Thereafter, for example, a chemical vapor deposition method (C
VD), the polysilicon layer 2 is formed on the gate oxide film 23.
4 is formed, and a gate oxide film 23 and a polysilicon layer 24 are formed.
Are combined to form the gate of the CMOS transistor.

Referring to FIG. 1B, in the next step, for example, phosphorus or arsenic ions are ion-implanted using a photoresist mask into the gate oxide film 2.
3 are diffused into a p-type silicon substrate 20 and an n-type well layer 21 opposite to each other.
0 and n ⁺ -type diffusion regions 26 and 25 of n-type well layer 21
To form

Next, referring to FIG. 1C, an ion implantation method is performed using a photoresist mask, for example, boron ions are diffused into the p-type silicon substrate 20 and the n-type well layer to perform field oxidation. The p on the p-type silicon substrate 20 and the n-type well layer 21 separated from the n ⁺ -type diffusion regions 25 and 26 by the film 22, respectively.
⁺ -Type diffusion regions 28 and 27 are formed, respectively. Thereafter, p ⁺ type diffusion region 27 and n ⁺ type diffusion region 25
/ O pad 29. Further, the polysilicon layer 24, the n ⁺ type diffusion region 26 and the p ⁺ type diffusion region 28 are connected to Vss.

Referring to FIG. 1C and FIG. 2 which shows an equivalent circuit of the semiconductor structure shown in FIG. 1C, the p ⁺ -type diffusion region 27, the n-type well layer 21 and the p-type silicon substrate 20 are combined to form a parasitic. A PNP bipolar transistor 30 (schematically shown in FIG. 2) is configured and has n ⁺
A parasitic NPN bipolar transistor 31 (schematically shown in FIG. 2) is formed by combining the type diffusion region 26, the p-type silicon substrate 20, and the n-type well layer 21. Further, the parasitic PNP bipolar transistor 30
The SCR 32 is configured by a combination of the SCR 32 and the parasitic NPN bipolar transistor 31. Parasitic PNP bipolar transistor 30 includes an emitter (ie, p ⁺ type diffusion region 27) connected to I / O pad 34,
It has a base connected to the collector of the parasitic NPN bipolar transistor 31 and a collector connected to Vss (by connecting the p-type silicon substrate 20 to Vss via the p ⁺ -type diffusion region 28). , Parasitic NPN
Bipolar transistor 31 has a base connected to the collector of parasitic PNP bipolar transistor 30,
The emitter connected to ss (ie, n ⁺ type diffusion region 2)
6) and (n ⁺ -type well layer 2 via n ⁺ -type diffusion region 25).
A collector connected to the I / O pad 34 (by connecting 1 to the I / O pad 34).

An n-type well layer 21, an n ⁺ -type diffusion region 26,
The combination of the polysilicon layer 24 and the gate oxide film 23 forms a CMOS transistor 33 (shown schematically in FIG. 2). CMOS transistor 33
Has a drain connected to the collector of the parasitic NPN bipolar transistor 31, a gate and a source connected to Vss (that is, the n ⁺ type diffusion region 26).

FIG. 2 shows a circuit in which an ESD destruction prevention measure is taken by the ESD destruction prevention device according to the present invention.
This is indicated by the block labeled "internal circuit" and referenced 35. The internal circuit 35 for which this ESD destruction prevention measure is taken is composed of the I / O pad 34 and the V
is connected between ss. The resistor R _w represents the equivalent parasitic resistance of the n-type well layer 21, and the resistor R _s
5 shows an equivalent parasitic resistance of the p-type silicon substrate 20.

According to the present invention, the n ⁺ -type diffusion region 25 and the p ⁺ -type diffusion region 27 do not have to be arranged at the positions shown in the figure. The positions of the two diffusion regions 25 and 27 can be exchanged. In contrast, even when the such region 25 and region 27 is reversed, the n ⁺ -type diffusion region 26 and p ⁺ -type diffusion region 28, n ⁺ -type diffusion region 2
6 is combined with n-type well layer 21, polysilicon layer 24 and gate oxide film 23 to form CMOS transistor 3
3 must be arranged in the relative positions shown so that they can be formed.

However, the p-type silicon substrate 20
It is not limited to the disclosed p-type, but can be n-type instead. When an n-type silicon substrate is used, a p-type well layer is formed instead of the n-type well layer 21. Further, the positions of the n ⁺ -type diffusion region 26 and the p ⁺ -type diffusion region 28 must be exchanged so that the CMOS transistor 33 can be formed.

[0016] In a preferred embodiment of the present invention, by adjusting the width d of the polysilicon layer 24 as shown in FIG. 1 (C), between the n-type well layer 21 and the n ⁺ -type diffusion region 26 The interval s can be adjusted. The smaller the interval s, the lower the punch-through voltage of the CMOS transistor 33, and consequently, the lower the trigger voltage to the SCR 32. In this embodiment, for example, the interval s is set to about 1.5 to
By adjusting to within the range of 3.0 micrometers, the punch-through voltage of the CMOS transistor 33 is reduced.
It can be suppressed within a range of about 6 to 10V. E on IC
When the SD occurs, a low punch-through voltage always occurs, and the CMO is generated before the ESD current reaches the internal circuit 35.
Since the S-transistor 33 receives the avalanche, a large amount of current is generated, the SCR 32 is triggered to be turned on, and the ESD current can be bypassed, so that the inflow of the ESD current to the internal circuit 35 is avoided.

[0017]

From the above description, it is apparent that the present invention has the following advantages. First, the present invention adjusts the width of the polysilicon layer so that the punch-through voltage of the CMOS transistor can be bypassed, which voltage can trigger a parasitic SCR to bypass the ESD current to prevent ESD damage to internal circuitry. By adjusting to a low level, S
Making CR technology suitable for use in submicron semiconductor manufacturing processes. Second, the manufacturing method of the ESD protection device according to the present invention is compatible with existing semiconductor manufacturing processes for manufacturing integrated circuits, and therefore, the manufacturing method according to the present invention is easy to adopt.

Although the present invention has been described with reference to the typical embodiments, it is needless to say that the scope of the present invention is not limited to the above-described embodiments, but rather, as is well known, various modifications are possible. And similar structures. The scope of the claims should be given the broadest interpretation so as to cover all such variations and similar structures.

[Brief description of the drawings]

FIG. 1 is a CM having an ESD destruction prevention device according to the present invention.
FIG. 9 is a schematic cross-sectional view illustrating a step related to a manufacturing process of an OS integrated circuit.

FIG. 2 is an equivalent circuit of the CMOS integrated circuit in FIG.

FIG. 3 is a schematic sectional view showing a semiconductor structure of a conventional SCR.

[Explanation of symbols]

Reference Signs List 20 p-type silicon substrate 21 n-type well layer 22 field oxide film 23 gate oxide film 24 polysilicon layer 25 n ⁺ -type diffusion region 26 n ⁺ -type diffusion region 27 p ⁺ -type diffusion region 28 p ⁺ -type diffusion region 30 parasitic PNP bipolar Transistor 31 Parasitic NPN bipolar transistor 32 SCR 33 CMOS transistor 35 Internal circuit

Continuation of front page (71) Applicant 596068419 No. 4, Creation Road II, Science-Based Industrial Park, Hsinchu City, Taiwan, R.A. OC (72) Inventor Chin Cheng Sue, Cumming Road V 61, Nanto, Taiwan

Claims (12)

[Claims] A silicon substrate; a well layer formed in the silicon substrate; a first diffusion region formed in the well layer; a second diffusion region formed in the well layer; A third layer formed on the silicon substrate outside the layer
A fourth diffusion region formed on the silicon substrate outside the well layer and located farther from the well layer than the third diffusion region; and a third diffusion region. And a gate formed to cover the silicon substrate between the gate and the well layer, wherein a CMOS transistor is configured by combining the gate, the well layer and the third diffusion region. Prevention device. 2. The device according to claim 1, wherein said silicon substrate is a p-type silicon substrate. 3. The ESD damage prevention device according to claim 2, wherein said well layer is an n-type well layer. 4. The first diffusion region is doped with boron ions, the second diffusion region is doped with phosphorus ions, the third diffusion region is doped with phosphorus ions, and the fourth diffusion region is doped with boron ions. The ESD destruction prevention device according to claim 3, wherein: 5. An interval between the well layer and the third diffusion region is set to be within about 1.5 to 3.0 micrometers so as to suppress a punch through voltage of the CMOS transistor within a range of about 6 to 10 V. 5. The ESD destruction prevention device according to claim 4, wherein: 6. The ESD protection device according to claim 1, wherein the silicon substrate is an n-type silicon substrate. 7. The ESD damage prevention device according to claim 6, wherein said well layer is a p-type well layer. 8. The first diffusion region is doped with boron ions, the second diffusion region is doped with phosphorus ions, the third diffusion region is doped with boron ions, and the fourth diffusion region is doped with phosphorus ions. The ESD destruction prevention apparatus according to claim 7, wherein: 9. The semiconductor device according to claim 1, further comprising a plurality of field oxide films for separating said first diffusion region, said second diffusion region, said third diffusion region, and said fourth diffusion region from each other. The ESD destruction prevention device according to claim 1, wherein 10. The semiconductor device according to claim 1, wherein the gate is formed between the third diffusion region and the second diffusion region, and covers the silicon substrate and a part of the well layer. Item 4. The ESD destruction prevention device according to Item 1. 11. A first conductivity type silicon substrate, a second conductivity type well layer formed on the silicon substrate, a first diffusion region formed on the well layer, and a first diffusion region formed on the well layer. A second diffusion region formed on the silicon substrate outside the well layer, a third diffusion region of the second conductivity type, and a first conduction region formed on the silicon substrate outside the well layer. A fourth diffusion region of a conductive type and located farther from the well layer than the third diffusion region; and the silicon substrate between the third diffusion region and the well layer. And a gate formed so as to cover the gate, the gate layer, the well layer, and the third diffusion region to form a CMOS transistor. 12. The semiconductor device according to claim 11, wherein the gate is formed between the third diffusion region and the second diffusion region, and covers the silicon substrate and a part of the well layer. 12. The ESD destruction prevention apparatus according to 11.