TWI834037B - Semiconductor device - Google Patents

Abstract

A semiconductor device is provided herein, which includes a semiconductor substrate, a first well, a second well, a field oxide layer, and a polysilicon layer. The semiconductor substrate has a first conductivity type. The first well is deposited in the semiconductor substrate and has a second conductivity type. The second well is formed in the first well and has the first conductivity type. The field oxide layer is deposited on the second well. The polysilicon layer is deposited on the field oxide layer, and a resistance device is formed by the polysilicon layer.

Description

Semiconductor device

The present invention relates to a semiconductor device, and in particular to a semiconductor device that increases the withstand voltage of a resistive element and provides electrostatic discharge protection.

With the development of high-voltage integrated circuits, especially for some AC-to-DC circuits used for high-voltage alternating current, some resistive components need to withstand high voltages of hundreds of volts. However, before reaching high voltages of hundreds of volts, traditional high-voltage resistor components may encounter component breakdown problems, making traditional resistors unable to meet demand.

By manufacturing polysilicon resistors on the field oxide layer, the withstand voltage can be greatly improved. The withstand voltage mainly depends on the thickness of the field oxide layer. The withstand voltage of the field oxide layer in general processes can reach 300-400V. However, for high-voltage alternating current AC-to-DC circuits, the highest peak voltage received by the resistive element may be as high as 500 to 650V, making polycrystalline silicon resistors unable to meet the demand. Therefore, it is necessary to improve the withstand voltage of resistive elements.

The semiconductor device proposed by the present invention can not only increase the withstand voltage of the resistor element, but also provide a path for electrostatic charge removal, so that in addition to meeting the needs of high-voltage applications, the polycrystalline silicon resistor can also meet the demand for electrostatic discharge protection at one end of the polycrystalline silicon resistor. time, providing the required protection function.

In view of this, the present invention proposes a semiconductor device, which includes a semiconductor substrate, a first well region, a second well region, a field oxide layer and a polycrystalline silicon layer. The above-mentioned semiconductor substrate has a first conductivity type. The first well region is formed in the semiconductor substrate and has a second conductivity type. The second well region is formed in the first well region and has the first conductivity type. The field oxide layer is formed on the second well region. The polycrystalline silicon layer is formed on the field oxide layer and forms a resistive element.

According to an embodiment of the invention, the semiconductor device further includes a first top doped layer and a second top doped layer. The first top doped layer is formed in the first well region and has the first conductivity type. The second top doped layer is formed in the first well region and has the first conductivity type, wherein the first top doped layer and the second top doped layer are located on both sides of the second well region, and They are separated from each other from the above-mentioned second well area.

According to an embodiment of the present invention, the semiconductor device further includes a third well region and a doping region. The third well region is formed in the semiconductor substrate and has the first conductivity type. The doping region is formed in the third well region and has the first conductivity type, wherein the doping region is coupled to a ground terminal.

The invention further provides a semiconductor device, which includes a semiconductor substrate, a first well region, a second well region, a first doping region, a field oxide layer and a polycrystalline silicon layer. The above-mentioned semiconductor substrate has a first conductivity type. The first well region is formed in the semiconductor substrate and has a second conductivity type. The second well region is formed in the first well region and has the second conductivity type. The first doped region is formed in the second well region and has the second conductivity type. The field oxide layer is formed on the first well region and surrounds the first doped region. The polycrystalline silicon layer is formed on the field oxide layer and forms a resistive element.

According to an embodiment of the invention, the semiconductor device further includes a first top doped layer and a second top doped layer. The first top doped layer is formed in the first well region and has the first conductivity type. The second top doped layer is formed in the first well region and has the first conductivity type, wherein the first top doped layer and the second top doped layer are located on both sides of the second well region, wherein The resistive element is further formed on the first top doped layer and the second top doped layer.

According to an embodiment of the present invention, the semiconductor device further includes a third well region and a second doping region. The third well region is formed in the semiconductor substrate and has the first conductivity type. The second doped region is formed in the third well region and has the first conductivity type.

According to an embodiment of the present invention, the resistive element has a first terminal coupled to a high voltage level and a second terminal coupled to a low voltage level, wherein the first doped region is Coupled to the high voltage level, the second doped region is coupled to a ground terminal.

According to another embodiment of the present invention, the semiconductor device further includes a third doped region. The third doped region is formed in the third well region, adjacent to the second doped region and has the second conductivity type, wherein the third doped region is coupled to the ground terminal, and the first The doped region, the second doped region and the third doped region form a parasitic bipolar transistor.

According to another embodiment of the present invention, the semiconductor device further includes a fourth doped region and a fifth doped region. The fourth doped region is formed in the second well region, adjacent to the first doped region, and has the first conductivity type. The fifth doped region is formed in the semiconductor substrate and has the second conductivity type.

According to an embodiment of the present invention, the fourth doped region is coupled to the high voltage level, and the fifth doped region is coupled to the ground terminal, wherein the fifth doped region and the third well The regions are separated from each other, and the first doped region, the fourth doped region, the second doped region and the fifth doped region form a parasitic silicon controlled rectifier.

The following is a detailed description of the semiconductor substrate, the semiconductor device and the manufacturing method of the semiconductor device according to some embodiments of the present disclosure. It should be understood that the following description provides many different embodiments or examples for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only used to briefly and clearly describe some embodiments of the present disclosure. Of course, these are only examples and not limitations of the present disclosure. Furthermore, repeated reference numbers or designations may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing some embodiments of the present disclosure and do not imply any correlation between the different embodiments and/or structures discussed. Furthermore, when it is mentioned that a first material layer is located on or above a second material layer, it includes the situation where the first material layer and the second material layer are in direct contact. Alternatively, one or more other material layers may be separated, in which case the first material layer and the second material layer may not be in direct contact.

In addition, relative terms, such as "lower" or "bottom" and "higher" or "top", may be used in the embodiments to describe the relative relationship of one element of the drawings to another element. It will be understood that if the device in the figures is turned upside down, elements described as being on the "lower" side would then be elements described as being on the "higher" side.

As used herein, the terms "about", "approximately" and "approximately" generally mean within 20%, preferably within 10%, and more preferably within 5%, or 3% of a given value or range. Within %, or within 2%, or within 1%, or within 0.5%. The quantities given here are approximate quantities, that is, in the absence of specific instructions of "about", "approximately", and "approximately", the meaning of "approximately", "approximately", and "approximately" can still be implied.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions , layers, and/or sections should not be limited by these terms, and these terms are only used to distinguish between different elements, components, regions, layers, and/or sections. Thus, a first element, component, region, layer, and/or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of some embodiments of the present disclosure. and/or part.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted to have meanings consistent with the relevant technology and the background or context of the present disclosure, and should not be interpreted in an idealized or overly formal manner. Interpretation, unless otherwise specifically defined in the embodiments of this disclosure.

Some embodiments of the present disclosure can be understood together with the drawings, and the drawings of the embodiments of the present disclosure are also regarded as part of the description of the embodiments of the present disclosure. It should be understood that the drawings of the embodiments of the present disclosure are not drawn to the scale of actual devices and components. The shapes and thicknesses of embodiments may be exaggerated in the drawings to clearly illustrate features of embodiments of the present disclosure. In addition, the structures and devices in the drawings are illustrated in a schematic manner in order to clearly demonstrate the features of the embodiments of the present disclosure.

In some embodiments of the present disclosure, relative terms such as “lower”, “upper”, “horizontal”, “vertical”, “below”, “above”, “top”, “bottom”, etc. shall be Understand the orientation shown in this paragraph and related figures. This relative terminology is only for convenience of explanation and does not mean that the device described needs to be manufactured or operated in a specific orientation. Terms related to joining and connecting, such as "connection" and "interconnection", unless otherwise defined, can mean that two structures are in direct contact, or they can also mean that two structures are not in direct contact, and there are other structures located there. between two structures. And the terms about joining and connecting can also include the situation where both structures are movable, or both structures are fixed.

Embodiments of the present invention disclose embodiments of semiconductor devices, and the above embodiments may be included in integrated circuits (ICs) such as microprocessors, memory devices, and/or other devices. The integrated circuits described above may also include different passive and active microelectronic components, such as thin-film resistors, other types of capacitors such as metal-insulator-metal capacitors (MIMCAP), inductors , Diodes, Metal-Oxide-Semiconductor field-effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (BJTs), lateral diffusion Type MOS transistors, high power MOS transistors or other types of transistors. Those skilled in the art will understand that semiconductor devices may also be used in integrated circuits that include other types of semiconductor elements.

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1 , the semiconductor device 100 includes a semiconductor substrate SUB, a first well region W1 , a second well region W2 , a field oxide layer FOX and a polycrystalline silicon layer PLY. The semiconductor substrate SUB has a first conductivity type. According to an embodiment of the present invention, the semiconductor substrate SUB is a silicon substrate. According to other embodiments of the present invention, the semiconductor substrate SUB may also be a lightly doped semiconductor substrate having the first conductivity type.

The first well region W1 is formed in the semiconductor substrate SUB and has a second conductivity type. According to an embodiment of the present invention, the first conductivity type is P type, and the second conductivity type is N type. According to an embodiment of the invention, the first well region W1 may be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the area of the predetermined first well region W1 to form the first well region W1.

The second well region W2 is formed in the first well region W1 and has the first conductivity type. According to an embodiment of the invention, the second well region W2 may be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the second well region W2 is intended to be formed to form the second well region W2. In this embodiment, the doping concentration of the second well region W2 is higher than the doping concentration of the semiconductor substrate SUB.

The field oxide layer FOX is formed over the first well area W1 and the second well area W2. The polycrystalline silicon layer PLY is formed over the field oxide layer FOX and the second well area W2, and is used to form the resistor element R. According to an embodiment of the present invention, the resistive element R is formed on the field oxide layer FOX and the second well region W2. According to another embodiment of the present invention, the resistive element R can be formed on the field oxide layer FOX, the first well region W1 and the second well region W2, wherein the width of the distribution on both sides of the resistive element R does not exceed the first well region W1 The width. As shown in Figure 1, the distribution width G of the resistive element R is less than or equal to the well width H of the first well region W1.

Figure 2 shows a top view of the polycrystalline silicon layer according to Figure 1 of the present invention. As shown in Figure 2, the resistive element 200 is a ring structure, including a pad PAD, a first node N1 and a second node N2, where the first node N1 in Figure 2 corresponds to the first node N1 in Figure 1 , the second node N2 in Figure 2 corresponds to the second node N2 in Figure 1. As shown in Figure 1, the first node N1 and the bonding pad PAD are coupled to the high voltage level VH, and the second node N2 is coupled to the low voltage level VL. According to some embodiments of the present invention, the low voltage level VL is a lower voltage level relative to the high voltage level VH. Therefore, the low voltage level VL can be the ground terminal GND or be between the high voltage level VH and The voltage between ground terminals GND.

Returning to FIG. 1 , the semiconductor device 100 further includes a third well region W3 and a doping region D. The third well region W3 is formed in the semiconductor substrate SUB and has the first conductivity type. According to an embodiment of the present invention, the third well region W3 may be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the third well region W3 is intended to be formed to form the third well region W3. In this embodiment, the doping concentration of the third well region W3 is higher than the doping concentration of the semiconductor substrate SUB.

The doped region D is formed in the third well region W3 and has the first conductivity type. According to an embodiment of the present invention, the doping concentration of the doping region D is higher than the doping concentration of the third well region W3. As shown in Figure 1, the doped region D is coupled to the ground terminal GND.

As shown in FIG. 1 , the semiconductor device 100 further includes a first top doped layer TOP1 and a second top doped layer TOP2. The first top doped layer TOP1 is formed in the first well region W1 and has the first conductivity type. The second top doped layer TOP2 is formed in the first well region W1 and has the first conductivity type. The first top doped layer TOP2 is formed in the first well region W1 and has the first conductivity type. The doped layer TOP1 and the second top doped layer TOP2 are located on both sides of the second well region W2 and are respectively separated from the second well region W2. According to an embodiment of the present invention, the doping concentration of the first top doped layer TOP1 and the second top doped layer TOP2 is lower than the doping concentration of the second well region W2.

According to an embodiment of the present invention, since the second well region W2 and the first well region W1 form the first parasitic diode DP1, the first well region W1 and the semiconductor substrate SUB form the second parasitic diode DP2, so that the high voltage The voltage across the level VH to the ground terminal GND is shared by the field oxide layer FOX, the first parasitic diode DP1 and the second parasitic diode DP2, thereby improving the withstand voltage of the resistive element R of the semiconductor device 100. According to an embodiment of the present invention, the first top doped layer TOP1 and the second top doped layer TOP2 are used to increase the lateral electric field endurance of the semiconductor device 100 .

FIG. 3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. As shown in FIG. 3 , the semiconductor device 300 includes a semiconductor substrate SUB, a first well region W1 , a second well region W2 , a first doped region D1 , a field oxide layer FOX and a polycrystalline silicon layer PLY. The semiconductor substrate SUB has a first conductivity type. According to an embodiment of the present invention, the semiconductor substrate SUB is a silicon substrate. According to other embodiments of the present invention, the semiconductor substrate SUB may also be a lightly doped semiconductor substrate having the first conductivity type.

The first well region W1 is formed in the semiconductor substrate SUB and has a second conductivity type. According to an embodiment of the present invention, the first conductivity type is P type, and the second conductivity type is N type. According to an embodiment of the invention, the first well region W1 may be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the area of the predetermined first well region W1 to form the first well region W1.

The second well region W2 is formed in the first well region W1 and has the second conductivity type. According to an embodiment of the invention, the second well region W2 may be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the area of the predetermined first well region W1 to form the second well region W2. In this embodiment, the doping concentration of the second well region W2 is higher than the doping concentration of the first well region W1.

The first doped region D1 is formed in the second well region W2 and has the second conductivity type. According to an embodiment of the invention, the first doped region D1 may be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the area of the predetermined first doped region D1 to form the first doped region D1. In this embodiment, the doping concentration of the first doping region D1 is higher than the doping concentration of the second well region W2.

The field oxide layer FOX is formed above the first well region W1 and the second well region W2 and surrounds the first doping region D1. The polycrystalline silicon layer PLY is formed on the field oxide layer FOX and is used to form a resistive element. R.

Figure 4 is a top view of the polycrystalline silicon layer according to Figure 3 of the present invention. As shown in Figure 4, the resistive element 400 is a ring structure, including a first node N1 and a second node N2. The first node N1 in Figure 4 corresponds to the first node N1 in Figure 3. Figure 4 The second node N2 corresponds to the second node N2 in Figure 3. As shown in FIG. 4 , the first doped region D1 is located at the center of the resistive element 400 . Comparing the resistor element 400 in Figure 4 with the resistor element 200 in Figure 2 , the first doping region D1 in Figure 4 is located at the position of the pad PAD in Figure 2 . As shown in FIG. 3 , the first node N1 and the first doped region D1 of the resistive element R are coupled to the high voltage level VH, and the second node N2 of the resistive element R is coupled to the low voltage level VL.

Returning to FIG. 3 , the semiconductor device 300 further includes a third well region W3 and a second doping region D2. The third well region W3 is formed in the semiconductor substrate SUB and has the first conductivity type. According to an embodiment of the present invention, the third well region W3 may be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the third well region W3 is intended to be formed to form the third well region W3. In this embodiment, the doping concentration of the third well region W3 is higher than the doping concentration of the semiconductor substrate SUB.

The second doped region D2 is formed in the third well region W3 and has the first conductivity type. According to an embodiment of the present invention, the doping concentration of the second doping region D2 is higher than the doping concentration of the third well region W3. As shown in Figure 3, the second doped region D2 is coupled to the ground terminal GND.

As shown in FIG. 3 , the semiconductor device 300 further includes a first top doped layer TOP1 and a second top doped layer TOP2. The first top doped layer TOP1 is formed in the first well region W1 and has the first conductivity type. The second top doped layer TOP2 is formed in the first well region W1 and has the first conductivity type. The first top doped layer TOP2 is formed in the first well region W1 and has the first conductivity type. The doped layer TOP1 and the second top doped layer TOP2 are located on both sides of the second well region W2 and are respectively separated from the second well region W2. According to an embodiment of the present invention, the doping concentration of the first top doped layer TOP1 and the second top doped layer TOP2 is lower than the doping concentration of the third well region W3 and higher than the doping concentration of the semiconductor substrate SUB. .

As shown in Figure 3, the width of the resistive element R distributed on the field oxide layer FOX is the first width X1, and the width of the first top doped region TOP1 or the second doped region TOP2 is the second width X2. The second width X2 is not less than the first width X1.

According to an embodiment of the present invention, the voltage across the high voltage level to the ground terminal GND is determined by the field oxide layer FOX, the first top doped region TOP1 (or the second top doped region TOP2), the first well region W1 and the semiconductor substrate SUB, thereby improving the withstand voltage of the semiconductor device 500 . According to an embodiment of the present invention, since the third parasitic diode DP3 is formed between the first well region W1 and the semiconductor substrate SUB, the third parasitic diode DP3 provides an electrostatic charge coupled to the first node N1 of the high voltage level VH. Exclusion path for charges.

In other words, when the first node N1 of the resistive element R is subjected to electrostatic discharge, since the first node N1 is coupled to the first doped region D1, electrostatic charges will be formed through the first well region W1 and the semiconductor substrate SUB. The third parasitic diode DP3 discharges the electrostatic charges to the ground terminal GND through the second doped region D2. According to an embodiment of the present invention, the first top doped layer TOP1 and the second top doped layer TOP2 are not only used to increase the vertical electric field endurance of the semiconductor device 300 , but also are used to increase the lateral electric field endurance of the semiconductor device 300 .

FIG. 5 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. Comparing the semiconductor device 500 in FIG. 5 with the semiconductor device 300 in FIG. 3 , the semiconductor device 500 further includes a third doping region D3.

The third doped region D3 is formed in the third well region W3 and is located between the first doped region D1 and the second doped region D2 and adjacent to the second doped region D2, and has a second conductive type. According to an embodiment of the present invention, the third doped region D3 may be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the area of the predetermined third doped region D3 to form the third doped region D3. In this embodiment, the doping concentration of the third doping region D3 is higher than the doping concentration of the second well region W2. As shown in Figure 5, the third doped region D3 is further coupled to the ground terminal GND.

According to an embodiment of the present invention, the voltage across the high voltage level to the ground terminal GND is determined by the field oxide layer FOX, the first top doped region TOP1 (or the second top doped region TOP2), the first well region W1 and the semiconductor substrate SUB, thereby improving the withstand voltage of the semiconductor device 500 . According to an embodiment of the present invention, the first doped region D1, the second doped region D2 and the third doped region D3 form a parasitic bipolar transistor NPN and the first node N1 is coupled to the first doped region D1, when the first node N1 of the resistive element R is subjected to electrostatic discharge, the parasitic bipolar transistor NPN is immediately turned on and the electrostatic charge is quickly discharged to the ground terminal GND. According to an embodiment of the present invention, the first top doped layer TOP1 and the second top doped layer TOP2 are not only used to increase the vertical electric field endurance of the semiconductor device 500 , but also are used to increase the lateral electric field endurance of the semiconductor device 500 .

FIG. 6 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. Comparing the semiconductor device 600 in FIG. 6 with the semiconductor device 300 in FIG. 3 , the semiconductor device 600 further includes a fourth doping region D4 and a fifth doping region D5.

The fourth doped region D4 is formed in the second well region W2, adjacent to the first doped region D1, and has the first conductivity type. According to an embodiment of the present invention, the fourth doped region D4 may be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the fourth doped region D4 is intended to be formed to form the fourth doped region D4.

The fifth doped region D5 is formed in the semiconductor substrate SUB and has the second conductivity type. According to an embodiment of the present invention, the fifth doped region D5 may be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the fifth doped region D5 is intended to be formed to form the fifth doped region D5. As shown in FIG. 6 , the fifth doping region D5 is coupled to the ground terminal GND and is separated from the third well region W3 .

According to an embodiment of the present invention, the first doped region D1, the fourth doped region D4, the second doped region D2 and the fifth doped region D5 form a parasitic silicon controlled rectifier (SCR). And the first node N1 is coupled to the first doped region D1 and the fourth doped region. When the first node N1 of the resistive element R is subjected to electrostatic discharge, the parasitic silicon controlled rectifier is turned on and the first node is discharged. The electrostatic charge received by N1 is discharged to the ground terminal GND.

The semiconductor device proposed by the present invention can not only increase the withstand voltage of the resistor element, but also provide a path to eliminate electrostatic charges, so that the polycrystalline silicon resistor can not only meet the needs of high-voltage applications, but also provide electrostatic discharge protection at one end of the polycrystalline silicon resistor, providing required protection features.

Although the embodiments and their advantages of the present disclosure have been disclosed above, it should be understood that anyone with ordinary skill in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the protection scope of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the relevant technical field can learn from some implementations of the present disclosure. It is understood that processes, machines, manufacturing, material compositions, devices, methods and steps currently or developed in the future can be based on the disclosure of the examples as long as they can perform substantially the same functions or obtain substantially the same results in the embodiments described herein. Some embodiments of the present disclosure use. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each claimed patent scope constitutes an individual embodiment, and the protection scope of the present disclosure also includes the combination of each claimed patent scope and embodiments.

100,300,500,600:Semiconductor devices 200,400: Resistor element SUB: semiconductor substrate W1: The first well area W2: The second well area W3: The third well area TOP1: The first top doped layer TOP2: The second top doped layer FOX: field oxide layer PLY: polycrystalline silicon layer R: Resistor element G: distribution width H: Well area width PAD: soldering pad N1: first node N2: second node VH: high voltage level VL: low voltage level GND: ground terminal D: doped area DP1: first parasitic diode DP2: Second parasitic diode DP3: The third parasitic diode D1: first doped region D2: Second doped region D3: The third doped region D4: The fourth doped region D5: The fifth doped region X1: first width X2: second width NPN: parasitic bipolar transistor

Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention; Figure 2 shows a top view of the polycrystalline silicon layer according to Figure 1 of the present invention; Figure 3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention; Figure 4 is a top view of the polycrystalline silicon layer according to Figure 3 of the present invention; Figure 5 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention; and FIG. 6 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

100:Semiconductor device

SUB: semiconductor substrate

W1: The first well area

W2: The second well area

W3: The third well area

TOP1: The first top doped layer

TOP2: The second top doped layer

FOX: field oxide layer

PLY: polycrystalline silicon layer

R: Resistor element

PAD: soldering pad

N1: first node

N2: second node

VH: high voltage level

VL: low voltage level

GND: ground terminal

D: doped area

DP1: first parasitic diode

DP2: Second parasitic diode

G: distribution width

H: Well area width

Claims (10)

A semiconductor device including: a semiconductor substrate having a first conductivity type; a first well region formed in the above-mentioned semiconductor substrate and having a second conductivity type; a second well area formed in the above-mentioned first well area and having the above-mentioned first conductivity type; An oxide layer is formed on the above-mentioned second well area; and A polycrystalline silicon layer is formed on the field oxide layer and forms a resistive element. The semiconductor device of claim 1 further includes: a first top doped layer formed in the first well region and having the first conductivity type; and a second top doped layer formed in the first well region and having the first conductivity type, wherein the first top doped layer and the second top doped layer are located on both sides of the second well region, And are separated from each other from the above-mentioned second well area. The semiconductor device of claim 1 further includes: a third well region formed in the above-mentioned semiconductor substrate and having the above-mentioned first conductivity type; and A doped region is formed in the third well region and has the first conductivity type, wherein the doped region is coupled to a ground terminal. A semiconductor device including: a semiconductor substrate having a first conductivity type; a first well region formed in the above-mentioned semiconductor substrate and having a second conductivity type; a second well region formed in the above-mentioned first well region and having the above-mentioned second conductivity type; a first doping region formed in the above-mentioned second well region and having the above-mentioned second conductivity type; a field oxide layer formed on the first well region and surrounding the first doping region; and A polycrystalline silicon layer is formed on the field oxide layer and forms a resistive element. For example, the semiconductor device of claim 4 further includes: a first top doped layer formed in the first well region and having the first conductivity type; and a second top doped layer formed in the first well region and having the first conductivity type, wherein the first top doped layer and the second top doped layer are located on both sides of the second well region, The resistive element is further formed on the first top doped layer and the second top doped layer. For example, the semiconductor device of claim 4 further includes: a third well region formed in the above-mentioned semiconductor substrate and having the above-mentioned first conductivity type; and A second doped region is formed in the third well region and has the first conductivity type. The semiconductor device of claim 6, wherein the resistive element has a first terminal coupled to a high voltage level and a second terminal coupled to a low voltage level, wherein the first doped region is coupled to the high voltage level, and the second doped region is coupled to a ground terminal. For example, the semiconductor device of claim 7 further includes: A third doped region, formed in the third well region, adjacent to the second doped region and having the second conductivity type, wherein the third doped region is coupled to the ground terminal, wherein the third doped region A doped region, the second doped region and the third doped region form a parasitic bipolar transistor. For example, the semiconductor device of claim 7 further includes: a fourth doped region formed in the second well region, adjacent to the first doped region and having the first conductivity type; and A fifth doped region is formed in the semiconductor substrate and has the second conductivity type. The semiconductor device of claim 9, wherein the fourth doped region is coupled to the high voltage level, the fifth doped region is coupled to the ground terminal, and the fifth doped region and the third The well regions are separated from each other, and the first doping region, the fourth doping region, the second doping region and the fifth doping region form a parasitic silicon controlled rectifier.

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