TWI707479B - High voltage semiconductor structure and method for fabricating the same - Google Patents

High voltage semiconductor structure and method for fabricating the same Download PDF

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TWI707479B
TWI707479B TW108131969A TW108131969A TWI707479B TW I707479 B TWI707479 B TW I707479B TW 108131969 A TW108131969 A TW 108131969A TW 108131969 A TW108131969 A TW 108131969A TW I707479 B TWI707479 B TW I707479B
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TW202111952A (en
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維克 韋
席德 內亞茲 依曼
陳柏安
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新唐科技股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

A high voltage semiconductor structure includes a substrate. The substrate has a first N-type well, a P-type isolation well, and a second N-type well as abutting and sequentially formed. A P-type heavily doped region is disposed at a surface portion of the P-type isolation well, wherein the P-type isolation well and the P-type heavily doped region together form a doped isolation structure. A first field oxide layer and a second field oxide layer are disposed on the substrate with contact to the P-type heavily doped region at two sides. A high voltage device is formed in the first N-type well. A peripheral device is formed in the second N-type well. The doped isolation structure isolates the high voltage device and the peripheral device. An N-type buried layer is disposed in the substrate at bottom of the first N-type well and a portion of the second N-type well.

Description

高電壓半導體結構及其製造方法High-voltage semiconductor structure and manufacturing method thereof

本發明是有關半導體製造技術，更是關於高電壓半導體結構。The present invention relates to semiconductor manufacturing technology, and more particularly to high-voltage semiconductor structures.

隨著電子產品的多樣功能，其控制電路需要能同時驅動操作在高電壓的高電壓元件以及操作在低電壓元件。因應高電壓元件以及低電壓元件的操作，其電源模組需要能提供高電壓電源以及低電壓電源。高電壓積體電路在電源模組的控制中扮演重要的角色。With the diverse functions of electronic products, its control circuit needs to be able to simultaneously drive high-voltage components operating at a high voltage and components operating at a low voltage. In response to the operation of high-voltage components and low-voltage components, the power supply module needs to be able to provide high-voltage power and low-voltage power. High-voltage integrated circuits play an important role in the control of power modules.

高電壓積體電路依照電源的需要，其會經常有由高電壓到低電壓的切換，或是由低電壓到高電壓的切換。高電壓積體電路中會包含高電壓驅動電路、低電壓驅動電路、電壓移位器、控制電路及電源選擇單元。High-voltage integrated circuits often switch from high voltage to low voltage or from low voltage to high voltage according to the needs of the power supply. The high-voltage integrated circuit will include a high-voltage drive circuit, a low-voltage drive circuit, a voltage shifter, a control circuit, and a power selection unit.

高電壓積體電路的作用例如是閘極驅動器，例如用來推動功率半導體場效電晶體(MOSFET)或絕緣閘雙極性電晶體(IGBT)。高電壓積體電路一般包括上橋電路(High-Side circuit)與下橋電路 (Low-Side circuit)，上橋電路其是屬於高電壓驅動元件。下橋電路是屬於低電壓驅動元件，如此在高電壓積體電路的半導體結構中，在上橋電路與下橋電路之間會包含相同導電型的元件，其可能操作在高電壓範圍或是低電壓範圍。元件之間需要適當隔離以防止電壓崩潰，而其同時也要減少隔離結構的漏電程度。The function of the high-voltage integrated circuit is, for example, a gate driver, such as a power semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). The high-voltage integrated circuit generally includes a high-side circuit and a low-side circuit, and the high-side circuit is a high-voltage driving element. The lower-bridge circuit is a low-voltage drive element, so in the semiconductor structure of the high-voltage integrated circuit, the same conductivity type element is included between the upper bridge circuit and the lower bridge circuit, which may operate in a high voltage range or a low voltage range. voltage range. The components need to be properly isolated to prevent voltage collapse, and at the same time to reduce the leakage of the isolation structure.

在高電壓積體電路的半導體結構中，如何在高電壓操作區域上的元件之間達到有效隔離，在研發中是所要考慮的課題其一。In the semiconductor structure of the high-voltage integrated circuit, how to achieve effective isolation between the components on the high-voltage operating area is one of the topics to be considered in the research and development.

本發明提供一種在高電壓積體電路的半導體結構中，對於N導電型的高電壓元件與低電壓元件之間的隔離，可以提高崩潰電壓，且可以抑制隔離結構的漏電流。The present invention provides a semiconductor structure of a high-voltage integrated circuit, which can increase the breakdown voltage and suppress the leakage current of the isolation structure for the isolation between the N-conductivity type high-voltage element and the low-voltage element.

於一實施例，本發明提供一種高電壓半導體結構包括一基底，該基底有依序相鄰的第一N型井區、P型隔離井區及第二N型井區。P型重摻雜區設置在該P型隔離井區的表層，其中該P型隔離井區與該P型重摻雜區構成摻雜隔離結構。第一場氧化層與第二場氧化層設置在該基底的表層與該P型重摻雜區接觸且位於兩側。高電壓元件形成在該第一N型井區中。外圍元件形成在該第二N型井區中，其中該摻雜隔離結構隔離該高電壓元件與該外圍元件。N型埋入層在該基底中，位於該第一N型井區與該第二N型井區的部分的底部。In one embodiment, the present invention provides a high-voltage semiconductor structure including a substrate having a first N-type well region, a P-type isolation well region, and a second N-type well region that are sequentially adjacent to each other. The P-type heavily doped region is arranged on the surface of the P-type isolation well region, wherein the P-type isolation well region and the P-type heavily doped region form a doped isolation structure. The first field oxide layer and the second field oxide layer are arranged on the surface of the substrate in contact with the P-type heavily doped region and are located on both sides. A high voltage element is formed in the first N-type well region. The peripheral element is formed in the second N-type well region, wherein the doped isolation structure isolates the high voltage element from the peripheral element. The N-type buried layer is in the substrate and is located at the bottom of the first N-type well region and the second N-type well region.

於一實施例，對於所述的高電壓半導體結構，該基底是矽晶圓，或是包含矽晶圓以及在該矽晶圓上的磊晶層，其中該第一N型井區、該P型隔離井區及該第二N型井區是形成在該磊晶層中。In one embodiment, for the high-voltage semiconductor structure, the substrate is a silicon wafer, or includes a silicon wafer and an epitaxial layer on the silicon wafer, wherein the first N-well region, the P The type isolation well region and the second N type well region are formed in the epitaxial layer.

於一實施例，對於所述的高電壓半導體結構，該P型重摻雜區的上表面沒有場氧化物。In one embodiment, for the high-voltage semiconductor structure, there is no field oxide on the upper surface of the P-type heavily doped region.

於一實施例，對於所述的高電壓半導體結構，該高電壓元件包括高電壓終端結構以及高電壓驅動元件，其中該高電壓驅動元件形成在該第一N型井區中，且該高電壓終端結構圍繞該高電壓驅動元件。In one embodiment, for the high-voltage semiconductor structure, the high-voltage element includes a high-voltage terminal structure and a high-voltage driving element, wherein the high-voltage driving element is formed in the first N-type well region, and the high-voltage The terminal structure surrounds the high voltage drive element.

於一實施例，對於所述的高電壓半導體結構，該外圍元件包含電壓移位器。In one embodiment, for the high-voltage semiconductor structure, the peripheral component includes a voltage shifter.

於一實施例，對於所述的高電壓半導體結構，其更包括:第一N型重摻雜區，在該第一N型井區的表層;第二N型重摻雜區，在該第二N型井區的表層;內層介電層，覆蓋過該基底;以及內連線結構，在該內層介電層中，連接該第一N型重摻雜區與該第二N型重摻雜區。In one embodiment, for the high-voltage semiconductor structure, it further includes: a first N-type heavily doped region on the surface of the first N-type well region; and a second N-type heavily doped region on the first N-type well region. The surface layer of the two N-type well regions; the inner dielectric layer covering the substrate; and the interconnection structure, in the inner dielectric layer, connecting the first N-type heavily doped region and the second N-type Heavy doped area.

於一實施例，對於所述的高電壓半導體結構，該第一N型重摻雜區是設於高電壓驅動元件結構上，該第二N型重摻雜區是N型電晶體的汲極。In one embodiment, for the high-voltage semiconductor structure, the first N-type heavily doped region is provided on the high-voltage drive device structure, and the second N-type heavily doped region is the drain of the N-type transistor .

於一實施例，本發明也提供一種製造高電壓半導體結構的方法，包括提供一基底。形成N型埋入層在該基底中。依序形成相鄰的第一N型井區、P型隔離井區及第二N型井區在該基底中，其中該N型埋入層位於該第一N型井區與該第二N型井區的部分的底部。形成P型重摻雜區在該P型隔離井區的表層，其中該P型隔離井區與該P型重摻雜區構成摻雜隔離結構。形成第一場氧化層與第二場氧化層在該基底的表層，與該P型重摻雜區接觸且位於兩側。形成高電壓元件在該第一N型井區中。形成外圍元件在該第二N型井區中，其中該摻雜隔離結構隔離該高電壓元件與該外圍元件。In one embodiment, the present invention also provides a method of manufacturing a high-voltage semiconductor structure, including providing a substrate. An N-type buried layer is formed in the substrate. A first N-type well region, a P-type isolation well region, and a second N-type well region are sequentially formed in the substrate, wherein the N-type buried layer is located between the first N-type well region and the second N-type well region. The bottom part of the well area. A P-type heavily doped region is formed on the surface of the P-type isolation well region, wherein the P-type isolation well region and the P-type heavily doped region form a doped isolation structure. A first field oxide layer and a second field oxide layer are formed on the surface of the substrate, in contact with the P-type heavily doped region and located on both sides. A high voltage element is formed in the first N-type well region. A peripheral element is formed in the second N-type well region, wherein the doped isolation structure isolates the high-voltage element from the peripheral element.

於一實施例，對於所述的製造高電壓半導體結構的方法，該P型重摻雜區的上表面沒有場氧化物。In one embodiment, for the method of manufacturing a high-voltage semiconductor structure, there is no field oxide on the upper surface of the P-type heavily doped region.

於一實施例，對於所述的製造高電壓半導體結構的方法，形成該高電壓元件的該步驟包括形成高電壓驅動元件在該第一N型井區中以及形成高電壓終端結構圍繞該高電壓驅動元件。In one embodiment, for the method of manufacturing a high-voltage semiconductor structure, the step of forming the high-voltage element includes forming a high-voltage driving element in the first N-type well region and forming a high-voltage terminal structure around the high-voltage Drive components.

於一實施例，對於所述的製造高電壓半導體結構的方法，形成該外圍元件的該步驟包括:形成電壓移位器在該第二N型井區中。In one embodiment, for the method of manufacturing a high-voltage semiconductor structure, the step of forming the peripheral element includes forming a voltage shifter in the second N-type well region.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

本發明是關於高電壓積體電路的設計，其中本發明提出隔離結構在高電壓N型元件以及其外圍的N型元件之間達到隔離效果，可以提高高電壓元件的崩潰電壓以及減少隔離結構的漏電流。The present invention relates to the design of high-voltage integrated circuits. Among them, the present invention proposes an isolation structure to achieve isolation between high-voltage N-type components and its peripheral N-type components, which can increase the breakdown voltage of high-voltage components and reduce the isolation structure. Leakage current.

以下舉一些實施例來說明本發明，但是本發明不限於所舉的實施例。Some examples are given below to illustrate the present invention, but the present invention is not limited to the examples.

在提出本發明的技術之前，本發明對所要處理的高電壓積體電路進行探究，以期能發現與瞭解其操作上可以提升之處，以利於能提出有效的解決方案。Before proposing the technology of the present invention, the present invention explores the high-voltage integrated circuit to be processed, in order to discover and understand the improvement in its operation, so as to be able to propose effective solutions.

圖1是依照本發明的一實施例，高電壓積體電路的基本架構示意圖。參閱圖1，此高電壓積體電路50是在實際應用上的基本架構。高電壓積體電路50會控制高電壓源單元，以提供輸出電壓。高電壓源單元連接在高電壓源HV與接地電壓之間，例如是由高電壓端選擇器60及低電壓端選擇器62串接所構成。FIG. 1 is a schematic diagram of the basic structure of a high-voltage integrated circuit according to an embodiment of the present invention. Referring to FIG. 1, the high-voltage integrated circuit 50 is a basic structure in practical application. The high-voltage integrated circuit 50 controls the high-voltage source unit to provide an output voltage. The high-voltage source unit is connected between the high-voltage source HV and the ground voltage, and is formed by, for example, a high-voltage terminal selector 60 and a low-voltage terminal selector 62 connected in series.

在高電壓積體電路50中包含高電壓驅動電路(HV)52、低電壓驅動電路(LV)54、電壓移位器56及控制電路58。控制電路58電路通過電壓移位單元56對高電壓驅動電路(HV)52控制，可以控制高電壓端選擇器60的導通與斷開。The high voltage integrated circuit 50 includes a high voltage drive circuit (HV) 52, a low voltage drive circuit (LV) 54, a voltage shifter 56, and a control circuit 58. The control circuit 58 controls the high voltage drive circuit (HV) 52 through the voltage shift unit 56 to control the on and off of the high voltage terminal selector 60.

高電壓驅動電路(HV)52也是上橋電路，其操作高電壓。高電壓驅動電路52例如包括高電壓電晶體。為了要隔離上橋電路的高電壓，一般還會設置高電壓終端(High Voltage Junction Termination，HVJT) 結構53，環繞高電壓驅動電路52以終止高電壓。另外在高電壓驅動電路52的外圍是低電壓驅動電路54、電壓移位器56等元件，其例如包含低電壓電晶體或是在電壓移位器56中的高電壓電晶體。The high voltage drive circuit (HV) 52 is also an upper bridge circuit, which operates at a high voltage. The high-voltage driving circuit 52 includes, for example, a high-voltage transistor. In order to isolate the high voltage of the upper bridge circuit, a High Voltage Junction Termination (HVJT) structure 53 is generally provided to surround the high voltage driving circuit 52 to terminate the high voltage. In addition, at the periphery of the high-voltage driving circuit 52 are components such as a low-voltage driving circuit 54 and a voltage shifter 56, which include, for example, a low-voltage transistor or a high-voltage transistor in the voltage shifter 56.

要進一步隔離高電壓驅動電路52，一般會利用在基底中在相同導電型的元件之間增加不同導電型摻雜區域來隔離。To further isolate the high-voltage driving circuit 52, generally, doped regions of different conductivity types are added between the elements of the same conductivity type in the substrate for isolation.

參閱圖2，習知技術對於高電壓半導體元件的之製造，其例如會在矽晶圓基板100上先形成磊晶層101。磊晶層101用以形成高電壓元件所需要的多種摻雜區。因此，矽的基板100與磊晶層101構成基底。然而於一實施例，基底也是可以指矽晶圓基板100，而所需要的多種摻雜區直接形成在基板100中。本發明的基底可以是基板100或是基板100與磊晶層101的整合。Referring to FIG. 2, for the manufacture of high-voltage semiconductor devices in the prior art, for example, an epitaxial layer 101 is formed on a silicon wafer substrate 100 first. The epitaxial layer 101 is used to form various doped regions required by high-voltage devices. Therefore, the silicon substrate 100 and the epitaxial layer 101 constitute a base. However, in one embodiment, the base may also refer to the silicon wafer substrate 100, and the required multiple doped regions are directly formed in the substrate 100. The base of the present invention may be the substrate 100 or the integration of the substrate 100 and the epitaxial layer 101.

在基板100上會因應高電壓元件形成N型埋入層102，其例如是在磊晶層101的底部，即是在基板100與磊晶層101之間。在磊晶層101中會對應所要形成的各種元件10、12、14、16、18、20而形成對應的摻雜區域。這些元件例如是高電壓橫向擴散金屬氧化物半導體元件(HV LDMOS) 10、高電壓內連線12、電阻器14、N型電晶體(NMOS)16、P型電晶體(PMOS)18及NPN電晶體20等，其中場效電晶體還包括閘極(G)、源極(S)及汲極(D)。另外，在磊晶層101的表層也會形成場氧化層112來隔離元件。An N-type buried layer 102 is formed on the substrate 100 in response to high-voltage components, which is, for example, at the bottom of the epitaxial layer 101, that is, between the substrate 100 and the epitaxial layer 101. Corresponding doped regions are formed in the epitaxial layer 101 corresponding to the various elements 10, 12, 14, 16, 18, and 20 to be formed. These elements are, for example, high-voltage laterally diffused metal oxide semiconductor elements (HV LDMOS) 10, high-voltage interconnects 12, resistors 14, N-type transistors (NMOS) 16, P-type transistors (PMOS) 18, and NPN devices. The crystal 20, etc., wherein the field effect transistor also includes a gate (G), a source (S), and a drain (D). In addition, a field oxide layer 112 is also formed on the surface of the epitaxial layer 101 to isolate the devices.

習知高電壓半導體結構的高電壓元件之間的隔離方式。對於較直接的隔離方式，其在磊晶層101中是採用P型摻雜隔離結構(p-iso)22。這些P型摻雜隔離結構22是形成在場氧化層112的下方。此結構存在一些可能的問題，敘述如後。The isolation method between the high-voltage components of the high-voltage semiconductor structure is known. For a more direct isolation method, a P-type doped isolation structure (p-iso) 22 is used in the epitaxial layer 101. These P-type doped isolation structures 22 are formed under the field oxide layer 112. There are some possible problems with this structure, as described below.

圖3是習知的高電壓積體電路的半導體剖面結構示意圖。參閱圖3，取半導體剖面結構關於P型摻雜隔離結構的部分來探究。在基板100上的磊晶層101中形成有N型摻雜區域104與N型摻雜區域106。此N型摻雜區域104與N型摻雜區域106被P型隔離井區108(p-iso)隔離。在磊晶層101的表層且位於N型摻雜區域104與N型摻雜區域106及P型隔離井區108的上方也形成有場氧化層112。場氧化層112也是隔離結構，位於兩個N型重摻雜區域(N+)114之間。3 is a schematic diagram of a semiconductor cross-sectional structure of a conventional high-voltage integrated circuit. Referring to FIG. 3, take the part of the semiconductor cross-sectional structure about the P-type doped isolation structure to explore. An N-type doped region 104 and an N-type doped region 106 are formed in the epitaxial layer 101 on the substrate 100. The N-type doped region 104 and the N-type doped region 106 are separated by a P-type isolation well 108 (p-iso). A field oxide layer 112 is also formed on the surface layer of the epitaxial layer 101 and located above the N-type doped region 104 and the N-type doped region 106 and the P-type isolation well region 108. The field oxide layer 112 is also an isolation structure and is located between two N-type heavily doped regions (N+) 114.

在圖3的P型隔離井區108當作摻雜隔離結構，其是直接形成在場氧化層112下方，與場氧化層112接觸。由於P型隔離井區108是摻雜P型摻質，例如是硼元素，其會於場氧化層112界面產生硼分離(Boron segregation)的現象，介面處的硼濃度降低，P型隔離井區108與氧化層112的界面由於硼分離的現象而形成漂移區域110。在漂移區域110會有由N型摻雜區域104的高電壓元件對N型摻雜區域106的外圍元件產生漏電流。另外在高電壓操作時，崩潰電壓有需要考慮。加大P型隔離井區108的長度可以提高崩潰電壓，防止元件損壞。然而由於在漂移區域110有漏電流的現象，加大P型隔離井區108的長度無法有效抑制漏電流。也就是說，在圖3的結構下，漏電流與崩潰電壓是相互增減，其一者的提升，另一者的將降低。The P-type isolation well region 108 in FIG. 3 is used as a doped isolation structure, which is formed directly under the field oxide layer 112 and is in contact with the field oxide layer 112. Since the P-type isolation well region 108 is doped with P-type dopants, such as boron, it will produce Boron segregation at the interface of the field oxide layer 112, and the boron concentration at the interface will decrease. The interface between 108 and the oxide layer 112 forms a drift region 110 due to the phenomenon of boron separation. In the drift region 110, the high-voltage components of the N-type doped region 104 may cause leakage current to the peripheral components of the N-type doped region 106. In addition, when operating at high voltage, the breakdown voltage needs to be considered. Increasing the length of the P-type isolation well region 108 can increase the breakdown voltage and prevent component damage. However, due to the leakage current phenomenon in the drift region 110, increasing the length of the P-type isolation well region 108 cannot effectively suppress the leakage current. That is to say, under the structure of FIG. 3, the leakage current and the breakdown voltage increase and decrease each other, and the increase of one, the decrease of the other.

本發明至少觀察到前述的現象後，進一步提出摻雜隔離結構的改良。圖4是依照本發明的一實施例，高電壓積體電路的半導體剖面結構示意圖。以下參閱圖4。After observing at least the aforementioned phenomenon, the present invention further proposes the improvement of the doped isolation structure. 4 is a schematic diagram of a cross-sectional structure of a semiconductor of a high-voltage integrated circuit according to an embodiment of the present invention. Refer to Figure 4 below.

於一實施例，在基底的表層例如在磊晶層101的表層所形成分離的場氧化層122與場氧化層124。場氧化層122在N型摻雜區域106上方。N型摻雜區域106所形成的元件是外圍元件例如包括電壓移位器的電晶體等。在N型摻雜區域106上的重摻雜區域114例如是電晶體的汲極。於一實施例，在N型摻雜區域104所形成的元件是高電壓元件，例如包括高電壓驅動元件(例如圖1的高電壓驅動電路52)或是高電壓終端結構(HVJT)圍繞高電壓驅動元件。本發明在N型摻雜區域104與 N型摻雜區域106中對應所形成的元件不限於所舉的實施例。In one embodiment, a separate field oxide layer 122 and a field oxide layer 124 are formed on the surface layer of the substrate, for example, on the surface layer of the epitaxial layer 101. The field oxide layer 122 is above the N-type doped region 106. The elements formed by the N-type doped region 106 are peripheral elements such as a transistor including a voltage shifter. The heavily doped region 114 on the N-type doped region 106 is, for example, the drain of the transistor. In one embodiment, the element formed in the N-type doped region 104 is a high-voltage element, for example, including a high-voltage driving element (such as the high-voltage driving circuit 52 in FIG. 1) or a high-voltage terminal structure (HVJT) surrounding the high-voltage Drive components. In the present invention, the corresponding elements formed in the N-type doped region 104 and the N-type doped region 106 are not limited to the illustrated embodiments.

本發明在P型隔離井區108的表層，於場氧化層122與場氧化層124之間形成P型重摻雜區 (P+)120，在P型重摻雜區 (P+)120上方沒有形成場氧化層。由於P型重摻雜區120的P型摻濃度可以有效提升，有效減少產生摻質對場氧化層在介面處的硼分離產生，而造成隔離區表面漏電流的現象。In the present invention, a P-type heavily doped region (P+) 120 is formed between the field oxide layer 122 and the field oxide layer 124 on the surface layer of the P-type isolation well region 108, and no P-type heavily doped region (P+) 120 is formed above Field oxide layer. Since the P-type doping concentration of the P-type heavily doped region 120 can be effectively increased, it effectively reduces the occurrence of dopant separation of boron at the interface of the field oxide layer, which causes leakage current on the surface of the isolation region.

圖5是依照本發明的一實施例，沿著隔離結構的摻雜濃度示意圖。參閱圖5，本發明從研究的數據顯示，沿著P型隔離井區108橫向方向的X軸的濃度分佈示意圖來看，點線是沒有P型重摻雜區120的濃度分佈，其大致上維持相同的濃度。於此，縱軸的濃度值刻度是取對數LOG的相對示意值，而不是實際需要的濃度值。實線是加入P型重摻雜區120的結構，從定性的現象來分析，在中間點(X=0)的摻質濃度最大。P型重摻雜區120的加入可以有效達到隔離效果，且能避免與場氧化層122與場氧化層124產生表面漏電流。FIG. 5 is a schematic diagram of the doping concentration along the isolation structure according to an embodiment of the present invention. Referring to FIG. 5, the present invention shows from the research data that the concentration distribution along the X axis in the lateral direction of the P-type isolation well region 108 shows that the dotted line is the concentration distribution without the P-type heavily doped region 120, which is roughly Maintain the same concentration. Here, the concentration value scale on the vertical axis is the relative schematic value of the logarithm LOG, not the actual concentration value. The solid line is the structure where the P-type heavily doped region 120 is added. From the qualitative analysis, the dopant concentration is the largest at the intermediate point (X=0). The addition of the P-type heavily doped region 120 can effectively achieve the isolation effect, and can avoid surface leakage current with the field oxide layer 122 and the field oxide layer 124.

再度參閱圖4，完成在基底的磊晶層101的多種摻雜結構以及其上的電壓元件後，內層介電層116後續形成而覆蓋磊晶層101的表面結構。其後內連線結構118，也在內層介電層116中形成，達成電路的連接路徑。本發明不限於後續的製程。Referring again to FIG. 4, after the various doping structures of the epitaxial layer 101 of the substrate and the voltage components thereon are completed, an inner dielectric layer 116 is subsequently formed to cover the surface structure of the epitaxial layer 101. After that, the interconnection structure 118 is also formed in the inner dielectric layer 116 to achieve a circuit connection path. The present invention is not limited to the subsequent manufacturing process.

本發明再從半導體製造的方法來看，於一實施例，製造方法包括提供一基板100。基板100於一實施例也可以包含磊晶層101的基板。形成N型埋入層102在基板100(101)中。依序形成相鄰的第一N型井區104、P型隔離井區108及第二N型井區106在基板100(101)中，其中該N型埋入層102位於該第一N型井區104與該部分第二N型井區106的底部。形成P型重摻雜區120在該P型隔離井區108的表層，其中該P型隔離井區108與該P型重摻雜區120構成摻雜隔離結構。形成第一場氧化層124與第二場氧化層122在該基底的表層，與該P型重摻雜區120接觸且位於兩側。形成高電壓驅動元件在該第一N型井區104中。形成外圍元件在該第二N型井區106中，其中該摻雜隔離結構108、120隔離該高電壓驅動元件與該外圍元件。From the perspective of the semiconductor manufacturing method, in one embodiment, the manufacturing method includes providing a substrate 100. The substrate 100 may also include a substrate of an epitaxial layer 101 in an embodiment. An N-type buried layer 102 is formed in the substrate 100 (101). A first N-type well region 104, a P-type isolation well region 108, and a second N-type well region 106 are sequentially formed in the substrate 100 (101), wherein the N-type buried layer 102 is located in the first N-type well region. The bottom of the well area 104 and the part of the second N-type well area 106. A P-type heavily doped region 120 is formed on the surface of the P-type isolation well region 108, wherein the P-type isolation well region 108 and the P-type heavily doped region 120 form a doped isolation structure. A first field oxide layer 124 and a second field oxide layer 122 are formed on the surface of the substrate, in contact with the P-type heavily doped region 120 and located on both sides. A high voltage driving element is formed in the first N-type well region 104. A peripheral element is formed in the second N-type well region 106, wherein the doped isolation structure 108, 120 isolates the high voltage driving element from the peripheral element.

於一實施例，對於所述的製造高電壓半導體結構的方法，該P型重摻雜區的上表面沒有場氧化物。In one embodiment, for the method of manufacturing a high-voltage semiconductor structure, there is no field oxide on the upper surface of the P-type heavily doped region.

於一實施例，對於所述的製造高電壓半導體結構的方法，形成該高電壓元件的該步驟包括形成高電壓驅動元件在該第一N型井區中，以及形成高電壓終端結構圍繞該高電壓驅動元件。In one embodiment, for the method of manufacturing a high-voltage semiconductor structure, the step of forming the high-voltage element includes forming a high-voltage driving element in the first N-type well region, and forming a high-voltage terminal structure around the high-voltage terminal structure. Voltage drive components.

於一實施例，對於所述的製造高電壓半導體結構的方法，形成該外圍元件的該步驟包括:形成電壓移位器在該第二N型井區中。In one embodiment, for the method of manufacturing a high-voltage semiconductor structure, the step of forming the peripheral element includes forming a voltage shifter in the second N-type well region.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10:橫向擴散金屬氧化物半導體元件 12:高電壓內連線 14:電阻器 16:N型電晶體 18:P型電晶體 20:NPN電晶體 22:P型摻雜隔離結構 50:高電壓積體電路 52:高電壓驅動電路 53:高電壓終端結構 54:低電壓驅動電路 56:電壓移位器 58:控制電路 60:高電壓端選擇器 62:低電壓端選擇器 100:基板 101:磊晶層 102:N型埋入層 104:第一N型井區 106:第二N型井區 108:P型隔離井區 110:漂移區域 112:場氧化層 114:N型重摻雜區域 116:內層介電層 118:內連線結構 120:P型重摻雜區 122、124:場氧10: Lateral diffusion metal oxide semiconductor components 12: High voltage internal wiring 14: resistor 16: N-type transistor 18: P-type transistor 20: NPN transistor 22: P-type doped isolation structure 50: High voltage integrated circuit 52: High voltage drive circuit 53: High voltage terminal structure 54: Low voltage drive circuit 56: Voltage shifter 58: control circuit 60: High voltage terminal selector 62: Low voltage side selector 100: substrate 101: epitaxial layer 102: N-type buried layer 104: The first N-type well area 106: The second N-type well area 108: P-type isolation well area 110: drift area 112: Field Oxide 114: N-type heavily doped region 116: inner dielectric layer 118: Internal connection structure 120: P-type heavily doped region 122, 124: field oxygen

圖1是依照本發明的一實施例，高電壓積體電路的基本架構示意圖。 圖2是習知高電壓積體電路的半導體剖面結構示意圖。 圖3是習知高電壓積體電路的半導體剖面結構示意圖。 圖4是依照本發明的一實施例，高電壓積體電路的半導體剖面結構示意圖。 圖5是依照本發明的一實施例，沿著隔離結構的摻雜濃度示意圖。 FIG. 1 is a schematic diagram of the basic structure of a high-voltage integrated circuit according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a semiconductor cross-sectional structure of a conventional high-voltage integrated circuit. FIG. 3 is a schematic diagram of a semiconductor cross-sectional structure of a conventional high-voltage integrated circuit. 4 is a schematic diagram of a cross-sectional structure of a semiconductor of a high-voltage integrated circuit according to an embodiment of the present invention. FIG. 5 is a schematic diagram of the doping concentration along the isolation structure according to an embodiment of the present invention.

100:基板 100: substrate

101:磊晶層 101: epitaxial layer

102:N型埋入層 102: N-type buried layer

104、106:N型摻雜區域 104, 106: N-type doped area

108:P型隔離井區 108: P-type isolation well area

114:N型重摻雜區域 114: N-type heavily doped region

116:內層介電層 116: inner dielectric layer

118:內連線結構 118: Internal connection structure

120:P型重摻雜區 120: P-type heavily doped region

122、124:場氧化層 122, 124: field oxide layer

Claims (11)

一種高電壓半導體結構，包括： 一基底，有依序相鄰的第一N型井區、P型隔離井區及第二N型井區; P型重摻雜區，在該P型隔離井區的表層，其中該P型隔離井區與該P型重摻雜區構成摻雜隔離結構； 第一場氧化層與第二場氧化層，在該基底的表層與該P型重摻雜區接觸且位於兩側; 高電壓元件，形成在該第一N型井區中; 外圍元件，形成在該第二N型井區中，其中該摻雜隔離結構隔離該高電壓元件與該外圍元件; 以及 N型埋入層，在該基底中，位於該第一N型井區與該第二N型井區的部分的底部。 A high-voltage semiconductor structure, including: A substrate, there are sequentially adjacent first N-type well area, P-type isolation well area and second N-type well area; P-type heavily doped region, on the surface of the P-type isolation well region, wherein the P-type isolation well region and the P-type heavily doped region form a doped isolation structure; The first field oxide layer and the second field oxide layer are in contact with the P-type heavily doped region on the surface of the substrate and are located on both sides; The high-voltage element is formed in the first N-type well region; A peripheral element is formed in the second N-type well region, wherein the doped isolation structure isolates the high-voltage element from the peripheral element; and The N-type buried layer is located at the bottom of the first N-type well region and the second N-type well region in the substrate. 如申請專利範圍第1項所述的高電壓半導體結構，其中該基底是矽晶圓，或是包含矽晶圓以及在該矽晶圓上的磊晶層，其中該第一N型井區、該P型隔離井區及該第二N型井區是形成在該磊晶層中。The high-voltage semiconductor structure described in the first item of the patent application, wherein the substrate is a silicon wafer, or includes a silicon wafer and an epitaxial layer on the silicon wafer, wherein the first N-type well region, The P-type isolation well region and the second N-type well region are formed in the epitaxial layer. 如申請專利範圍第1項所述的高電壓半導體結構，其中該P型重摻雜區的上表面沒有場氧化物。In the high-voltage semiconductor structure described in item 1 of the scope of patent application, there is no field oxide on the upper surface of the P-type heavily doped region. 如申請專利範圍第1項所述的高電壓半導體結構，其中該高電壓半導體結構包括一高電壓驅動元件與一高電壓終端結構，其中該高電壓驅動元件設於該第一N型井區中以及該高電壓終端結構圍繞該高電壓驅動元件。The high-voltage semiconductor structure according to claim 1, wherein the high-voltage semiconductor structure includes a high-voltage driving element and a high-voltage terminal structure, wherein the high-voltage driving element is disposed in the first N-type well region And the high voltage terminal structure surrounds the high voltage driving element. 如申請專利範圍第1項所述的高電壓半導體結構，其中該外圍元件包含電壓移位器。The high-voltage semiconductor structure according to the first item of the scope of patent application, wherein the peripheral element includes a voltage shifter. 如申請專利範圍第1項所述的高電壓半導體結構，更包括: 第一N型重摻雜區，在該第一N型井區的表層; 第二N型重摻雜區，在該第二N型井區的表層; 內層介電層，覆蓋過該基底; 以及 內連線結構，在該內層介電層中，接該第一N型重摻雜區與該第二N型重摻雜區。 The high-voltage semiconductor structure described in item 1 of the scope of patent application includes: The first N-type heavily doped region, in the surface layer of the first N-type well region; The second N-type heavily doped region, in the surface layer of the second N-type well region; An inner dielectric layer covering the substrate; and The interconnect structure connects the first N-type heavily doped region and the second N-type heavily doped region in the inner dielectric layer. 如申請專利範圍第6項所述的高電壓半導體結構，其中該第一N型重摻雜區是在高電壓驅動元件上，該第二N型重摻雜區是N型電晶體的汲極。The high-voltage semiconductor structure described in item 6 of the scope of patent application, wherein the first N-type heavily doped region is on the high-voltage drive element, and the second N-type heavily doped region is the drain of the N-type transistor . 一種製造高電壓半導體結構的方法，包括： 提供一基底; 形成N型埋入層，在該基底中; 依序形成相鄰的第一N型井區、P型隔離井區及第二N型井區在該基底中，其中該N型埋入層位於該第一N型井區與該第二N型井區的部分的底部; 形成P型重摻雜區在該P型隔離井區的表層，其中該P型隔離井區與該P型重摻雜區構成摻雜隔離結構； 形成第一場氧化層與第二場氧化層，在該基底的表層與該P型重摻雜區接觸且位於兩側; 形成高電壓元件在該第一N型井區中;以及 形成外圍元件在該第二N型井區中，其中該摻雜隔離結構隔離該高電壓元件與該外圍元件。 A method of manufacturing a high-voltage semiconductor structure includes: Provide a base; Form an N-type buried layer in the substrate; A first N-type well region, a P-type isolation well region, and a second N-type well region are sequentially formed in the substrate, wherein the N-type buried layer is located between the first N-type well region and the second N-type well region. The bottom of the part of the well area; Forming a P-type heavily doped region on the surface of the P-type isolation well region, wherein the P-type isolation well region and the P-type heavily doped region form a doped isolation structure; A first field oxide layer and a second field oxide layer are formed, and the surface layer of the substrate is in contact with the P-type heavily doped region and is located on both sides; Forming a high-voltage element in the first N-type well region; and A peripheral element is formed in the second N-type well region, wherein the doped isolation structure isolates the high-voltage element from the peripheral element. 如申請專利範圍第8項所述的製造高電壓半導體結構的方法，其中該P型重摻雜區的上表面沒有場氧化物。According to the method for manufacturing a high-voltage semiconductor structure as described in item 8 of the scope of patent application, the upper surface of the P-type heavily doped region has no field oxide. 如申請專利範圍第8項所述的製造高電壓半導體結構的方法，其中形成該高電壓元件的該步驟包括: 形成高電壓驅動元件在該第一N型井區中，其中一高電壓終端結構圍繞該高電壓驅動元件。 The method for manufacturing a high-voltage semiconductor structure as described in item 8 of the scope of patent application, wherein the step of forming the high-voltage element includes: A high-voltage driving element is formed in the first N-type well region, and a high-voltage terminal structure surrounds the high-voltage driving element. 如申請專利範圍第8項所述的製造高電壓半導體結構的方法，其中形成該外圍元件的該步驟包括形成電壓移位器在該第二N型井區中。The method for manufacturing a high-voltage semiconductor structure as described in item 8 of the scope of patent application, wherein the step of forming the peripheral element includes forming a voltage shifter in the second N-type well region.
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