TWI854784B - High-voltage junction termination structure - Google Patents

Abstract

A high-voltage junction termination structure is provided herein, which is configured to separate the semiconductor devices in a first region from those in a second region. The isolation structure includes a first well, a second well, a first doping region, a second doping region, a third doping region, a fourth doping region, and a fifth doping region. The second well is adjacent to the first well and in contact with the first well on an interface. The first doping region is formed in the first well. The second doping region is formed in the first well. The third doping region and the fourth doping region are formed in the second well. The fifth doping region is formed in both the first well and the second well and deposited on the interface. The first well, the first doping region, the third doping region, and the fifth doping region are N-type, and the second well, the second doping region, and the fourth doping region are P-type.

Description

High voltage junction termination structure

The present invention relates to a high voltage junction terminal structure for isolating a high side region circuit and a low side region circuit, and more particularly to a high voltage junction terminal structure for providing an electrostatic discharge path.

FIG. 1 is a circuit diagram showing a high voltage integrated circuit. As shown in FIG. 1, the high voltage integrated circuit 100 includes a low-side region driver circuit 110, a voltage level shift circuit 120, a high-side region driver circuit 130, an upper bridge transistor Q1, and a lower bridge transistor Q2. The lower bridge driver circuit 110 controls the lower bridge transistor Q2 according to the input signal SIN, and controls the upper bridge transistor Q1 through the driving signal through the voltage level shift circuit 120 and the high-side region circuit 130, wherein the low-side region driver circuit 110 is powered by a low voltage VD and a ground terminal GND.

The high-side driving circuit 130 is powered by a first high voltage VB and a floating voltage VS, wherein the first high voltage VB is greater than the second high voltage HV, and the upper bridge transistor Q1 and the lower bridge transistor Q2 are not turned on at the same time to generate a floating voltage VS. The voltage level shifting circuit 120 includes a first N-type transistor N1, a second N-type transistor N2, a first resistor R1, and a second resistor R2, and is used to convert the driving signal generated by the low-side driving circuit 110 (i.e., ranging from the low voltage VD to the ground terminal GND) into a voltage level of the high-side driving circuit 130 (i.e., ranging from the first high voltage VB to the floating voltage VS). In order to isolate the low-side driving circuit 110 and the high-side driving circuit 130, the high-voltage integrated circuit 100 further includes a junction diode JD parasitic on a high-voltage junction termination structure, wherein the cathode terminal NC of the junction diode JD is coupled to the first high voltage VB, and the anode terminal NA of the junction diode JD is coupled to the ground terminal GND.

Since the junction diode JD occupies a larger circuit area than the first N-type transistor N1 and the second N-type transistor N2, when an electrostatic discharge event occurs at the first high voltage VB, removing the electrostatic charge through the junction diode JD helps protect the high voltage integrated circuit 100 from burning. Since the junction diode JD, the first N-type transistor N1, and the second N-type transistor N2 are adjacent to each other in the circuit layout and have similar structures, they can all be used to remove the electrostatic charge. In order to avoid the first N-type transistor N1 or the second N-type transistor N2 being turned on when an electrostatic discharge event occurs, it is necessary to ensure that the electrostatic charge is removed to the ground terminal GND through the junction diode JD.

The present invention proposes a high voltage junction terminal structure with electrostatic discharge capability. By forming a silicon controlled rectifier with the high voltage junction terminal structure, the high voltage junction terminal structure that occupies a larger circuit area has excellent electrostatic discharge capability. In addition, the present invention further reduces the conduction voltage of the silicon controlled rectifier formed by the high voltage junction terminal structure, ensuring that the electrostatic charge is indeed discharged to the ground terminal through the silicon controlled rectifier formed by the high voltage junction terminal structure, thereby reducing the possibility of other circuit components being burned due to electrostatic discharge.

In view of this, the present invention proposes a high voltage junction terminal structure for dividing semiconductor elements respectively located in a first region and a second region. The above-mentioned high voltage junction terminal structure includes: a first well region, a second well region, a first doped region, a second doped region, a third doped region, a fourth doped region and a fifth doped region. The above-mentioned first well region has N-type doping. The above-mentioned second well region has P-type doping, is adjacent to the above-mentioned first well region and contacts the above-mentioned first well region at an interface. The above-mentioned first doped region has N-type doping and is formed in the above-mentioned first well region. The above-mentioned second doped region has P-type doping and is formed in the above-mentioned first well region. The third doped region has N-type doping and is formed in the second well region. The fourth doped region has P-type doping and is formed in the second well region. The fifth doped region has N-type doping and is formed in the first well region and the second well region and is located on the interface.

According to an embodiment of the present invention, the semiconductor elements in the first region are powered by a first high voltage and a first low voltage, and the semiconductor elements in the second region are powered by a second high voltage and a second low voltage. The first high voltage exceeds the first low voltage, and the second high voltage exceeds the second low voltage. The first high voltage exceeds the second high voltage, and the second low voltage is not greater than the first low voltage.

According to an embodiment of the present invention, the first well region, the second well region, the first doped region, the second doped region, the third doped region, the fourth doped region and the fifth doped region form a silicon-controlled rectifier, wherein the fifth doped region is used to reduce the conduction voltage of the silicon-controlled rectifier.

According to an embodiment of the present invention, when an electrostatic discharge event occurs at the first high voltage, the charge of the electrostatic discharge event is discharged to the second low voltage via the silicon-controlled rectifier.

According to an embodiment of the present invention, the first doped region and the second doped region are electrically connected together to form a first node and electrically connected to the first high voltage, and the third doped region and the fourth doped region are electrically connected together to form a second node and electrically connected to the second low voltage.

According to an embodiment of the present invention, the high voltage junction terminal structure further includes a field oxide layer. The field oxide layer is formed between the second doped region and the third doped region. The field oxide layer has a width, wherein the width is used to determine the breakdown voltage of the high voltage junction terminal structure.

According to another embodiment of the present invention, the high voltage junction terminal structure further includes: a first gate oxide layer, a second gate oxide layer, a first gate electrode and a second gate electrode. The first gate oxide layer is located between the field oxide layer and the fifth doped region and covers the first well region. The second gate oxide layer is formed between the third doped region and the fifth doped region and covers the second well region. The first gate electrode covers the field oxide layer and the first gate oxide layer, and contacts the first gate oxide layer. The second gate electrode covers the second gate oxide layer and contacts the second gate oxide layer.

According to another embodiment of the present invention, the first doped region, the second doped region, the first well region, the third doped region, the fourth doped region, the fifth doped region, the second well region, the second gate oxide layer and the second gate electrode form a silicon-controlled rectifier, wherein the fifth doped region is used to reduce the conduction voltage of the silicon-controlled rectifier, and the second gate oxide layer is used to further reduce the conduction voltage of the silicon-controlled rectifier.

According to another embodiment of the present invention, the first doped region and the second doped region are electrically connected together to form a first node and electrically connected to the first high voltage, and the third doped region, the fourth doped region and the second gate electrode are electrically connected together to form a second node and electrically connected to the second low voltage.

According to an embodiment of the present invention, the first well region, the second well region, the first doped region, the second doped region, the third doped region, the first gate oxide layer, the second gate oxide layer, and the fourth doped region are arranged along a first direction. The first doped region, the second doped region, the first gate oxide layer, the second gate oxide layer, the third doped region, and the fourth doped region extend along a second direction, wherein the first direction and the second direction are different.

According to another embodiment of the present invention, the fifth doping region further includes a plurality of sub-doping regions. The plurality of sub-doping regions are arranged along a second direction, wherein there is a distance between each of the plurality of sub-doping regions.

According to another embodiment of the present invention, the first doped region, the second doped region, the first well region, the plurality of sub-doped regions, the second gate oxide layer, the second gate electrode, the third doped region, the second well region, and the fourth doped region form a first silicon-controlled rectifier. The first doped region, the second doped region, the first well region, the third doped region, the second well region, and the fourth doped region form a second silicon-controlled rectifier. The first silicon-controlled rectifier and the second silicon-controlled rectifier are different.

According to another embodiment of the present invention, the breakdown voltage of the first silicon-controlled rectifier is similar to the breakdown voltage of the second silicon-controlled rectifier, wherein the turn-on voltage of the first silicon-controlled rectifier is smaller than the turn-on voltage of the second silicon-controlled rectifier.

The following description is an embodiment of the present disclosure. Its purpose is to illustrate the general principles of the present disclosure and should not be regarded as a limitation of the present disclosure. The scope of the present disclosure shall be based on the scope defined by the application patent.

It is worth noting that the content disclosed below can provide multiple embodiments or examples for implementing different features of the present disclosure. The specific component examples and arrangements described below are only used to briefly and concisely explain the spirit of the present disclosure and are not used to limit the scope of the present disclosure. In addition, the following description may reuse the same component symbols or words in multiple examples. However, the purpose of repetition is only to provide a simplified and clear description, and is not used to limit the relationship between the multiple embodiments and/or configurations discussed below.

In addition, the description described below that a feature is connected to, coupled to and/or formed on another feature may actually include multiple different embodiments, including that the features are directly in contact, or that other additional features are formed between the features, etc., so that the features are not in direct contact.

In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used in the embodiments to describe the relative relationship of one element of the drawings to another element. It is understood that if the device in the drawings is turned over so that it is upside down, the elements described on the "lower" side will become elements on the "upper" side.

It is understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or parts, these elements, components, regions, layers, and/or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and/or parts. Therefore, a first element, component, region, layer, and/or part discussed below may be referred to as a second element, component, region, layer, and/or part without departing from the teachings of some embodiments of the present disclosure.

Some embodiments of the present disclosure can be understood together with the drawings, and the drawings of the embodiments of the present disclosure are also considered as part of the description of the embodiments of the present disclosure. It should be understood that the drawings of the embodiments of the present disclosure are not drawn in proportion to the actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present disclosure. In addition, the structures and devices in the drawings are drawn in a schematic manner to clearly show the features of the embodiments of the present disclosure.

Here, the terms "about", "approximately", and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. The quantities given here are approximate quantities, that is, in the absence of specific description of "about", "approximately", and "generally", the meaning of "about", "approximately", and "generally" can still be implied.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of this disclosure.

In some embodiments of the present disclosure, terms such as "connected", "interconnected", etc., related to bonding and connection, unless otherwise specifically defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein there is another structure disposed between the two structures. Moreover, such terms related to bonding and connection may also include the situation where both structures are movable, or both structures are fixed.

In the drawings, similar components and/or features may have the same component symbols. Various components of the same type may be distinguished by adding letters or numbers after the component symbols to distinguish similar components and/or similar features.

In some embodiments of the present disclosure, relative terms such as "lower", "upper", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be understood as the orientations shown in the paragraph and related drawings. Such relative terms are only for the convenience of explanation and do not mean that the device described therein needs to be manufactured or operated in a specific orientation. Terms related to joining and connection, such as "connected", "interconnected", etc., unless specifically defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein other structures are disposed between the two structures. Furthermore, such terms related to joining and connection may also include situations where both structures are movable, or both structures are fixed.

Embodiments of the present invention disclose embodiments of semiconductor devices, and the embodiments may be included in integrated circuits (ICs) such as microprocessors, memory devices, and/or other devices. The ICs may also include various passive and active microelectronic components such as thin-film resistors, other types of capacitors such as metal-insulator-metal capacitors (MIMCAPs), inductors, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (BJTs), lateral diffused MOS transistors, high-power MOS transistors, or other types of transistors. A person having ordinary skill in the art to which the present invention pertains will appreciate that the semiconductor device may also be used in an integrated circuit including other types of semiconductor elements.

FIG. 2 is a cross-sectional view of a high voltage junction termination structure according to an embodiment of the present invention. As shown in FIG. 2 , the high voltage junction termination structure 200 includes a substrate SUB, a first well region W1 and a second well region W2.

The substrate SUB has a first conductivity type. According to one embodiment of the present invention, the substrate SUB is a silicon substrate. According to other embodiments of the present invention, the substrate SUB may also be a lightly doped semiconductor substrate having the first conductivity type.

The first well region W1 is formed in the semiconductor substrate SUB and has a second conductivity type. According to one embodiment of the present invention, the first conductivity type is P type and the second conductivity type is N type. According to one embodiment of the present invention, the first well region W1 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the area of the predetermined first well region W1 to form the first well region W1.

As shown in FIG. 2, the first well W1 is adjacent to the first region RG1. According to some embodiments of the present invention, the high-side region driver circuit 130 of FIG. 1 is located in the first region RG1. According to some embodiments of the present invention, the voltage level shift circuit 120 of FIG. 1 may be located between the first region RG1 and the second region RG2.

The second well region W2 is formed in the semiconductor substrate SUB and is adjacent to the first well region W1 and contacts the first well region W1 at the interface INT, wherein the second well region W2 has a first conductivity type. According to one embodiment of the present invention, the second well region W2 can also be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the second well region W2 is to be formed to form the second well region W2. In this embodiment, the doping concentration of the second well region W2 is higher than the doping concentration of the semiconductor substrate SUB.

As shown in FIG. 2, the second well W2 is adjacent to the second region RG2. According to some embodiments of the present invention, the low-end region driving circuit 110 of FIG. 1 is located in the second region RG2. According to some embodiments of the present invention, the voltage level shifting circuit 120 of FIG. 1 may be located between the second region RG2 and the first region RG1. According to some embodiments of the present invention, the first region RG1 may be regarded as a high-end region, and the second region RG2 may be regarded as a low-end region, and the high-voltage junction terminal structure 200 is used to isolate the high-end region and the low-end region.

As shown in FIG. 2 , the semiconductor structure 200 further includes a first doping region D1, a second doping region D2, a third doping region D3, and a fourth doping region D4. The first doping region D1 has a second conductivity type and is formed in the first well region W1. According to one embodiment of the present invention, the doping concentration of the first doping region D1 is higher than the doping concentration of the first well region W1. The second doping region D2 has a first conductivity type and is formed in the first well region W1. According to one embodiment of the present invention, the doping concentration of the second doping region D2 is higher than the doping concentration of the second well region W2.

The third doped region D3 has the second conductivity type and is formed in the second well region W2. According to one embodiment of the present invention, the doping concentration of the third doped region D3 is higher than the doping concentration of the first well region W1. The fourth doped region D4 has the first conductivity type and is formed in the second well region W2. According to one embodiment of the present invention, the doping concentration of the fourth doped region D4 is higher than the doping concentration of the second well region W2.

As shown in FIG. 2 , the high voltage junction termination structure 200 further includes a field oxide layer FOX, a gate oxide layer GOX, and a gate electrode GATE. The field oxide layer FOX is formed in the first well region W1 and is adjacent to the second doped region D2, wherein the field oxide layer FOX has a width WD. According to an embodiment of the present invention, the width WD is used to determine the breakdown voltage of the high voltage junction termination structure 200. The gate oxide layer GOX covers the interface INT and is formed between the field oxide layer FOX and the third doped region D3. The gate electrode GATE covers the field oxide layer FOX and the gate oxide layer GOX, and contacts the gate oxide layer GOX.

The semiconductor structure 200 further includes a first isolation structure ISO1 and a second isolation structure ISO2. The first isolation structure ISO1 is located between the first doped region D1 and the second doped region D2 and on the first well region W1 to separate the first doped region D1 and the second doped region D2.

As shown in FIG. 2 , the first isolation structure ISO1 directly contacts the first doped region D1 and the second doped region D2 , but this is not intended to limit the present invention. According to other embodiments of the present invention, the first isolation structure ISO1 does not contact at least one of the first doped region D1 and the second doped region D2 .

The second isolation structure ISO2 is located between the third doped region D3 and the fourth doped region D4 and on the second well region W2 to separate the third doped region D3 and the fourth doped region D4. As shown in FIG. 2 , the second isolation structure ISO2 directly contacts the third doped region D3 and the fourth doped region D4, but this is not intended to limit the present invention. According to other embodiments of the present invention, the second isolation structure ISO2 does not contact at least one of the third doped region D3 and the fourth doped region D4.

As shown in FIG. 2 , the first doped region D1 and the second doped region D2 are coupled together to form a first node ND1, and the fourth doped region D4 and the fifth doped region D5 are coupled together to form a second node ND2. According to an embodiment of the present invention, the first well region W1, the second well region W2, the first doped region D1, the second doped region D2, the third doped region D3 and the fourth doped region D4 of the high voltage junction terminal structure 200 form a silicon controlled rectifier to improve the electrostatic charge removal capability.

According to an embodiment of the present invention, the first node ND1 is coupled to the first high voltage VB of FIG. 1, and the second node ND2 is coupled to the ground terminal GND of FIG. 1. Moreover, since the high voltage junction terminal structure 200 forms a silicon controlled rectifier, it has a better electrostatic charge removal capability than the junction diode JD of FIG. 1.

However, in the circuit layout, the high voltage junction terminal structure 200 is adjacent to the first N-type transistor N1 and the second N-type transistor N2 of the voltage level shift circuit 120. Although the high voltage junction terminal structure 200 has a better electrostatic charge removal capability than the first N-type transistor N1 and the second N-type transistor N2, it cannot be guaranteed that the high voltage junction terminal structure 200 will be turned on before the first N-type transistor N1 and the second N-type transistor N2 when an electrostatic discharge event occurs. Therefore, the high voltage junction terminal structure 200 still needs to be further optimized.

FIG. 3 is a cross-sectional view of a high voltage junction termination structure according to another embodiment of the present invention. Compared with the high voltage junction termination structure 200 of FIG. 2, the high voltage junction termination structure 300 further includes a fifth doped region D5 and a third isolation structure ISO3, and omits the gate oxide layer GOX.

The fifth doped region D5 has the second conductivity type and is formed in the first well region W1 and the second well region W2 and is formed on the interface INT. According to one embodiment of the present invention, the doping concentration of the fifth doped region D5 is higher than the doping concentration of the first well region W1. According to one embodiment of the present invention, the field oxide layer FOX is formed between the second doped region D2 and the fifth doped region D5.

The third isolation structure ISO3 is located between the third doped region D3 and the fifth doped region D5 and on the second well region W2 to separate the third doped region D3 and the fifth doped region D5. As shown in FIG. 2 , the third isolation structure ISO3 directly contacts the third doped region D3 and the fifth doped region D5, but this is not intended to limit the present invention. According to other embodiments of the present invention, the third isolation structure ISO3 does not contact at least one of the third doped region D3 and the fifth doped region D5.

According to one embodiment of the present invention, since the high voltage junction terminal structure 300 further includes a fifth doped region D5 than the high voltage junction terminal structure 200, and the fifth doped region D5 is used to reduce the turn-on voltage of the silicon-controlled rectifier formed by the high voltage junction terminal structure 300, the turn-on voltage of the silicon-controlled rectifier of the high voltage junction terminal structure 300 is lower than the turn-on voltage of the silicon-controlled rectifier of the high voltage junction terminal structure 200, and the breakdown voltages of the high voltage junction terminal structure 300 and the high voltage junction terminal structure 200 are similar, and can be used to withstand similar high voltages.

According to some embodiments of the present invention, since the fifth doped region D5 helps to reduce the turn-on voltage of the silicon-controlled rectifier formed by the high-voltage junction terminal structure 300, it can be ensured that when an electrostatic discharge event occurs, the silicon-controlled rectifier formed by the high-voltage junction terminal structure 300 will be turned on earlier than the transistors adjacent to the high-voltage junction terminal structure 300 (e.g., the first N-type transistor N1 and the second transistor N2 in FIG. 1), thereby ensuring that the electrostatic charge is discharged to the ground through the high-voltage junction terminal structure 300 having a larger conductive surface area.

FIG. 4 is a cross-sectional view of a high voltage junction termination structure according to another embodiment of the present invention. Compared with the high voltage junction termination structure 200 in FIG. 2 , the high voltage junction termination structure 400 in FIG. 4 further includes a first gate oxide layer GOX1, a second gate oxide layer GOX2, a first gate electrode GATE1, and a second gate electrode GATE2.

As shown in FIG. 4 , the first gate oxide layer GOX1 is formed on the first well region W1 and is further located between the field oxide layer FOX and the fifth doped region D5. The second gate oxide layer GOX2 is formed between the third doped region D3 and the fifth doped region D5 and covers the second well region W2. The first gate electrode GATE1 covers the field oxide layer FOX and the first gate oxide layer GOX1 and contacts the first gate oxide layer GOX1. The second gate electrode GATE2 covers the second gate oxide layer GOX2 and contacts the second gate oxide layer. According to an embodiment of the present invention, the second gate, the third doped region D3 and the fourth doped region D4 are coupled together to form a second node ND2 of the high voltage junction termination structure 400.

According to one embodiment of the present invention, the first node ND1 of the high voltage junction terminal structure 400 is coupled to the first high voltage VB of FIG. 1, and the second node ND2 is coupled to the ground terminal GND of FIG. 1. According to some embodiments of the present invention, the silicon-controlled rectifier formed by the high voltage junction terminal structure 400 is compared with the silicon-controlled rectifier formed by the high voltage junction terminal structure 300. The silicon-controlled rectifier formed by the high voltage junction terminal structure 400 has a lower conduction voltage than the silicon-controlled rectifier formed by the high voltage junction terminal structure 300, and both have similar breakdown voltages.

In other words, the third doped region D3, the second gate oxide layer GOX2 and the fifth doped region D5 of the high voltage junction terminal structure 400 form an N-type transistor, wherein the N-type transistor (i.e., the second gate) is coupled to the lowest voltage level (i.e., the second node ND2 is coupled to the ground terminal GND in FIG. 1). Moreover, compared to the high voltage junction terminal structure 300, the N-type transistor with the gate grounded helps to further reduce the conduction voltage of the silicon-controlled rectifier formed by the high voltage junction terminal structure 400.

FIG. 5 is a top view of a high voltage junction termination structure according to another embodiment of the present invention, wherein the cross-sectional view cut along line A-A' is as shown in FIG. 2, and the cross-sectional view cut along line B-B' is as shown in FIG. 4. As shown in FIG. 5, the first doping region D1, the second doping region D2, the third doping region D3, and the fourth doping region D4 of the high voltage junction termination structure 500 are arranged along the first direction DR1, and the high voltage junction termination structure 500 further includes a plurality of sub-doping layers SD, wherein the plurality of sub-doping regions SD are arranged along the second direction DR2. According to one embodiment of the present invention, the first direction DR1 is different from the second direction DR2.

According to one embodiment of the present invention, the fifth doped region D5 of the high voltage junction termination structure 400 of FIG. 4 is divided into a plurality of sub-doped regions SD as shown in FIG. 5 , and as shown in FIG. 5 , the sub-doped regions SD have a spacing D therebetween. As shown in FIG. 5 , the first gate oxide layer GOX1 and the second gate oxide layer GOX2 (i.e., along line B-B′) of the high voltage junction termination structure 500 may correspond to the first gate oxide layer GOX1 and the second gate oxide layer GOX2 of the high voltage junction termination structure 400 of FIG. 4 . According to one embodiment of the present invention, the first gate oxide layer GOX1 and the first gate GATE1 are connected to the second gate oxide layer GOX2 and the second gate GATE2 via a distance D. In other words, the distance D between the sub-doped regions SD also forms a gate oxide layer and a gate, so that the first gate oxide layer GOX1 and the first gate GATE1 and the second gate oxide layer GOX2 and the second gate GATE2 are electrically connected together.

According to some embodiments of the present invention, since the first gate oxide layer GOX1 and the first gate GATE1 as well as the second gate oxide layer GOX2 and the second gate GATE2 are electrically connected to each other via the distance D, a field oxide layer FOX (not shown in FIG. 5 ) may be formed in the region of the distance D to isolate each sub-doped region SD.

The present invention proposes a high voltage junction terminal structure with electrostatic discharge capability. By forming a silicon controlled rectifier with the high voltage junction terminal structure, the high voltage junction terminal structure that occupies a larger circuit area has excellent electrostatic discharge capability. In addition, the present invention further reduces the conduction voltage of the silicon controlled rectifier formed by the high voltage junction terminal structure, ensuring that the electrostatic charge is indeed discharged to the ground terminal through the silicon controlled rectifier formed by the high voltage junction terminal structure, thereby reducing the possibility of other circuit components being burned due to electrostatic discharge.

Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person with ordinary knowledge in the relevant technical field can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the relevant technical field can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure content of some embodiments of the present disclosure, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described here, they can be used according to some embodiments of the present disclosure. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each patent application constitutes a separate embodiment, and the protection scope of the present disclosure also includes the combination of each patent application and embodiment.

100: High voltage integrated circuit 110: Low end drive circuit 120: Voltage level shift circuit 130: High end drive circuit 200,300,400,500: High voltage junction terminal structure Q1: Upper bridge transistor Q2: Lower bridge transistor VD: Low voltage GND: Ground terminal SIN: Input signal VB: First high voltage VS: Floating voltage HV: Second high voltage N1: First N-type transistor N2: Second N-type transistor R1: First resistor R2: Second resistor JD: Junction diode NC: Cathode terminal NA: Anode terminal SUB: Substrate W1: First well area W2: Second well area RG1: First region RG2: Second region INT: Interface D1: First doped region D2: Second doped region D3: Third doped region D4: Fourth doped region D5: Fifth doped region FOX: Field oxide layer GOX: Gate oxide layer GOX1: First gate oxide layer GOX2: Second gate oxide layer GATE: Gate electrode GATE1: First gate electrode GATE2: Second gate electrode WD: Width ISO1: First isolation structure ISO2: Second isolation structure ISO3: Third isolation structure ND1: First node ND2: Second node SD: Sub-doped layer DR1: First direction DR2: Second direction D: Spacing

FIG. 1 is a circuit diagram showing a high voltage integrated circuit; FIG. 2 is a cross-sectional view showing a high voltage junction terminal structure according to one embodiment of the present invention; FIG. 3 is a cross-sectional view showing a high voltage junction terminal structure according to another embodiment of the present invention; FIG. 4 is a cross-sectional view showing a high voltage junction terminal structure according to another embodiment of the present invention; and FIG. 5 is a top view showing a high voltage junction terminal structure according to another embodiment of the present invention.

300: High voltage junction terminal structure

SUB: Substrate

W1: First well area

W2: Second well area

RG1: First Region

RG2: Second Region

INT: Interface

D1: First doping zone

D2: Second mixed area

D3: The third mixed area

D4: The fourth mixed zone

D5: Fifth mixed area

FOX: Field oxide layer

WD: Width

ISO1: First isolation structure

ISO2: Second isolation structure

ISO3: The third isolation structure

ND1: First Node

ND2: Second Node

Claims (13)

A high voltage junction terminal structure for dividing semiconductor elements located in a first region and a second region, comprising: a first well region having an N-type doping; a second well region having a P-type doping, adjacent to the first well region and contacting the first well region at an interface; a first doping region having an N-type doping and formed in the first well region; a second doping region having a P-type doping and formed in the first well region; a third doping region having an N-type doping and formed in the second well region; a fourth doping region having a P-type doping and formed in the second well region; and A fifth doped region having N-type doping and formed in the first well region and the second well region and located on the interface. A high voltage junction terminal structure as claimed in claim 1, wherein the semiconductor elements in the first region are powered by a first high voltage and a first low voltage, and the semiconductor elements in the second region are powered by a second high voltage and a second low voltage, wherein the first high voltage exceeds the first low voltage, and the second high voltage exceeds the second low voltage, wherein the first high voltage exceeds the second high voltage, and wherein the second low voltage is not greater than the first low voltage. A high voltage junction terminal structure as claimed in claim 2, wherein the first well region, the second well region, the first doped region, the second doped region, the third doped region, the fourth doped region and the fifth doped region form a silicon-controlled rectifier, wherein the fifth doped region is used to reduce the conduction voltage of the silicon-controlled rectifier. A high voltage junction terminal structure as claimed in claim 3, wherein when an electrostatic discharge event occurs at the first high voltage, the charge of the electrostatic discharge event is discharged to the second low voltage via the silicon-controlled rectifier. A high voltage junction terminal structure as claimed in claim 2, wherein the first doped region and the second doped region are electrically connected together to form a first node and electrically connected to the first high voltage, and the third doped region and the fourth doped region are electrically connected together to form a second node and electrically connected to the second low voltage. The high voltage junction terminal structure of claim 2 further includes: A field oxide layer formed between the second doped region and the third doped region, wherein the field oxide layer has a width, wherein the width is used to determine the breakdown voltage of the high voltage junction terminal structure. The high voltage junction terminal structure of claim 6 further includes: a first gate oxide layer, located between the field oxide layer and the fifth doped region and covering the first well region; a second gate oxide layer, formed between the third doped region and the fifth doped region and covering the second well region; a first gate electrode, covering the field oxide layer and the first gate oxide layer, and contacting the first gate oxide layer; and a second gate electrode, covering the second gate oxide layer, and contacting the second gate oxide layer. A high voltage junction terminal structure as in claim 7, wherein the first doped region, the second doped region, the first well region, the third doped region, the fourth doped region, the fifth doped region, the second well region, the second gate oxide layer and the second gate electrode form a silicon-controlled rectifier, wherein the fifth doped region is used to reduce the on-voltage of the silicon-controlled rectifier, and wherein the second gate oxide layer is used to further reduce the on-voltage of the silicon-controlled rectifier. A high voltage junction terminal structure as in claim 8, wherein the first doped region and the second doped region are electrically connected together to form a first node and electrically connected to the first high voltage, and the third doped region, the fourth doped region and the second gate electrode are electrically connected together to form a second node and electrically connected to the second low voltage. A high voltage junction terminal structure as claimed in claim 9, wherein the first well region, the second well region, the first doped region, the second doped region, the third doped region, the first gate oxide layer, the second gate oxide layer and the fourth doped region are arranged along a first direction; wherein the first doped region, the second doped region, the first gate oxide layer, the second gate oxide layer, the third doped region and the fourth doped region extend along a second direction; wherein the first direction and the second direction are different. As in claim 10, the fifth doped region further comprises: A plurality of sub-doped regions arranged along a second direction, wherein each of the plurality of sub-doped regions has a spacing therebetween. A high voltage junction terminal structure as claimed in claim 11, wherein the first doped region, the second doped region, the first well region, the plurality of sub-doped regions, the second gate oxide layer, the second gate electrode, the third doped region, the second well region and the fourth doped region form a first silicon-controlled rectifier; wherein the first doped region, the second doped region, the first well region, the third doped region, the second well region and the fourth doped region form a second silicon-controlled rectifier; wherein the first silicon-controlled rectifier and the second silicon-controlled rectifier are different. A high voltage junction terminal structure as claimed in claim 12, wherein the breakdown voltage of the first silicon-controlled rectifier is similar to the breakdown voltage of the second silicon-controlled rectifier; wherein the turn-on voltage of the first silicon-controlled rectifier is less than the turn-on voltage of the second silicon-controlled rectifier.

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