TW201423990A - Bi-directional bipolar junction transistor for high voltage electrostatic discharge protection - Google Patents

Abstract

A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.

Description

Bidirectional bipolar junction transistor for high voltage electrostatic discharge protection

Embodiments of the present invention generally relate to semiconductor devices, and more particularly to a bidirectional bipolar junction transistor (BJT) for high voltage electrostatic discharge (ESD) protection.

In fact, in all aspects of the manufacture of electronic devices, there is currently a driving force that continues to advance toward the size of the reduction device. When both smaller and larger devices have substantially equivalent capabilities, smaller electronic devices tend to be more popular than larger, bulkier devices. Thus, the ability to manufacture smaller components will obviously tend to facilitate the production of smaller devices that incorporate those components. However, many modern electronic devices require electronic circuitry to perform startup functions (eg, switching devices) and data processing or other decision making functions. The use of low voltage complementary metal oxide semiconductor (CMOS) technology for these dual functions may not always be practical. Therefore, high voltage (or high power) devices have also been developed to manipulate low voltage operations that are not practical for many applications.

The electrostatic discharge (ESD) performance of a typical high voltage device often depends on the overall width of the corresponding device and the surface or lateral rule. Therefore, ESD performance can typically be more decisive for smaller devices. Typically, the high voltage device has a characteristic that includes a low on-state resistance (Rdson), a high breakdown voltage, and a low hold voltage. The low on-state resistance can tend to cause an ESD current that is more likely to concentrate on the surface or the drain edge of a device during an ESD event. High currents and high electric fields can cause physical damage in a surface junction area of such a device. Based on this typical requirement for a low on-state resistance, the surface or lateral ruler is likely to be unable to be increased. Therefore, ESD protection can be a challenge.

The characteristic of the high breakdown voltage of the high voltage device typically means that the breakdown voltage is higher than the operating voltage and the trigger voltage (Vt1) is higher than the breakdown voltage. Thus, during an ESD event, the internal circuitry of the high voltage device may be at risk of damage before the high voltage device is turned "on" for ESD protection. The low hold voltage characteristic of the high voltage device also exposes the possibility that unwanted noise associated with a power-on peak voltage or a surge voltage can be triggered, or a latch-up effect can occur during normal operation. Since the electric field distribution can be sensitive to routing, the high voltage device can also experience a plate effect such that the ESD current can be concentrated on the surface or the drain edge during an ESD event.

In order to improve the performance of high voltage devices for ESD events, one technique that has been implemented involves the additional use of masks and other processes to create a larger diode within a bipolar junction transistor (BJT) assembly and / or increase the surface or transverse ruler for the MOS transistor. Voltage controlled rectifiers (SCRs) have also been developed to protect circuits during ESD events. However, this characteristic also increases the latch-up effect during normal operation when the low hold voltage of the pilot rectifier indicates that they can be properly executed during an ESD event.

In particular, motor driver circuits can use current solutions to troubleshoot protection from ESD events. This is because when a motor is turned off, it can continue to rotate for a while, thus acting in response to an inductor that feeds back a high negative voltage. If the motor driver circuit is to include a PMOS, the parasitic forward biased diode of the PMOS can be turned on by the negative feedback voltage, potentially causing latch-up effects and/or other irregular circuit operations.

Thus, what is desired may be to develop an improved structure to provide ESD protection, and in particular to provide two-way ESD protection.

Accordingly, some exemplary embodiments focus on a bidirectional bipolar junction transistor (BJT) for high voltage electrostatic discharge (ESD) protection. In some cases, the ESD protection can be based, at least in part, on a modification of a bipolar complementary metal oxide semiconductor (BiCMOS) diffusion metal oxide semiconductor (DMOS) process (BCD process) that can involve an epitaxial process. provide.

In an exemplary embodiment, a two-way BJT is provided (as used herein, "exemplary" means "as an example, instance or illustration"). The bidirectional BJT can include a p-type substrate, an N+ doped buried layer, an N-type well region, and two P-type well regions. The N+ doped buried layer can be disposed adjacent to the substrate. The N-type well region may be disposed adjacent to the N+ doped buried layer and surrounding the first and second P-type well regions such that a portion of the N-type well region is interposed in the first and second portions P type well area. The plurality of P-type well regions may be disposed adjacent to the N+ doped buried layer, and each of the P-type well regions may each include one or more N+ doped plates and one or more P+ dopings board. A plurality of field oxide (FOX) films may be disposed adjacent to the N-well region, and one or more field plates may be disposed adjacent to the plurality of FOX portions.

According to a further embodiment, the first P-well may include first and second N+ doped plates, and a first P+ doped plate may be interposed between the first and second N+ doped plates And adjacent to the first and the second N+ doped plates. The second P-type well may include third and fourth N+ doped plates, and a second P+ doped plate may be interposed between the third and fourth N+ doped plates and adjacent to the third And the fourth N+ doped plate.

According to an alternative of the previous embodiment, the first P-well may include a first P+ doped plate, first, second, third, and fourth N+ doped plates, and first and second gates structure. The first P+ doped plate may be interposed between the second and the third N+ doped plates, and adjacent to the second and the third N+ doped plates, the first gate structure may be inserted Between the first and the second N+ doped plates, adjacent to the first and second N+ doped plates, and the second gate structure can be inserted in the third and the fourth N+ doping Between the plates, and adjacent to the third and fourth N+ doped plates. The second P-well may include a second P+ doped plate, fifth, sixth, seventh, and eighth N+ doped plates, and third and fourth gate structures. The second P+ doped plate may be interposed between the sixth and the seventh N+ doped plates, and adjacent to the sixth and the seventh N+ doped plates, the third gate structure may be inserted Between the fifth and the sixth N+ doped plates, adjacent to the fifth and sixth N+ doped plates, and the fourth gate structure can be inserted in the seventh and the eighth N+ doping Between the plates, and adjacent to the seventh and the eighth N+ doped plates.

In another exemplary embodiment, a circuit including a bidirectional high voltage ESD protection component is provided. The bidirectional high voltage ESD protection component comprises a p-type substrate, an N+ doped buried layer, an N-type well region, and two P-type well regions. The N+ doped buried layer can be disposed adjacent to the substrate. The N-type well region may be disposed adjacent to the N+ doped buried layer and may surround the first and second P-type well regions such that a portion of the N-type well region is inserted in the first and the Between the second P-wells. The plurality of P-type well regions may be disposed adjacent to the N+ doped buried layer, and each of the P-type well regions may each include one or more N+ doped plates and one or more P+ dopings board. The first, second, and third field oxide (FOX) portions may be disposed adjacent to the N-type well region. A first field plate may be disposed adjacent to the first FOX portion, second and third field plates may be disposed adjacent to a plurality of respective portions of the second FOX portion, and a fourth field plate may be adjacent to The third FOX portion is set.

According to still another exemplary embodiment, a semiconductor device including a first isolated high voltage n-channel metal oxide field effect transistor (HVNMOS) and a second isolated HV NMOS is provided, the first and the second isolated HVNMOS Share a common N-well isolation zone.

According to still another exemplary embodiment, a method of fabricating a bidirectional bipolar junction transistor (BJT) is provided comprising the steps of: providing a substrate structure, wherein the substrate structure comprises a p-type substrate region and is buried in An N+ doped buried layer in the p-type substrate region; forming a first P-type well region, a second P-type well region, and an N-type adjacent to the N+ doped buried layer in the p-type substrate region a well region, wherein the N-type well region surrounds the first and second P-type well regions such that at least a portion of the N-type well region is interposed between the first and second P-type well regions; Forming at least one N+ doped plate and at least one P+ doped plate in each of the first and second P-type well regions; forming an oxide layer by processing the N-type well region, wherein the oxide layer comprises a first, a second, and a third field oxide (FOX) portion; and a first, a second, a third, and a fourth field plate adjacent to the oxide layer, wherein the first a field plate is formed adjacent to the first FOX portion, the second and third field plates being adjacent to respective portions of the second FOX portion Formed, and the fourth panel adjacent to the third portion being formed FOX.

Some exemplary embodiments of the present invention will now be described more fully with reference to the appended claims Indeed, the various exemplary embodiments of the invention may be embodied in a variety of different embodiments and should not be construed as being limited to the exemplary embodiments set forth herein; Applicable legal provisions.

Some exemplary embodiments of the present invention may provide a bidirectional BJT; for example, the bidirectional BJT may be used for bidirectional high voltage ESD protection, such as for positive and negative voltage ESD protection. The bidirectional BJT of the exemplary embodiment can combine two isolated high voltage N-channel metal oxide semiconductor transistors (MOS) into an ESD guard, thereby providing a total area less than when providing similar ESD performance in both directions. The structure of a diode BJT and MOS. For example, the two isolated high voltage N-channel MOSs may not utilize drain-side diffusion. The exemplary embodiment may also have a breakdown voltage proximate to the operating voltage of the high voltage device and a trigger voltage that is lower than the breakdown voltage of the high voltage device. Moreover, a relatively high holding voltage than that provided by a controlled rectifier (SCR) can be provided to more easily avoid latch-up effects. For example, the exemplary embodiment is useful in a motor driver circuit such as connected between an input/output (I/O) pad and a power pad. In this case, the exemplary embodiment may provide positive and negative high voltage ESD protection without causing irregularities during normal operation and introducing no latch-up problems. In some cases, the exemplary embodiment can also be fabricated with a standard BCD process that does not require an additional number of masks or processes. For example, polysilicon used in some exemplary embodiments can be provided via ion implantation through a hard mask. According to an exemplary embodiment, the collapse and/or trigger voltage can be adjusted by adjusting the length of one or more field gates. Further, early turn-on can be provided by applying an additional bias voltage to one or more gates or polysilicon of the multiple emitter structure.

Figure 1a shows a simplified diagram of a conventional SCR 100. As shown, a conventional SCR consists of a P+ material 101, an N-material 102, a P-type material 103, and an N+ material 104; the P+ material 101 is adjacent to the N-material 102; the N-material 102 is in turn Adjacent to the P-type material 103; and the P-type material 103 itself is adjacent to the N+ material 104. An electrical equivalent map 150 is also depicted in Figure 1a. As shown in the chart 160 of Figure 1b, a conventional SCR provides ESD protection as shown by the fast back 161 in the forward direction, which occurs in the forward collapse voltage.

Figure 2a is a simplified diagram of an embodiment of the invention. As shown in view 200, embodiments of the present invention can operate in accordance with two NPN bipolar transistors 201 having a plurality of coupled N-type regions 202. Thus, as can be seen in views 210 and 220, the exemplary embodiment can operate to be triggered by a forward biased diode 211 and then turn on in both the forward direction 210 and the reverse direction 220. NPN BJT 201 is coming back quickly. Graph 230 depicts the aforementioned plurality of forward and reverse fast forwards 231. The exemplary embodiment may have a low on-resistance (Ron) and a high hold voltage, and the high ESD current may be discharged by the forward biased diode and the NPN BJT at the same time.

Figures 3a and 3b illustrate a simplified circuit diagram representation of an embodiment of the invention. As can be seen in Figure 3a, embodiments of the present invention can include two high voltage isolation NMOSs 300a and 300b that are combined in a common isolation region 301. As shown in Figure 3b, a plurality of electrical characteristics of embodiments of the present invention can be modeled in accordance with two BJT transistors 310a and 310b having a plurality of coupled collectors 311. As can be seen in Figures 4a and 4b, under positive ESD stress, the top transistor 310a operates in a forward biased diode 410a instead. As can be seen in Figures 5a and 5b, under negative ESD stress, the bottom transistor 310b operates instead of a forward biased diode 510b. Thus, embodiments of the present invention can ensure that ESD current is discharged, regardless of positive ESD or negative ESD stress, thereby providing two-way ESD protection. The plurality of forward and reverse collapse voltages of the exemplary embodiment may be the same or different via the use of a plurality of isolated NMOS or NPN BJTs having the plurality of identical or different breakdown voltages.

Thus, the electrical characteristics and properties of the exemplary embodiments of the present invention have been generally described, and reference is now made to Figures 6 through 11 to illustrate the structure of the exemplary embodiment.

Figure 6 illustrates a cross-sectional view of an exemplary embodiment for providing bidirectional high voltage ESD protection. As can be seen from FIG. 6, a P-type material substrate 600 with an N+ buried layer 601 or an epitaxially grown P-layer (P-epi) may be provided, wherein the N+ buried layer 601 is adjacent to the The P-type material substrate 600 or the epitaxially grown P-layer (P-epi) is provided. An N-type well 602a-c may be disposed adjacent to the N+ buried layer 601 and around the first and second P-type wells 603a and 603b such that a portion 602b of the N-type well is disposed in the first and the first Between the two P-wells 603a and 603b. According to some embodiments, the N-wells 602a-c may be a single connected well; or according to another embodiment, the N-wells 602a-c may comprise two or more separate N-type wells. According to an exemplary embodiment, a plurality of outer portions of the N-wells 602a, 602c may be in contact with the P-type substrate 600. The first and second P-wells 603a and 603b can include at least one P+ doped plate 605 and at least one N+ doped plate 604.

For example, according to the exemplary embodiment depicted in FIG. 6, each of the first and second P-wells 603a and 603b can include two N+ doped plates 604 and one P+ doped plate 605. Therefore, as shown, the first P-well 603a can include a first P+ doped plate 605 that can be inserted into a first N+ doped plate 604 and a second N+ doped Between the plates 604, and adjacent to the first N+ doped plate 604 and the second N+ doped plate 604. Similarly, the second P-type well 603b may include a second P+ doping plate 605, which is disposed in a third N+ doping plate 604 and a fourth N+ doping plate 604. And adjacent to the third N+ doped plate 604 and the fourth N+ doped plate 604. A plurality of field oxide film (FOX) portions 609 can be disposed adjacent the surface of portions of the N-wells 602a-c and adjacent a distal end of each of the plurality of N+ doped plates 604.

According to a further embodiment, one or more field plates 606 may be disposed adjacent to the plurality of FOX portions 609 (eg, the top of the plurality of FOX portions 609). For example, a first field plate 606 can be disposed adjacent to a first FOX portion, and a second and a third field plate 606 can be disposed adjacent to a plurality of respective portions of a second FOX portion, and a The four field plate 606 can be disposed adjacent to a third FOX portion. For example, the plurality of field plates 606 can comprise a layer of polysilicon, wherein the polysilicon can be provided in ion implantation in accordance with a hard mask. According to an exemplary embodiment, the length of one or more field plates 606 may be adjusted during manufacture to adjust the breakdown voltage and the trigger voltage of the device. That is, the collapse and the trigger voltage may depend on the length of the one or more field plates 606. According to another exemplary embodiment, an anode 607 may be operatively coupled to the P+ doped plate 605, the N+ doped plate 604, and the plurality of field plates 606 of one of the plurality of P-wells 603a; The cathode 608 can be operatively coupled to the P+ doped plate 605, the N+ doped plate 604, and the plurality of field plates 606 of the other of the plurality of P-wells 603b.

As can be seen from Fig. 6, the provided structure can effectively form a plurality of BJT transistors 610a and 610b (in this example, there are eight, that is, four anode side BJT transistors 610a and four cathodes). Side BJT transistor 610b). As shown, the plurality of anode side BJT transistors 610a and the plurality of collectors of the plurality of cathode side BJT transistors 610b (labeled "C" in FIG. 6) are effective according to the depicted structure. Ground connection. Furthermore, the plurality of anode side BJT transistors 610a and the plurality of bases of the plurality of cathode side BJT transistors 610b (labeled "B" in FIG. 6) are operatively connected to their respective P+ boards. 605; and the plurality of anode side BJT transistors 610a and the plurality of emitters of the plurality of cathode side BJT transistors 610b (labeled "E" in FIG. 6) are operatively connected to their respective N+ plates 604.

According to a further embodiment, a method of fabricating a bidirectional bipolar junction transistor (BJT) includes the steps of providing a substrate structure, wherein the substrate structure comprises a p-type substrate region and is buried in the p-type substrate region An N+ doped buried layer 601; forming a first P-type well region 603a, a second P-type well region 603b, and an N-type well region adjacent to the N+ doped buried layer in the p-type substrate region 602a-c, wherein the N-well region 602a-c surrounds the first and second P-well regions 603a, 603b such that at least a portion 602b of the N-well region 602a-c is inserted in the first sum Between the second P-type well regions 603a, 603b; forming at least one N+ doped plate 604 and at least one P+ doped plate 605 in each of the first and second P-type well regions 603a, 603b; Processing the N-type well regions 602a-c to form an oxide layer, wherein the oxide layer comprises a first, a second and a third field oxide (FOX) portion 609; and adjacent to the oxide layer Forming a first, a second, a third, and a fourth field plate 606, wherein the first field plate 606 is formed adjacent to the first FOX portion 609 The second and the third field plate 606 adjacent to the second portion 609 of each FOX are formed, and the fourth field plate 606 adjacent to the third portion 609 is formed FOX.

As shown in Figures 7 and 8, respectively, in a positive ESD event, the four anode side transistors 610a can actually operate in accordance with two forward biased diodes 710a, and in a negative In the ESD event, the four cathode side transistors 610b can actually operate in accordance with two forward biased diodes 810b. Thus, during a positive or negative ESD event, the ESD current can be discharged by at least one forward biased diode and at least one NPN BJT at the same time.

Turning now to Figure 9, a cross-sectional view of an exemplary embodiment including a multiple emitter structure is depicted. As with the embodiment depicted in FIG. 6, the multiple emitter structure of the embodiment in FIG. 9 includes a P-type material substrate 600 or an epitaxially grown P-layer (P-epi), an N+ buried Layer 601, an N-well 602a-c, a first and a second P-well 603a and 603b. The P-type material substrate 600 or the epitaxially grown P-layer (P-epi) has an N+ buried layer 601 disposed adjacent thereto. An N-type well 602a-c may be disposed adjacent to the N+ buried layer 601 and around the first and second P-type wells 603a and 603b such that a portion 602b of the N-type well is disposed in the first and the first Between the two P-wells 603a and 603b. According to some embodiments, the N-wells 602a-c may be a single connected well; or according to another embodiment, the N-wells 602a-c may comprise two or more separate N-type wells. According to an exemplary embodiment, a plurality of outer portions of the N-wells 602a, 602c may be in contact with the P-type substrate 600. Each of the first and second P-wells 603a and 603b can include at least one P+ doped plate 905 and at least one N+ doped plate 904.

For example, to provide the multiple emitter structure depicted in FIG. 9, each of the first and second P-wells 603a and 603b can include four N+ doped plates 90 4 and two P+ doped plates. 905 and two gate structures 906. Therefore, as shown, the first P-well 603a can include a first gate structure 906 that can be mounted on a first N+ doped plate 904 and a second N+ doped plate. Between 904, and adjacent to the first N+ doped plate 904 and the second N+ doped plate 904. A first P+ doped plate 905 can be interposed between the second N+ doped plate 904 and a third N+ doped plate 904, and adjacent to the second N+ doped plate 904 and the third N+ doping Board 904. Finally, a second gate structure 906 can be interposed between the third N+ doped plate 904 and a fourth N+ doped plate 904, and adjacent to the third N+ doped plate 904 and the fourth N+ doped Chopping board 904. Similarly, the second P-well 603b can include a third gate structure 906 that can be interposed between a fifth N+ doped plate 904 and a sixth N+ doped plate 904. And adjacent to the fifth N+ doped plate 904 and the sixth N+ doped plate 904. A second P+ doped plate 905 can be interposed between the sixth N+ doped plate 904 and a seventh N+ doped plate 904, and adjacent to the sixth N+ doped plate 904 and the seventh N+ doping Board 904. Finally, a fourth gate structure 906 can be interposed between the seventh N+ doped plate 904 and an eighth N+ doped plate 904, and adjacent to the seventh N+ doped plate 904 and the eighth N+ doped Chopping board 904. A plurality of field oxide film (FOX) portions 609 can be disposed adjacent the surface of the plurality of N-type wells 602a-c and adjacent a distal end of each of the plurality of N+ doped plates 604.

According to a further embodiment, one or more field plates 606 may be disposed adjacent to the plurality of FOX portions 609 (eg, the top of the plurality of FOX portions 609). For example, a first field plate 606 can be disposed adjacent to a first FOX portion, and a second and a third field plate 606 can be disposed adjacent to a plurality of respective portions of a second FOX portion, and a The four field plate 606 can be disposed adjacent to a third FOX portion. For example, the plurality of field plates 606 can comprise a layer of polysilicon, wherein the polysilicon can be provided in ion implantation in accordance with a hard mask. According to an exemplary embodiment, the length of one or more field plates 606 may be adjusted during manufacture to adjust the breakdown voltage and the trigger voltage of the device. That is, the collapse and the trigger voltage may depend on the length of the one or more field plates 606. According to another exemplary embodiment, an anode 607 may be operatively coupled to the P+ doped plate 905, the N+ doped plate 904, and the plurality of field plates 606 of one of the plurality of P-wells 603a; Cathode 608 can be operatively coupled to the P+ doped plate 905, the N+ doped plate 904, and the plurality of field plates 606 of the other of the plurality of P-wells 603b. The gate structure 906 that may be formed between the plurality of N+ doped plates 904 may include a gate oxide layer and a layer of polysilicon, wherein similar to the plurality of field plates 606, the polysilicon may be implanted in accordance with ion implantation. A hard mask is provided. The plurality of gates 906 can enable collective operation of the plurality of distributed N+ doped plates 904.

As can be seen from Fig. 9, the provided structure can effectively form a plurality of BJT transistors 910a and 910b (in this example, there are twelve, that is, six anode side BJT transistors 910a and six cathodes). Side BJT transistor 910b). As shown, the plurality of anode side BJT transistors 910a and the plurality of collectors of the plurality of cathode side BJT transistors 910b (labeled "C" in FIG. 9) are effective according to the depicted structure. Ground connection. Furthermore, the plurality of anode side BJT transistors 910a and the plurality of bases of the plurality of cathode side BJT transistors 910b (labeled "B" in Fig. 9) are operatively connected to their respective P+ doping a plurality of emitters 905; and the plurality of anode side BJT transistors 910a and the plurality of cathode side BJT transistors 910b of the plurality of emitters (labeled "E" in Fig. 9) are operatively connected to their respective N+ doped plate 904.

As shown in Figures 10 and 11, respectively, in a positive ESD event, the six anode side transistors 910a can actually operate in accordance with two forward biased diodes 1010a, and in a negative In the ESD event, the six cathode side transistors 910b can actually operate in accordance with two forward biased diodes 1110b. Thus, during a positive or negative ESD event, the ESD current can be discharged by at least one forward biased diode and at least one NPN BJT at the same time.

Each of the embodiments depicted in Figures 6 through 11 can be fabricated via a similar process and using similar materials. In this regard, the material of the N+ buried layer 601 may be an N-epi, a deep N-type well, or a plurality of stacked N+ buried layers. The structure can be fabricated using any standard BCD process without additional masking. According to another exemplary embodiment, the structure can be fabricated using a non-elevation process, such as a three-well process. The structure can also be fabricated using a single layer polycrystalline or a two layer polycrystalline process. A partial oxidation (LOCOS) process can be used to fabricate at least a portion of the structure, such as fabricating the plurality of FOX portions 609. Alternatively, a shallow trench isolation (STI) process can be used, for example, to fabricate at least a portion of the structure (such as the plurality of FOX portions 609).

It will be appreciated that the configuration depicted in Figures 6 through 11 and indeed in accordance with other embodiments not depicted may operate in accordance with two isolated high voltage NMOSs 300a and 300b, which are highly isolated. The voltage NMOSs 300a and 300b are combined in a common N-type isolation region 301. That is, the substrate 600, the N+ buried layer 601, the N-well 602a, 602b, the P-well 603a, the one or more P+ plates 604, the one or more N+ plates 605, the plurality of fields The board 606, together with the plurality of gate structures 906 associated with the P-well 603a in accordance with some embodiments, can operate in accordance with a first isolated high voltage NMOS 300a. Similarly, the substrate 600, the N+ buried layer 601, the N-well 602c, 602b, the P-well 603b, the one or more P+ plates 604, the plurality of N+ plates 605, and the plurality of field plates 606 Together with the plurality of gate structures 906 associated with the P-well 603b in accordance with some embodiments, the second isolation high voltage NMOS 300b can operate. Therefore, the shared common N-type isolation region in which the first and second isolated high voltage NMOSs are combined includes an N-type well 602b. In FIGS. 6 to 11, the gates, sources, and drains of the plurality of high voltage NMOSs 300a and 300b are denoted as "G", "S", and "D", respectively.

Figure 12 contains a top graph 1200 depicting the breakdown voltage characteristics of an exemplary embodiment. As can be seen from the chart 1200, the breakdown voltage has an equal magnitude in the forward (positive) and reverse (negative) directions. The bottom graphs 1210 and 1220 illustrate the measured leakage currents 1211, 1221 between the anode 607 and the cathode 608 during positive and negative ESD stress experiments, respectively, and the measured ESD currents 1212, 1222 of an exemplary embodiment. As can be seen, both of the measured ESD currents 1212, 1222 exhibit a fast back 1231 indicating a successful ESD protection in both the positive and negative directions.

Thus, the exemplary embodiment can provide a relatively small size bidirectional bipolar junction transistor (BJT) for high voltage electrostatic discharge (ESD) protection. Moreover, the exemplary embodiment can be applied to a standard BCD process without the need for additional masking. Embodiments can also be applied to different high voltage BCD processes and provide different operating voltage related ESD protection in the same process by providing an N+ buried or N-well formulation. As such, high voltage ESD protection is often required for devices that are intended to be used at high voltage settings, and can provide such devices that can encounter ESD events in a relatively small size. Some embodiments can also be used for general direct current (DC) circuit operation. Additionally, ESD protection may be provided for such a device that is required to be bi-directional, such as in a motor driver circuit. In this regard, for example, embodiments may be operatively coupled between an input/output (I/O) pad of the motor driver circuit and a power pad so as to not cause irregularities during normal operation and are not introduced. Latch-up effects, while providing positive and negative high voltage ESD protection. The exemplary embodiment may also provide flexibility as the collapse and/or trigger voltage may be tunable by modifying the length of one or more field plates during manufacturing.

Numerous variations and other embodiments of the inventions set forth herein will be apparent to those skilled in the art in the <RTIgt; Therefore, it is to be understood that the invention is not limited to the specific embodiments disclosed, and the modifications and other embodiments are intended to be included within the scope of the following claims. In addition, while the above description and related drawings are illustrative of the embodiments in the context of the elements and/or functions of the exemplified combination, it should be understood that the components and/or functions of the various combinations may be Below the scope of the scope, provided by alternative embodiments. In this regard, elements and/or functions that are different from the combinations of those described above are also contemplated as being set forth in the following claims. Although specific terms are used herein, they are used in a generic and descriptive sense rather than a limitation.

100. . . Voltage controlled rectifier

101. . . P+ material

102. . . N-material

103. . . P type material

104. . . N+ material

150. . . Electrical equivalent diagram

161, 231, 1231. . . Quickly back

201. . . NPN bipolar transistor

202. . . Coupled N-type region

211, 410a, 510b, 710a, 810b, 1010a, 1110b. . . Forward biased diode

210. . . Forward direction

220. . . Reverse direction

300a, 300b. . . Isolated high voltage NMOS

301. . . Common isolation zone

310a, 310b, 610a, 610b, 910a, 910b. . . BJT transistor

311. . . Coupled collector

600. . . P-type substrate

601. . . N+ buried layer

602a, 602b, 602c, 602a-c. . . N-type well

603a, 603b. . . P-well

604, 904. . . N+ doped plate

605, 905. . . P+ doped plate

606. . . Field board

607. . . anode

608. . . cathode

609. . . Field oxide film portion

906. . . Gate structure

1211, 1221. . . Measured leakage current

1212, 1222. . . Measured ESD current

B. . . Base

C. . . Collector

E. . . Emitter

The embodiments of the present invention can be further understood by the following detailed description:

1a and 1b respectively illustrate a simplified diagram of a prior art SCR and its associated electrical characteristics;

2a and 2b are respectively a simplified diagram of an embodiment of the invention and its associated electrical characteristics;

3a and 3b illustrate an electrical circuit having electrical characteristics that are roughly equivalent to an embodiment of the present invention;

Figures 4a and 4b illustrate circuit representations depicted in Figures 2a and 2b under positive ESD stress;

Figures 5a and 5b illustrate circuit representations depicted in Figures 2a and 2b under negative ESD stress;

Figure 6 is a cross-sectional view showing the structure of an exemplary embodiment;

Figure 7 is a cross-sectional view showing the structure of an exemplary embodiment of positive ESD stress;

Figure 8 is a cross-sectional view showing the structure of an exemplary embodiment of the negative ESD stress;

Figure 9 is a cross-sectional view showing an exemplary embodiment having a multiple emitter structure;

Figure 10 is a cross-sectional view showing the multiple emitter exemplary embodiment under positive ESD stress;

11 is a cross-sectional view of the multiple emitter exemplary embodiment under negative ESD stress;

Figure 12 illustrates the breakdown voltage characteristics and experimental electrical characteristics of an exemplary embodiment.

300a, 300b. . . Isolated high voltage NMOS

301. . . Common isolation zone

600. . . P-type substrate

601. . . N+ buried layer

602a, 602b, 602c, 602a-c. . . N-type well

603a, 603b. . . P-well

604. . . N+ doped plate

605. . . P+ doped plate

606. . . Field board

607. . . anode

608. . . cathode

609. . . Field oxide film portion

610a, 610b. . . BJT transistor

B. . . Base

C. . . Collector

E. . . Emitter

Claims (37)

A bidirectional bipolar junction transistor (BJT) comprising:
a p-type substrate;
An N+ doped buried layer disposed adjacent to the substrate;
a first P-type well region disposed adjacent to the N+ doped buried layer;
a second P-type well region disposed adjacent to the N+ doped buried layer;
An N-type well region adjacent to the N+ doped buried layer and surrounding the first and second P-type well regions such that at least a portion of the N-type well region is interposed in the first and second P-wells Between well zones;
Second and third field oxide (FOX) portions disposed adjacent to the N-type well region; and second, third, and fourth field plates adjacent to the first FOX portion Providing that the second and third field plates are disposed adjacent to respective portions of the second FOX portion, and the fourth field plate is disposed adjacent to the third FOX portion;
Wherein each of the first and second P-type wells comprises at least one N+ doped plate and at least one P+ doped plate. The bidirectional bipolar junction transistor according to claim 1, wherein the first P-type well comprises first and second N+ doped plates and a first P+ doped plate, the first P+ doping a miscellaneous plate interposed between the first and second N+ doped plates and adjacent to the first and second N+ doped plates; and further wherein the second P-type well includes third and fourth An N+ doped plate and a second P+ doped plate, the second P+ doped plate being interposed between the third and the fourth N+ doped plates, adjacent to the third and the fourth N+ doping board. The bidirectional bipolar junction transistor according to claim 1, wherein the first P-type well comprises a first P+ doped plate, first, second, third and fourth N+ doped plates And the first and second gate structures, the first P+ doped plate being interposed between the second and third N+ doped plates and adjacent to the second and third N+ doped plates, The first gate structure is interposed between the first and second N+ doped plates and adjacent to the first and second N+ doped plates, and the second gate structure is inserted in the first Between the third and the fourth N+ doped plates, adjacent to the third and fourth N+ doped plates; and further wherein the second P-type well comprises a second P+ doped plate, fifth, a seventh and eighth N+ doped plate, and third and fourth gate structures, the second P+ doped plate being interposed between the sixth and the seventh N+ doped plates and adjacent to the a sixth and the seventh N+ doped plate, the third gate structure being interposed between the fifth and sixth N+ doped plates, adjacent to the fifth and sixth N+ doped plates, and The fourth gate structure is placed in Between the seventh and the eighth plate doped N +, and adjacent to the seventh and eighth of the N + doped plate. The bidirectional bipolar junction transistor of claim 3, wherein the plurality of gate structures comprise a polysilicon layer. The bidirectional bipolar junction transistor of claim 4, wherein the polysilicon layer is provided in ion implantation in accordance with a hard mask. The bidirectional bipolar junction transistor of claim 1, wherein the first, second, and third FOX portions are fabricated via a LOCOS process. The bidirectional bipolar junction transistor of claim 1, wherein the first, the second, and the third FOX portions are fabricated via a shallow trench isolation (STI) process. The bidirectional bipolar junction transistor according to claim 1, wherein the N+ buried layer comprises an n-type epitaxial layer. The bidirectional bipolar junction transistor of claim 1, wherein the N+ buried layer comprises a deep N-type well. The bidirectional bipolar junction transistor of claim 1, wherein the N+ buried layer comprises a plurality of stacked N+ buried layers. The bidirectional bipolar junction transistor of claim 1, wherein each P-type well comprises a stacked P-type well and a P+ buried layer. The bidirectional bipolar junction transistor of claim 1, wherein the plurality of P-type wells are manufactured via P-type implantation. The bidirectional bipolar junction transistor of claim 1, wherein the N-well region is fabricated via N-type implantation. The bidirectional bipolar junction transistor of claim 1, wherein the bidirectional BJT is fabricated via a single layer polycrystalline process. The bidirectional bipolar junction transistor of claim 1, wherein the bidirectional BJT is fabricated via a two-layer polycrystalline process. The bidirectional bipolar junction transistor of claim 1, wherein the bidirectional BJT is fabricated via a non-epilation process. The bidirectional bipolar junction transistor according to claim 16, wherein the non-epilation process comprises a three-well process. A circuit comprising a bidirectional high voltage electrostatic discharge (ESD) protection element, the bidirectional high voltage ESD protection element comprising:
a p-type substrate;
An N+ doped buried layer disposed adjacent to the substrate;
a first P-type well region disposed adjacent to the N+ doped buried layer;
a second P-type well region disposed adjacent to the N+ doped buried layer;
An N-type well region adjacent to the N+ doped buried layer and surrounding the first and second P-type well regions such that at least a portion of the N-type well region is interposed in the first and second P-wells Between well zones;
Second and third field oxide (FOX) portions disposed adjacent to the N-type well region; and second, third, and fourth field plates adjacent to the first FOX portion Providing that the second and third field plates are disposed adjacent to respective portions of the second FOX portion, and the fourth field plate is disposed adjacent to the third FOX portion;
Wherein each of the first and second P-type wells comprises at least one N+ doped plate and at least one P+ doped plate. The circuit of claim 18, wherein the bidirectional high voltage ESD protection component further comprises:
An anode operatively coupled to at least the N+ doped plate and the at least one P+ doped plate of the first P-type well; and a cathode operatively coupled to at least the second P-type well At least one N+ doped plate and the at least one P+ doped plate;
More particularly, the circuit includes a motor driver circuit including an input/output (I/O) pad and a power pad, the anode of the bidirectional high voltage ESD protection component or one of the cathodes being executable Grounded to the I/O pad, and the other of the anode or the cathode of the bidirectional high voltage ESD protection element is operatively coupled to the power pad. A semiconductor device comprising a first isolated high voltage n-channel metal oxide field effect transistor (HVNMOS) and a second isolated HVNMOS, wherein the first and second isolated HVNMOS are combined in a common N-well isolation region . A method of fabricating a bidirectional bipolar junction transistor (BJT) comprising the following steps:
Providing a substrate structure, wherein the substrate structure comprises a p-type substrate region and an N+ doped buried layer buried in the p-type substrate region;
Forming a first P-type well region, a second P-type well region and an N-type well region adjacent to the N+ doped buried layer in the p-type substrate region, wherein the N-type well region surrounds the first sum The second P-type well region such that at least a portion of the N-type well region is interposed between the first and second P-type well regions;
Forming at least one N+ doped plate and at least one P+ doped plate in each of the first and second P-type well regions;
Forming an oxide layer by processing the N-type well region, wherein the oxide layer comprises a first, a second, and a third field oxide (FOX) portion; and forming a first layer adjacent to the oxide layer a second, a third, and a fourth field plate, wherein the first field plate is formed adjacent to the first FOX portion, and the second and third field plates are adjacent to the second FOX portion A respective portion is formed, and the fourth field plate is formed adjacent to the third FOX portion. The method of claim 1, wherein the step of forming at least one N+ doped plate and at least one P+ doped plate in each of the first and second P-type well regions comprises sub-steps :
Forming a first and a second N+ doped plate in the first P-type well region, and forming a third and a fourth N+ doped plate in the second P-type well region;
Forming a first P+ doped plate in the first P-type well region and forming a second P+ doped plate in the second P-type well region, wherein:
The first P+ doped plate is interposed between the first and second N+ doped plates and adjacent to the first and second N+ doped plates; and the second P+ doped plate is inserted Between the third and the fourth N+ doped plates, and adjacent to the third and fourth N+ doped plates. The method of claim 21, wherein the step of forming at least one N+ doped plate and at least one P+ doped plate in each of the first and second P-type well regions comprises a sub-step :
Forming a first P+ doped plate in the first P-type well region and forming a second P+ doped plate in the second P-type well region;
Forming a first, a second, a third, and a fourth N+ doped plate in the first P-type well region, and forming a fifth, a sixth, and a first in the second P-type well region. a seventh and an eighth N+ doped plate; and forming a first and a second gate structure in the first P-type well region, and forming a third and a first in the second P-type well region Four gate structure, where:
The first P+ doped plate is interposed between the second and third N+ doped plates and adjacent to the second and third N+ doped plates;
The first gate structure is interposed between the first and second N+ doped plates and adjacent to the first and second N+ doped plates; and the second gate structure is inserted in the first And between the fourth N+ doped plate and adjacent to the third and the fourth N+ doped plates. The method of claim 23, wherein the plurality of gate structures comprise a polysilicon layer. The method of claim 24, wherein the forming the polysilicon layer is performed in accordance with a hard mask in ion implantation. The method of claim 21, wherein the forming the first, the second, and the third FOX portion is performed via a LOCOS process. The method of claim 21, wherein the forming the first, the second, and the third FOX portions is performed via a shallow trench isolation (STI) process. The method of claim 21, wherein the N+ buried layer comprises an n-type epitaxial layer. The method of claim 21, wherein the N+ buried layer comprises a deep N-type well. The method of claim 21, wherein the N+ buried layer comprises a plurality of stacked N+ buried layers. The method of claim 21, wherein each P-type well region comprises a stacked P-type well and a P+ buried layer. The method of claim 21, wherein the forming the plurality of P-well regions is performed via a P-type implant. The method of claim 21, wherein the forming the N-well region is performed via an N-type implant. The method of claim 21, wherein the manufacturing the bidirectional BJT is performed via a single layer polycrystalline process. The method of claim 21, wherein the manufacturing the bidirectional BJT is performed via a two-layer polycrystalline process. The method of claim 21, wherein the manufacturing the bidirectional BJT is performed via a non-epilation process. The method of claim 36, wherein the non-epilation process comprises a three-well process.