TWI491011B - Bi-directional triode thyristor for high voltage electrostatic discharge protection - Google Patents

Description

Bidirectional triode thyristor for high voltage electrostatic discharge protection

Embodiments of the present invention generally relate to semiconductor devices and, more particularly, to high voltage electrostatic discharge (ESD) protection for bidirectional triode thyristors.

In almost all aspects of the manufacture of electronic devices, there is currently a tendency to shrink the size of the device. Smaller cost electronic devices are more popular than large, bulky devices, especially when the two devices have substantially equal capabilities. Thus, the ability to fabricate devices with smaller components will obviously tend to facilitate the production of smaller assemblies of the aforementioned components. However, many modern electronic devices require electronic circuitry to perform startup functions (such as switching devices) and data processing or other decision functions simultaneously. The use of low voltage complementary metal oxide semiconductors (CMOS) for these dual functions is not always practical. High voltage (or high power) devices are thus developed to handle many applications that are not suitable for low voltage operation.

The electrostatic discharge (ESD) performance of a typical high voltage device typically depends on the overall width and surface area or lateral dimension of the corresponding device. Therefore, ESD performance is often more critical for smaller devices. High voltage devices typically have the following characteristics: a low on-state resistance (Rdson), a high breakdown voltage, and a low hold voltage. Among certain ESD events, this low on-state resistance can make it easier for ESD current to concentrate on its surface or the edge of the drain. High currents and high electric fields can cause physical damage to the surface interface of the device. This surface or lateral dimension may not be increased based on the requirements of a typical low on-state resistance. Therefore, ESD protection can be challenging.

The high breakdown voltage characteristic of the high voltage device generally represents that the breakdown voltage is higher than the operating voltage, and the trigger voltage (vt1) is higher than the breakdown voltage. Therefore, during an ESD event, the high voltage device internal circuit is likely to exist before the high voltage device turns on ESD protection. The risk of damage. This low hold voltage of the high voltage device also has the potential that during normal operation, unwanted noise associated with a peak voltage or a surge voltage can be triggered or latched. In ESD events, the high voltage device is also sensitive to the path so that the ESD current can be easily concentrated at the surface or the edge of the drain.

In order to improve the performance of high voltage devices during ESD events, one technology has been implemented to include additional masks; the other is to form larger sized diodes and/or add MOS in bipolar junction transistors (BJT). The surface area of the transistor or the dimension of the side. In the case of ESD events, controlled rectifiers (SCRs) have also been developed to protect circuits. However, the low hold voltage of the SCRs represents that they can be better executed in an ESD event, which improves the incidence of latch-up effects during normal operation.

With existing solutions, motor driver circuits can be particularly plagued by the protection of ESD events. This is because when the motor is turned off, it can continue to rotate for a certain period of time, so that a negative voltage is fed back as an inductor. If the motor driver circuit includes a PMOS, the parasitic forward biased diode of the PMOS can be turned on by the negative feedback voltage, potentially causing latch-up problems and/or other irregular circuit operations.

Therefore, it is expected to develop an improved structure to provide ESD protection, especially for providing two-way ESD protection.

Some exemplary embodiments therefore focus on a bidirectional triode thyristor (also referred to as "TRIAC" (triode for alternating current)) for high voltage electrostatic discharge (ESD) protection. In some cases, the ESD protection can be based, at least in part, on a modification of a bipolar complementary metal oxide semiconductor (BiCMOS) diffusion metal oxide semiconductor (DMOS) process (Bipolar-CMOS-DMOS, BCD process). The BCD process can involve an epitaxial process.

In an exemplary embodiment, a TRIAC is provided (as used herein, "example" means, by way of example, example or illustration), the TRIAC includes a P-type substrate, an N ⁺ doped buried layer, an N-type well region, and Two P-type well areas. The N ⁺ doped buried layer can be disposed adjacent to the substrate. The N-type well region may be disposed adjacent to the N ⁺ doped buried layer and surrounding the first and second P-type well regions such that an intermediate portion of the N-type well region is inserted in the first and the Between the second P-wells. The P-well region may be disposed adjacent to the N ⁺ doped buried layer, and each P-well region may include one or more N ⁺ doped plates and one or more P ⁺ doped plates, respectively. The intermediate portion of the N-well region may include at least one P-shaped portion.

According to a further embodiment, the P-well region comprises three N ⁺ doped plates, two P ⁺ doped plates, and two gate structures. For each P-well, the three N ⁺ doped plates, the two P ⁺ doped plates, and the two gate structures can be configured such that a first P-doped plate is disposed adjacent to one a first N ⁺ doped plate, a first gate structure disposed between the first and second N ⁺ doped plates, and a second gate structure disposed on the second and a third N ⁺ doped plate Between and a second P ⁺ doped plate is disposed adjacent to the third N ⁺ doped plate.

In another exemplary embodiment, a circuit is provided that includes a TRIAC high voltage electrostatic discharge protection component. The TRIAC high voltage ESD protection component comprises a P-type substrate, an N ⁺ doped buried layer, an N-type well region and two P-type well regions. The N ⁺ doped buried layer may be disposed adjacent to the substrate. The N-type well region may be disposed adjacent to the N ⁺ doped buried layer and surrounding the first and second P-type well regions such that a portion of the N-type well region is disposed in the first and second P-type well regions in. The intermediate portion of the N-type well region may include: at least one P-type portion. The P-well region may be adjacent to the N ⁺ doped buried layer, and each N-well region may include one or more N ⁺ doped plates and one or more P ⁺ doped plates, respectively. The P-well region can include three N ⁺ doped plates, two P ⁺ doped plates, and two gate structures. For each P-well, the three N ⁺ doped plates, the two P ⁺ doped plates, and the two gate structures can be configured such that a first P ⁺ doped plate is disposed adjacent to a first An N ⁺ doped plate, a first gate structure is disposed between the first and second N ⁺ doped plates, and a second gate structure is disposed between the second and a third N ⁺ doped plates And a second P ⁺ doped plate is disposed adjacent to the third N ⁺ doped plate.

In accordance with another exemplary embodiment, a semiconductor device is provided comprising: a first high voltage thyristor and a second high voltage thyristor and the first and second thyristors sharing a common N-well region.

101a‧‧‧Gate control circuit

101b‧‧‧Gate control circuit

100a‧‧‧NPN BJT

100b‧‧‧NPN BJT

110a‧‧‧PNP BJT

110b‧‧‧PNP BJT

200a‧‧‧NPN BJT

200b‧‧‧NPN BJT

210a‧‧‧PNP BJT

210b‧‧‧PNP BJT

220a‧‧‧ Forward biased diode

220b‧‧‧ Forward biased diode

P-SUB 300‧‧‧P type material substrate

P-EPI 300‧‧‧P epitaxial layer

301‧‧‧N ⁺ buried layer

302a‧‧‧N type well

302b‧‧‧N type well

302c‧‧‧N type well

303a‧‧‧First P-well

303b‧‧‧Second P-well

304‧‧‧P ⁺ doped plate

304a‧‧P ⁺ doped plate

305‧‧‧N ⁺ doped plate

306‧‧‧ gate structure

307‧‧‧Anode

308‧‧‧ cathode

309‧‧‧ field oxide film part

310a‧‧‧Anode-side transistor

310b‧‧‧Cathode side transistor

311a‧‧‧ Forward biased diode

320‧‧‧PNP BJT

404‧‧‧P type (P-type implant)

506‧‧‧ field board

711, 721‧‧‧ leakage current

712, 722‧‧‧Measured ESD current

731‧‧‧ Jump back

The invention has been described generally, and the drawings are not necessarily to scale. And where:

Figure 1 depicts a simplified circuit diagram representation of a conventional two-phase AC triode (TRIAC).

2a is a simplified diagram of an embodiment of the invention; and FIGS. 2b and 2c respectively show a simplified diagram of an embodiment of the invention under positive and negative electrostatic discharge (ESD) stress.

3a is a cross-sectional view showing the structure of an exemplary embodiment; and FIGS. 3b and 3c are cross-sectional views showing the structure of an embodiment of the present invention under forward and negative electrostatic discharge (ESD) stress, respectively.

4a is a cross-sectional view showing the structure of an exemplary embodiment; and FIGS. 4b and 4c are cross-sectional views showing the structure of an embodiment of the present invention under forward and negative electrostatic discharge (ESD) stress, respectively.

Figure 5a is a cross-sectional view showing the structure of an exemplary embodiment; Figures 5b and 5c are cross-sectional views showing the structure of an embodiment of the present invention under forward and negative electrostatic discharge (ESD) stress, respectively.

6a is a cross-sectional view showing the structure of an exemplary embodiment; and FIGS. 6b and 6c are cross-sectional views showing the structure of an embodiment of the present invention under forward and negative electrostatic discharge (ESD) stress, respectively.

FIG. 7 illustrates breakdown voltage characteristics and test electrical characteristics of an exemplary embodiment.

Some exemplary embodiments of the present invention, which will be more fully described below, will appear in some but not all embodiments of the present invention with reference to the accompanying drawings. In fact, the exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments herein; rather, these exemplary embodiments will satisfy the requirements of the legality of the application.

Some exemplary embodiments of the present invention may provide a bidirectional triode sluice fluid (also referred to as "TRIAC" (triode for alternating current)), for example, for bidirectional high voltage electrostatic discharge (ESD) protection, such as guard positive And negative voltage ESD. The TRIAC of the exemplary embodiment can combine two high voltage thyristors into one ESD guard, thereby providing a structure; according to an exemplary embodiment, the total area of the structure is less than the diode-BJT and MOS, while being provided in two Directional, similar ESD performance. The exemplary embodiment may also have a breakdown voltage proximate to the operating voltage of the high voltage device and a trigger voltage that is lower than the breakdown voltage of the high voltage device. In addition, the relatively high holding voltage provided can more easily avoid latch-ups than existing pilot-controlled rectifiers (SCRs). For example, by allowing adjustment of various electrical characteristics during manufacturing, demonstration implementation Examples can provide flexibility. For example, adjusting the breakdown voltage and the trigger voltage by adjusting the length of one or more field plates disposed adjacent to the plurality of field oxide (FOX) portions, and/or adjusting the hold voltage by adjusting the width of the N-type well . Embodiments of the present invention may also be configured for early turn-on by providing additional bias voltages in the gate or polysilicon of the multiple emitter structure.

Exemplary embodiments may also, for example, eliminate the need for conventional TRIACs for the required gating circuits. For example, the exemplary embodiment can be used with a motor driver circuit, such as between an I/O pad and a power pad. In this case, the exemplary embodiment can provide forward and negative high voltage electrostatic discharge protection without causing irregularities during normal operation or causing latch-up problems. Embodiments may also include, for example, for system level surge voltage protection on a wafer. In some cases, embodiments may also be fabricated using standard BCD processes without the need to add a greater number of masks or processes. The polysilicon used in some exemplary embodiments can be provided, for example, by ion implantation by a hard mask.

Figure 1 depicts a simplified circuit diagram representation of a conventional two-phase AC triode (TRIAC). 1 shows that the conventional TRIAC can have the following composition and is arranged as shown: two NPN BJTs 100a, 100b; two PNP BJTs 110a, 110b; and two gate circuits 101a, 101b. In contrast, Figure 2a depicts a simplified circuit diagram representation of an embodiment of the present invention. Referring to Fig. 2a, embodiments of the invention may have the following composition and are arranged as shown: two NPN BJTs 200a, 200b and two PNP BJTs 210a, 210b. NPN and PNP BJTs can be, for example, high voltage NPN and PNP BJTs. As shown, the exemplary embodiment may also, for example, eliminate the need for conventional TRIACs for the desired gating circuit in FIG. Thus, embodiments of the present invention can substantially provide the benefit of reduced area and complexity by eliminating the need for relatively large and complex gated circuits for conventional TRIACs.

Figures 2b and 2c illustrate electrical characteristics of an embodiment of the invention, respectively, under stresses of forward and negative electrostatic discharge (ESD). As seen in Figure 2b, the top NPN BJT transistor 200a can function as a forward biased diode 220a under forward ESD stress. As can be seen in Figure 2c, under negative ESD stress, the bottom NPN BJT transistor 200b can function as a forward biased diode 220b. Thus, whether applying positive or negative ESD stress, embodiments of the present invention ensure that the ESD current has been discharged, thereby providing bidirectional ESD protection. Exemplary embodiments of the same or different forward and reverse collapse voltages can be generated by using thyristor fluids having the same or different breakdown voltages.

Having described the general electrical features and characteristics of an exemplary embodiment of the present invention, reference is made to Figures 6-8 to describe the structure of an exemplary embodiment.

Figure 3a depicts a cross-sectional view of a first exemplary embodiment of a TRIAC for high voltage electrostatic discharge (ESD) protection. As can be seen from Fig. 3a, a P-type material substrate 300 (P-SUB) or a P epitaxial layer (P-EPI) can be provided. The N ⁺ doped buried layer 301 may be disposed adjacent to the P-type material substrate 300 (P-SUB) or the P epitaxial layer (P-EPI). N-type wells 302a-c may be adjacent to N ⁺ doped buried layer 301 and disposed around first and second P-type wells 303a and 303b such that a portion 302b of the N-type well is inserted into the first P-type well Between 303a and the second P-well 303b. And according to some embodiments, the N-wells 302a-c can be a single connected well, or according to another embodiment, can include two or more independent N-wells. According to an exemplary embodiment, the outside of the N-type wells 302a and 302c may be in contact with the P-type substrate 300. The first P-well 303a and the second P-well 303b may include at least one P ⁺ doped plate 304 and at least one N ⁺ doped plate 305. The portion of the N-well 302b between the first P-well 303a and the second P-well 303b may include at least one P ⁺ doped plate 304a.

For example, according to the exemplary embodiment shown in FIG. 3a, the first P-well 303a and the second P-well 303b may each include two P ⁺ doped plates 304, three N ⁺ doped plates 305, and two Gate structure 306. Therefore, as shown, the first P-well 303a can include a first P ⁺ doped plate 304, a first gate structure 306, a second gate structure 306, and a second P ⁺ doping. a plate 304; the first P ⁺ doped plate 304 may be disposed adjacent to the first N ⁺ doped plate 305; the first gate structure 306 may be inserted in the first and a second N ⁺ doped Between the miscellaneous plates 305; the second gate structure 306 can be interposed between the second and a third N ⁺ doped plates 305; and the second P ⁺ doped plate 304 can be adjacent to a third N ⁺ Doped plate 305 is provided. Similarly, the second P-well 303b can include a third P ⁺ doped plate 304, a third gate structure 306, a fourth gate structure, and a fourth P ⁺ doped plate 304; P ⁺ doped plate 304 may be disposed adjacent to a fourth N ⁺ doped plate 305 ; the third gate structure 306 may be interposed between the fourth and fifth N ⁺ doped plates 305; A fourth gate structure may be interposed between the fifth and sixth N ⁺ doped plates 305; and the fourth P ⁺ doped plate 304 may be adjacent to the sixth N ⁺ doped plate 305 Settings. The portion of the N-well 302b between the first P-well 303a and the second P-well 303b can include a P ⁺ doped plate 304a. According to another exemplary embodiment, an anode 307 may be operatively coupled to the P ⁺ doped plate 304, the N ⁺ doped plate 305, and the gate structure 306 of one of the plurality of P-wells 303a, And a cathode 308 can be operatively coupled to the P ⁺ doped plate 304, the N ⁺ doped plate 305, and the gate structure 306 of the other of the plurality of P-wells 303b.

The gate structure 306, which may be formed between a plurality of N ⁺ doped plates 305, may include a gate oxide layer and a layer of polysilicon, wherein, for example, the polysilicon may be provided in ion implantation in accordance with a hard mask. The gate structure 306 can enable collective operation of the plurality of dispersed N ⁺ doped plates 305. A plurality of field oxide film (FOX) portions 309 can be disposed adjacent to the surface of portions of the N-wells 302a-c and adjacent to the distal end of each P ⁺ doped plate 304.

As can be seen from Figures 3a-3c, a plurality of NPN BJT transistors 310a and 310b (eight in this example, four anode sides 310a and four cathode sides 310b) and a plurality of PNP bipolar transistors 320 (in this example) Four of them can be effectively formed and illustrated by the structural arrangement provided. As shown in Figure 3b, at the forward ESD event, the anode side transistor 310a can actually operate as a forward biased diode 311a. As shown in FIG. 3c, in the negative ESD event, the cathode side transistor 311b can actually operate as the forward biased diode 311b. Thus, in a positive or negative ESD event, the ESD current can be simultaneously discharged by biasing the diode and the thyristor in the forward direction.

Figure 4a illustrates a cross-sectional view of a second exemplary embodiment of a TRIAC for high voltage electrostatic discharge protection. As can be seen from FIG. 4a, the second embodiment is similar to that of FIG. 3 except that the P-type portion 404 disposed adjacent to the portion of the N-well 302b includes a P-type implant instead of the P ⁺ doped plate. A first embodiment is described above, wherein a portion of the N-well 302b is interposed between the first P-well 303a and the second P-well 303b. As can be seen from Figures 4b and 4c, during the forward or negative ESD event, the behavior of the second embodiment remains similar with: the anode side transistor 310a is biased in the forward direction during a forward ESD event. 311a operates; and during a negative ESD event, the cathode side transistor 311b operates in the forward biasing diode 311b.

Figure 5a illustrates a cross-sectional view of a third exemplary embodiment of a TRIAC for high voltage electrostatic discharge protection. As can be seen from Figure 5a, this third embodiment is similar to Figure 3a and the first embodiment mentioned above. In the third embodiment, the P ⁺ doped plate 304a disposed adjacent to the portion of the N-well 302b includes a P ⁺ doped plate interposed between the first P-well 303a, between the second P-type well 303b. However, unlike the first embodiment, a plurality of field plates 506 disposed adjacent to the plurality of FOX portions 309 are further included in the third embodiment. As mentioned previously, the breakdown voltage and trigger voltage of the TRIAC can be adjusted by manipulating the width of these field plates 506 during manufacturing. As can be seen from Figures 5b and 5c, during the forward and negative ESD events, the third embodiment behaves similarly to the first and second embodiments with the anode side transistor 310a in a forward ESD event. The operation is performed in accordance with the forward biasing diode 311a; in a negative ESD event, the cathode side transistor 311b operates in the forward biasing of the diode 311b.

Figure 6a depicts a cross-sectional view of a fourth exemplary embodiment of a TRIAC for high voltage electrostatic discharge protection. As can be seen from Figure 6a, the fourth embodiment is similar to Figure 4a and the second embodiment mentioned above. In the fourth embodiment, the P ⁺ doped plate 304a disposed adjacent to the portion of the N-well 302b includes a P-type implant instead of a P ⁺ doped plate, and the N-type well 302b is interposed Between the first P-well 303a and the second P-well 303b. However, similar to the third embodiment described above, a plurality of field plates 506 adjacent to the plurality of FOX portions 309 are also included in the fourth embodiment. As can be seen from Figures 6b and 6c, during the forward and negative ESD events, the fourth embodiment behaves similarly to the first, second and third embodiments and has: in a forward ESD event, the anode side transistor 310a operates in accordance with the forward biasing diode 311a; in a negative ESD event, the cathode side transistor 311b operates in the forward biasing diode 311b.

It will be understood that the configuration shown in Figures 3a-6c and indeed in accordance with the configuration of other embodiments not described, may represent two thyristors, for example, a forward and a reverse high voltage thyristor. The two thyristors have been combined into one device such that the thyristors share a common N-type well region 302b. Thus, embodiments of the present invention may share a common N-type region 302b. That is, the substrate 300, the N ⁺ doped buried layer 301, portions of the N-type wells 302a and 302b, the P-type portion, and the plurality of P ⁺ doped plates associated with the first P-type well 303a 304. The plurality of N ⁺ doped plates 305 and the plurality of gate structures 306 can operate in accordance with a first high voltage thyristor. Similarly, the substrate 300, the N ⁺ doped buried layer 301, portions of the N-type wells 302c, 302b, the second P-well 303b, and the plurality of associated with the second P-well 303b The P ⁺ doped plate 304, the plurality of N ⁺ doped plates 305, and the plurality of gate structures 306 can operate in accordance with a second high voltage thyristor. Thus, the portion of the N-well 302b between the first P-type region 303a and the second P-type region 303b can include a common N-type region. It will be appreciated that this configuration results in a device having a plurality of electrical characteristics that are compatible with two thyristors (e.g., a forward and a reverse high voltage thyristor) that have been connected in series. Compared.

A number of exemplary embodiments of TRIACs for high voltage ESD protection have been described, and various methods and materials that can be used to fabricate various embodiments are now described. In this regard, the material of the N ⁺ buried layer 601 may be an N epitaxial (N-epi), a deep N-type well, or a plurality of stacked N ⁺ buried layers. The P-wells 603a and 603b may be stacked using a P-type well and a P ⁺ buried layer, or a P implant. In some cases, the N-wells 602a-c can also be N-type implants. Exemplary embodiments can be fabricated using any standard BCD process without additional masking. Exemplary embodiments may also or alternatively be fabricated using a non-evaporation process (eg, a three-well process or a single-layer poly-crystal process or a two-layer poly-crystal process). A ruthenium local oxidation (LOCOS) process can be used to fabricate at least a portion of the structure, such as fabricating the plurality of FOX portions 309. Alternatively, a shallow trench isolation (STI) process can be used, such as to fabricate at least a portion of the structure (such as the plurality of FOX portions 309). The plurality of field plates 506 can be polycrystalline germanium, metal or stacked multi-polysilicon and metal. With respect to Embodiments 1 and 3, respectively, which are depicted in Figures 3a and 5a, for example, the P ⁺ doped plate is disposed adjacent to the common N-well region 302b and the P ⁺ doped plate can be diffused by diffusion. The process is made, such as by an opening between the plurality of adjacent FOX portions 309. Thus, the P ⁺ doped plate can be fabricated by diffusing a heavily P ⁺ doped material to the N-type material of the common N-well region 302b. About are depicted in FIGS. 4a and 6a in Examples 2 and 4, the P-type implant may include any type of P-type carriers, for example, P ^- or P ^+. For example, the P-type implant 404 can be implanted through the FOX 309 or can be implanted prior to the FOX portion 309 being fabricated. For example, the depth of the P-type implant corresponds to the depth of the N-type and/or the P-type well. As indicated above, various adjustments can be made to change the plurality of electrical characteristics of the exemplary embodiment. For example, the collapse and trigger voltages can be adjusted by adjusting the length of the plurality of field plates 506 disposed adjacent to the plurality of FOX portions 309. The holding voltage can also be adjusted by adjusting the width of the N-wells 302a-c. Additionally, when implemented in a circuit, early turn-on can be achieved by applying an additional bias voltage to one or more gates of the multiple emitter structure or the polysilicon.

FIG. 7 includes an uppermost graph 700 depicting a plurality of breakdown voltage characteristics of an exemplary embodiment. As can be seen from the graph 700, the collapse voltage can be of equal magnitude in both the forward (forward) and reverse (negative) directions. The bottom graphs 710, 720 are shown in the forward and negative ESD stresses, respectively. Leakage currents 711, 721 and measured ESD currents 712, 722 measured between the anode 307 and the cathode 308 in an exemplary embodiment during the experiment. It can be seen that both of the measured ESD currents 712, 722 exhibit a jumpback 731 indicating successful triggering of the respective thyristor and thus successful ESD protection in the positive and negative directions.

The exemplary embodiment thus provides a relatively small sized TRIAC for high voltage electrostatic discharge (ESD) protection without the need for conventional TRIACs gated circuits. Again, the exemplary embodiments can be applied to standard BCD processes without the need for additional masks. Embodiments can also be applied to different high voltage BCD processes by providing an N ⁺ buried layer or N-well method to provide different operating voltage related ESD protection in the same process. In this way, devices used in high voltage settings may encounter ESD events, providing the high voltage ESD protection often required by the device in a relatively small size. Some embodiments can also be used for system level surge voltage protection on a wafer, even for general DC circuit operation. In addition, ESD protection can be provided to devices that require bidirectional protection, such as motor driver circuits. In this regard, embodiments may be operatively coupled between the input/output pads of the motor driver circuit and the power pad, for example, to provide positive and negative high voltage electrostatic discharge without causing or inducing irregular operation or latching problems. Protection.

Other embodiments and many modifications of the inventions set forth herein will be apparent to those skilled in the art, which, however, are directed to the teachings set forth herein. Therefore, it is understood that the invention is not limited to the specific embodiments disclosed, and the modifications and other embodiments are included in the scope of the appended claims. An exemplary embodiment incorporating exemplary combinations of certain elements and/or functions, it being understood that combinations of different elements and/or functions may be provided by different embodiments without departing from the appended claims. range. In this regard, various combinations of elements and/or functions are also included in some of the derived claims, for example, not only as specifically described above. Although specific nouns are used herein, they are used for general purposes only and are not intended to be limiting.

P-SUB 300‧‧‧P type material substrate

P-EPI 300‧‧‧P epitaxial layer

301‧‧‧N ⁺ doped buried layer

302a‧‧‧N type well

302b‧‧‧N type well

302c‧‧‧N type well

303a‧‧‧First P-well

303b‧‧‧Second P-well

304‧‧‧P ⁺ doped plate

304a‧‧P ⁺ doped plate

305‧‧‧N ⁺ doped plate

306‧‧‧ gate structure

307‧‧‧Anode

308‧‧‧ cathode

309‧‧‧ field oxide film part

310a‧‧‧Anode-side transistor

310b‧‧‧Cathode side transistor

Claims (21)

A semiconductor device comprising: a P-type substrate; an N ⁺ -doped buried layer disposed adjacent to the P-type substrate; a first P-type well region disposed adjacent to the N ⁺ -doped buried layer; a second P-type well region disposed adjacent to the N ⁺ doped buried layer; and an N-type well region adjacent to the N ⁺ doped buried layer and surrounding the first and second P-type wells a region such that at least a portion of the N-type well region is interposed between the first and second P-type well regions; wherein the N-type is interposed between the first and second P-type well regions The portion of the well region includes a P-type portion; wherein the first P-type well includes first, second, and third N ⁺ doped plates, first and second P ⁺ doped plates, and first and second portions a gate structure, the first P ⁺ doped plate is disposed adjacent to the first N ⁺ doped plate, and the first gate structure is interposed between the first and the second N ⁺ doped plates The second gate structure is interposed between the second and the third N ⁺ doped plates, and the second P ⁺ doped plate is disposed adjacent to the third N ⁺ doped plate; Where the second P-type well comprises a fourth, fifth and a sixth N ⁺ doped plate, third and fourth P ⁺ doped plates, and third and fourth gate structures, the third P ⁺ doped plate being disposed adjacent to the fourth N ⁺ doped plate The third gate structure is interposed between the fourth and the fifth N ⁺ doped plates, and the fourth gate structure is interposed between the fifth and the sixth N ⁺ doped plates, and The fourth P ⁺ doped plate is disposed adjacent to the sixth N ⁺ doped plate. The semiconductor device of claim 1, wherein the P-type portion comprises a fifth P ⁺ doped plate. The semiconductor device of claim 1, wherein the P-type portion comprises a P-type implant portion. The semiconductor device of claim 1, further comprising first, second and third field oxide (FOX) portions disposed adjacent to the N-type well region. The semiconductor device of claim 4, wherein the first FOX portion is disposed further adjacent to the first P ⁺ doped plate, the second FOX portion is disposed adjacent to the P-type portion and is disposed Between the second and the third P ⁺ doped plates, and the third FOX portion is disposed adjacent to the fourth P ⁺ doped plate. The semiconductor device of claim 4, further comprising a fourth field oxide (FOX) portion disposed adjacent to the N-type well region, wherein the first FOX portion is further adjacent to the first P ⁺ doping a chip is disposed, the second FOX portion is further disposed between the second and the fifth P ⁺ doped plates, the third FOX portion being more adjacent to the P portion and the third P ⁺ doping A plate is provided, and the fourth FOX portion is disposed closer to the third P ⁺ doped plate. The semiconductor device of claim 4, further comprising a field plate disposed adjacent to the plurality of FOX portions. The semiconductor device of claim 1, wherein at least one of the first, second, third, and fourth gate structures comprises a polysilicon layer. The semiconductor device of claim 1, wherein the N ⁺ doped buried layer comprises an N-type epitaxial layer. The semiconductor device of claim 1, wherein the N ⁺ doped buried layer comprises a deep N-type well. The semiconductor device of claim 1, wherein the N ⁺ -doped buried layer comprises a plurality of stacked N ⁺ -doped buried layers. A semiconductor device according to claim 1, wherein each P-type well comprises a stacked P-type well and a P ⁺ buried layer. The semiconductor device of claim 1, wherein the plurality of P-type wells are manufactured by P-type implantation. The semiconductor device of claim 1, wherein the N-well region is fabricated by N-type implantation. The semiconductor device of claim 1, further comprising a first bidirectional BJT, wherein the first bidirectional BJT is fabricated by a single layer polycrystalline process. The semiconductor device of claim 1, further comprising a second bidirectional BJT, wherein the second bidirectional BJT is fabricated by a two-layer polycrystalline process. The semiconductor device of claim 1, further comprising a third bidirectional BJT, wherein the third bidirectional BJT is fabricated by a non-epilation process. A circuit comprising a semiconductor device, the semiconductor device comprising: a P-type substrate; an N ⁺ doped buried layer disposed adjacent to the P-type substrate; a first P-type well region adjacent to the N ⁺ doping a buried layer is disposed; a second P-type well region is disposed adjacent to the N ⁺ doped buried layer; and an N-type well region adjacent to the N ⁺ -doped buried layer and surrounding the first And the second P-type well region such that at least a portion of the N-type well region is interposed between the first and second P-type well regions; wherein the first and second P-type well regions are interposed The portion of the N-well region between the includes a P-type portion; wherein the first P-well includes first, second, and third N ⁺ doped plates, first and second P ⁺ doped plates, And first and second gate structures, the first P ⁺ doped plate being disposed adjacent to the first N ⁺ doped plate, the first gate structure being disposed in the first and the second N ⁺ Between the doped plates, the second gate structure is interposed between the second and the third N ⁺ doped plates, and the second P ⁺ doped plate is adjacent to the third N ⁺ doped plate Is set; and more in it P-type well comprises a fourth, fifth and sixth N ⁺ doped plate, third and fourth P ⁺ doped plate, and third and fourth gate structure, the third P ⁺ doped adjacent to the plate a fourth N ⁺ doped plate is disposed, the third gate structure is interposed between the fourth and the fifth N ⁺ doped plates, and the fourth gate structure is inserted in the fifth and the first Between the six N ⁺ doped plates, and the fourth P ⁺ doped plate is disposed adjacent to the sixth N ⁺ doped plate. The circuit of claim 18, wherein the circuit comprises a motor driver circuit, the motor driver circuit comprising an input/output (I/O) pad and a power pad; and further wherein the semiconductor device further comprises: An anode operatively coupled to the first, second and third N ⁺ doped plates, the first and second P ⁺ doped plates, and the first and second gate structures, and a cathode operatively coupled to the fourth, fifth and sixth N ⁺ doped plates, the third and fourth P ⁺ doped plates, and the third and fourth gate structures; More preferably, one of the anode or cathode of the semiconductor device is operatively coupled to the I/O pad, and the other of the anode or cathode of the semiconductor device is operatively coupled to the power pad. A semiconductor device comprising a first high voltage thyristor and a second high voltage thyristor, wherein the isolated first and second high voltage thyristors share a common N-type well region adjacent to the common N-type well region Buried at an N ⁺ doped layer and surrounding a first and a second P-type well region such that at least a portion of the common N-type well region is interposed between the first and second P-type well regions The portion of the common N-type well region interposed between the first and second P-type well regions includes a P-type portion; wherein the first P-type well includes first, second, and third portions An N ⁺ doped plate, first and second P ⁺ doped plates, and first and second gate structures, the first P ⁺ doped plate being disposed adjacent to the first N ⁺ doped plate, a first gate structure is interposed between the first and the second N ⁺ doped plates, the second gate structure is interposed between the second and the third N ⁺ doped plates, and the first a second P ⁺ doped plate disposed adjacent to the third N ⁺ doped plate; and further wherein the second P-type well includes fourth, fifth, and sixth N ⁺ doped plates, third and fourth P ⁺ doped plate, And third and fourth gate structures, the third P ⁺ doped plate being disposed adjacent to the fourth N ⁺ doped plate, the third gate structure being interposed in the fourth and the fifth N ⁺ Between the doped plates, the fourth gate structure is interposed between the fifth and the sixth N ⁺ doped plates, and the fourth P ⁺ doped plate is adjacent to the sixth N ⁺ doped plate be set to. A method of fabricating a semiconductor device, comprising: providing a P-type substrate; disposing an N ⁺ doped buried layer such that the N ⁺ doped buried layer is adjacent to the P-type substrate; and providing a first P-type well region, such that a first P-type well region is adjacent to the N ⁺ doped buried layer; a second P-type well region is disposed such that the second P-type well region is adjacent to the N ⁺ -doped buried layer; and an N-type well region is disposed Adjacent to the N ⁺ doped buried layer and surrounding the first and second P-type well regions such that at least a portion of the N-type well region is interposed in the first and second P-type well regions The portion of the N-type well region interposed between the first and the second P-type well region includes a P-type portion; wherein the first P-type well includes first, second, and a three N ⁺ doped plate, first and second P ⁺ doped plates, and first and second gate structures, the first P ⁺ doped plate being disposed adjacent to the first N ⁺ doped plate, The first gate structure is interposed between the first and the second N ⁺ doped plates, and the second gate structure is interposed between the second and the third N ⁺ doped plates, and the the second P ⁺ doped adjacent to the first plate N ⁺ doped plate is provided; and further wherein the second P-type well comprises a fourth, fifth and sixth N ⁺ doped plate, third and fourth P ⁺ doped plate, and the second and third a fourth gate structure, the third P ⁺ doped plate being disposed adjacent to the fourth N ⁺ doped plate, the third gate structure being interposed between the fourth and the fifth N ⁺ doped plates The fourth gate structure is interposed between the fifth and the sixth N ⁺ doped plates, and the fourth P ⁺ doped plate is disposed adjacent to the sixth N ⁺ doped plate.