TW202245252A - Semiconductor device - Google Patents

Abstract

A semiconductor device is provided herein, which includes a semiconductor substrate, a first well, a second well, a field oxide layer, and a polysilicon layer. The semiconductor substrate has a first conductivity type. The first well is deposited in the semiconductor substrate and has a second conductivity type. The second well is formed in the first well and has the first conductivity type. The field oxide layer is deposited on the second well. The polysilicon layer is deposited on the field oxide layer, and a resistance device is formed by the polysilicon layer.

Description

Semiconductor device

The present invention relates to a semiconductor device, in particular to a semiconductor device which increases the withstand voltage of a resistance element and protects against electrostatic discharge.

With the development of high-voltage integrated circuits, especially for some alternating current to direct current (AC-DC) circuits used for high-voltage alternating current, some resistive elements need to withstand high voltages of hundreds of volts. However, before the high voltage of hundreds of volts, the traditional high-voltage resistance element may first encounter the problem of element breakdown, so that the traditional resistance can no longer meet the demand.

By fabricating polysilicon resistors on the field oxide layer, the withstand voltage can be greatly improved, and the withstand voltage mainly depends on the thickness of the field oxide layer. The withstand voltage of the field oxide layer in the general process can reach 300-400V. However, for the AC-to-DC circuit of high-voltage AC, the highest peak voltage accepted by the resistance element may be as high as 500-650V, which makes the polysilicon resistor unable to meet the demand. Therefore, it is necessary to improve the withstand voltage of the resistance element.

The semiconductor device proposed by the present invention, in addition to increasing the withstand voltage of the resistance element, can also provide a path for eliminating electrostatic charges, so that the polysilicon resistor can not only meet the requirements of high-voltage applications, but also meet the requirements of electrostatic discharge protection at one end of the polysilicon resistor. , provide the required protection features.

In view of this, the present invention proposes a semiconductor device, which includes a semiconductor substrate, a first well region, a second well region, a field oxide layer and a polysilicon layer. The above-mentioned semiconductor substrate has a first conductivity type. The first well region is formed in the semiconductor substrate and has a second conductivity type. The second well region is formed in the first well region and has the first conductivity type. The field oxide layer is formed on the second well region. The polysilicon layer is formed on the field oxide layer and forms a resistance element.

According to an embodiment of the present invention, the above semiconductor device further includes a first top doped layer and a second top doped layer. The first top doped layer is formed in the first well region and has the first conductivity type. The second top doped layer is formed in the first well region and has the first conductivity type, wherein the first top doped layer and the second top doped layer are located on both sides of the second well region, and They are respectively separated from the above-mentioned second well area.

According to an embodiment of the present invention, the above-mentioned semiconductor device further includes a third well region and a doped region. The third well region is formed in the semiconductor substrate and has the first conductivity type. The above-mentioned doped region is formed in the above-mentioned third well region and has the above-mentioned first conductivity type, wherein the above-mentioned doped region is coupled to a ground terminal.

The present invention further provides a semiconductor device, including a semiconductor substrate, a first well region, a second well region, a first doped region, a field oxide layer and a polysilicon layer. The above-mentioned semiconductor substrate has a first conductivity type. The first well region is formed in the semiconductor substrate and has a second conductivity type. The second well region is formed in the first well region and has the second conductivity type. The first doped region is formed in the second well region and has the second conductivity type. The field oxide layer is formed on the first well region and surrounds the first doped region. The polysilicon layer is formed on the field oxide layer and forms a resistance element.

According to an embodiment of the present invention, the above semiconductor device further includes a first top doped layer and a second top doped layer. The first top doped layer is formed in the first well region and has the first conductivity type. The second top doped layer is formed in the first well region and has the first conductivity type, wherein the first top doped layer and the second top doped layer are located on both sides of the second well region, wherein The resistance element is further formed on the first top doped layer and the second top doped layer.

According to an embodiment of the present invention, the above-mentioned semiconductor device further includes a third well region and a second doped region. The third well region is formed in the semiconductor substrate and has the first conductivity type. The second doped region is formed in the third well region and has the first conductivity type.

According to an embodiment of the present invention, the above-mentioned resistance element has a first terminal coupled to a high voltage level and a second terminal coupled to a low voltage level, wherein the first doped region is Coupled to the high voltage level, the second doped region is coupled to a ground terminal.

According to another embodiment of the present invention, the above semiconductor device further includes a third doped region. The third doped region is formed in the third well region, adjacent to the second doped region and has the second conductivity type, wherein the third doped region is coupled to the ground terminal, wherein the first The doping region, the second doping region and the third doping region form a parasitic bipolar transistor.

According to another embodiment of the present invention, the above-mentioned semiconductor device further includes a fourth doped region and a fifth doped region. The fourth doped region is formed in the second well region, adjacent to the first doped region and has the first conductivity type. The fifth doped region is formed in the semiconductor substrate and has the second conductivity type.

According to an embodiment of the present invention, the fourth doped region is coupled to the high voltage level, the fifth doped region is coupled to the ground terminal, wherein the fifth doped region is connected to the third well The regions are separated from each other, wherein the first doped region, the fourth doped region, the second doped region and the fifth doped region form a parasitic silicon controlled rectifier.

The semiconductor substrate, the semiconductor device and the manufacturing method of the semiconductor device according to some embodiments of the present disclosure will be described in detail below. It should be understood that the following descriptions provide many different embodiments or examples for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only for simple and clear description of some embodiments of the present disclosure. Of course, these are only examples rather than limitations of the present disclosure. Furthermore, repeated reference numerals or designations may be used in different embodiments. These repetitions are only for simply and clearly describing some embodiments of the present disclosure, and do not mean that there is any relationship between the different embodiments and/or structures discussed. Furthermore, when it is mentioned that a first material layer is located on or over a second material layer, it includes the situation that the first material layer is in direct contact with the second material layer. Alternatively, one or more layers of other material may be interspersed, in which case there may be no direct contact between the first material layer and the second material layer.

In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element to another element in the drawings. It will be appreciated that if the illustrated device is turned over so that it is upside down, elements described as being on the "lower" side will then become elements on the "higher" side.

Here, the terms "about", "approximately" and "approximately" usually mean within 20%, preferably within 10%, and more preferably within 5%, or within 3% of a given value or range. Within %, or within 2%, or within 1%, or within 0.5%. The quantity given here is an approximate quantity, that is, the meanings of "about", "about" and "approximately" can still be implied if "about", "approximately" and "approximately" are not specified.

It can be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions , layer, and/or section should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and/or sections. Thus, a first element, component, region, layer, and/or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of some embodiments of the present disclosure. and/or sections.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It can be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having meanings consistent with the related art and the background or context of the present disclosure, rather than in an idealized or overly formal manner Interpretation, unless otherwise defined in the embodiments of the present disclosure.

Some embodiments of the present disclosure can be understood together with the drawings, and the drawings of the embodiments of the present disclosure are also regarded as a part of the description of the embodiments of the present disclosure. It should be understood that the drawings of the embodiments of the present disclosure are not drawn in proportion to actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings in order to clearly show the features of the embodiments of the present disclosure. In addition, the structures and devices in the drawings are shown schematically in order to clearly show the features of the embodiments of the present disclosure.

In some embodiments of the present disclosure, relative terms such as "lower", "upper", "horizontal", "vertical", "under", "above", "top", "bottom", etc. shall be used It is to be understood as the orientation shown in this paragraph and related drawings. This relative term is used for convenience of description only, and it does not mean that the described device must be manufactured or operated in a specific orientation. The terms about bonding and connection, such as "connection", "interconnection", etc., unless otherwise specified, can refer to two structures that are in direct contact, or can also refer to two structures that are not in direct contact, and other structures are provided here. between the two structures. And the terms about joining and connecting may also include the situation that both structures are movable, or both structures are fixed.

Embodiments of the present invention disclose embodiments of semiconductor devices, and the above embodiments may be included in integrated circuits (ICs) such as microprocessors, memory devices, and/or other devices. The integrated circuits described above may also contain various passive and active microelectronic components such as thin-film resistors, other types of capacitors such as metal-insulator-metal capacitors (MIMCAP), inductors , Diodes, Metal-Oxide-Semiconductor field-effect transistors (Metal-Oxide-Semiconductor field-effect transistors, MOSFETs), complementary MOS transistors, bipolar junction transistors (bipolar junction transistors, BJTs), lateral diffusion type MOS transistors, high power MOS transistors, or other types of transistors. Those skilled in the art of the present invention can understand that the semiconductor device can also be used in an integrated circuit including other types of semiconductor elements.

FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1 , the semiconductor device 100 includes a semiconductor substrate SUB, a first well region W1 , a second well region W2 , a field oxide layer FOX, and a polysilicon layer PLY. The semiconductor substrate SUB has a first conductivity type. According to an embodiment of the present invention, the semiconductor substrate SUB is a silicon substrate. According to other embodiments of the present invention, the semiconductor substrate SUB may also be a lightly doped semiconductor substrate with the first conductivity type.

The first well region W1 is formed in the semiconductor substrate SUB and has the second conductivity type. According to an embodiment of the present invention, the first conductivity type is P type, and the second conductivity type is N type. According to an embodiment of the present invention, the first well region W1 can be formed by an ion implantation step. For example, phosphorous ions or arsenic ions can be implanted in the predetermined area of the first well region W1 to form the first well region W1.

The second well region W2 is formed in the first well region W1 and has the first conductivity type. According to an embodiment of the present invention, the second well region W2 can be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the second well region W2 is planned to be formed to form the second well region W2. In this embodiment, the doping concentration of the second well region W2 is higher than that of the semiconductor substrate SUB.

The field oxide layer FOX is formed on the first well region W1 and the second well region W2 , and the polysilicon layer PLY is formed on the field oxide layer FOX and the second well region W2 to form the resistance element R. According to an embodiment of the present invention, the resistance element R is formed on the field oxide layer FOX and the second well region W2. According to another embodiment of the present invention, the resistance element R can be formed on the field oxide layer FOX, the first well region W1 and the second well region W2, wherein the width of the two sides of the resistance element R does not exceed the first well region W1 the width. As shown in FIG. 1, the distribution width G of the resistance element R is smaller than or equal to the well width H of the first well W1.

Figure 2 shows a top view of the polysilicon layer described in Figure 1 according to the present invention. As shown in FIG. 2, the resistance element 200 is a ring structure, including a pad PAD, a first node N1, and a second node N2, wherein the first node N1 in FIG. 2 corresponds to the first node N1 in FIG. 1 , the second node N2 in Figure 2 corresponds to the second node N2 in Figure 1 . As shown in FIG. 1 , the first node N1 and the pad PAD are coupled to the high voltage level VH, and the second node N2 is coupled to the low voltage level VL. According to some embodiments of the present invention, the low voltage level VL is a lower voltage level relative to the high voltage level VH, so the low voltage level VL can be the ground terminal GND or between the high voltage level VH and The voltage between the ground terminal GND.

Referring back to FIG. 1 , the semiconductor device 100 further includes a third well region W3 and a doped region D. Referring to FIG. The third well region W3 is formed in the semiconductor substrate SUB and has the first conductivity type. According to an embodiment of the present invention, the third well region W3 can be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the third well region W3 is planned to be formed to form the third well region W3. In this embodiment, the doping concentration of the third well region W3 is higher than that of the semiconductor substrate SUB.

The doped region D is formed in the third well region W3 and has the first conductivity type. According to an embodiment of the present invention, the doping concentration of the doped region D is higher than that of the third well region W3. As shown in FIG. 1 , the doped region D is coupled to the ground terminal GND.

As shown in FIG. 1 , the semiconductor device 100 further includes a first top doped layer TOP1 and a second top doped layer TOP2 . The first top doped layer TOP1 is formed in the first well region W1 and has the first conductivity type, and the second top doped layer TOP2 is formed in the first well region W1 and has the first conductivity type, wherein the first top doped layer TOP2 is formed in the first well region W1 and has the first conductivity type. The doped layer TOP1 and the second top doped layer TOP2 are located at two sides of the second well region W2 and are separated from the second well region W2 respectively. According to an embodiment of the present invention, the doping concentrations of the first top doped layer TOP1 and the second top doped layer TOP2 are lower than the doping concentration of the second well region W2.

According to an embodiment of the present invention, since the second well region W2 and the first well region W1 form the first parasitic diode DP1, the first well region W1 and the semiconductor substrate SUB form the second parasitic diode DP2, so that the high voltage The cross voltage from the level VH to the ground terminal GND is shared by the field oxide layer FOX, the first parasitic diode DP1 and the second parasitic diode DP2, thereby improving the withstand voltage of the resistance element R of the semiconductor device 100 . According to an embodiment of the present invention, the first top doped layer TOP1 and the second top doped layer TOP2 are used to increase the lateral electric field bearing capacity of the semiconductor device 100 .

FIG. 3 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention. As shown in FIG. 3 , the semiconductor device 300 includes a semiconductor substrate SUB, a first well region W1 , a second well region W2 , a first doped region D1 , a field oxide layer FOX, and a polysilicon layer PLY. The semiconductor substrate SUB has a first conductivity type. According to an embodiment of the present invention, the semiconductor substrate SUB is a silicon substrate. According to other embodiments of the present invention, the semiconductor substrate SUB may also be a lightly doped semiconductor substrate with the first conductivity type.

The first well region W1 is formed in the semiconductor substrate SUB and has the second conductivity type. According to an embodiment of the present invention, the first conductivity type is P type, and the second conductivity type is N type. According to an embodiment of the present invention, the first well region W1 can be formed by an ion implantation step. For example, phosphorous ions or arsenic ions can be implanted in the predetermined area of the first well region W1 to form the first well region W1.

The second well region W2 is formed in the first well region W1 and has the second conductivity type. According to an embodiment of the present invention, the second well region W2 can be formed by an ion implantation step. For example, phosphorous ions or arsenic ions can be implanted in the predetermined area of the first well region W1 to form the second well region W2. In this embodiment, the doping concentration of the second well region W2 is higher than that of the first well region W1.

The first doped region D1 is formed in the second well region W2 and has the second conductivity type. According to an embodiment of the present invention, the first doped region D1 can be formed by an ion implantation step. For example, phosphorous ions or arsenic ions can be implanted in the predetermined area of the first doped region D1 to form the first doped region D1. In this embodiment, the doping concentration of the first doped region D1 is higher than that of the second well region W2.

The field oxide layer FOX is formed above the first well region W1 and the above second well region W2, and surrounds the first doped region D1, and the polysilicon layer PLY is formed on the field oxide layer FOX to form a resistance element R.

FIG. 4 shows a top view of the polysilicon layer described in FIG. 3 according to the present invention. As shown in FIG. 4, the resistance element 400 is a ring structure, including a first node N1 and a second node N2, wherein the first node N1 in FIG. 4 corresponds to the first node N1 in FIG. 3, and the first node N1 in FIG. 4 The second node N2 corresponds to the second node N2 in FIG. 3 . As shown in FIG. 4 , the first doped region D1 is located at the center of the resistor element 400 . Comparing the resistor element 400 in FIG. 4 with the resistor element 200 in FIG. 2 , the first doped region D1 in FIG. 4 is located at the pad PAD in FIG. 2 . As shown in FIG. 3 , the first node N1 of the resistance element R and the first doped region D1 are coupled to the high voltage level VH, and the second node N2 of the resistance element R is coupled to the low voltage level VL.

Referring back to FIG. 3 , the semiconductor device 300 further includes a third well region W3 and a second doped region D2 . The third well region W3 is formed in the semiconductor substrate SUB and has the first conductivity type. According to an embodiment of the present invention, the third well region W3 can be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the third well region W3 is planned to be formed to form the third well region W3. In this embodiment, the doping concentration of the third well region W3 is higher than that of the semiconductor substrate SUB.

The second doped region D2 is formed in the third well region W3 and has the first conductivity type. According to an embodiment of the present invention, the doping concentration of the second doped region D2 is higher than that of the third well region W3. As shown in FIG. 3 , the second doped region D2 is coupled to the ground terminal GND.

As shown in FIG. 3 , the semiconductor device 300 further includes a first top doped layer TOP1 and a second top doped layer TOP2 . The first top doped layer TOP1 is formed in the first well region W1 and has the first conductivity type, and the second top doped layer TOP2 is formed in the first well region W1 and has the first conductivity type, wherein the first top doped layer TOP2 is formed in the first well region W1 and has the first conductivity type. The doped layer TOP1 and the second top doped layer TOP2 are located at two sides of the second well region W2 and are separated from the second well region W2 respectively. According to an embodiment of the present invention, the doping concentrations of the first top doped layer TOP1 and the second top doped layer TOP2 are lower than the doping concentration of the third well region W3 and higher than the doping concentration of the semiconductor substrate SUB .

As shown in Figure 3, the width of the resistance element R distributed on the field oxide layer FOX is the first width X1, the width of the first top doped region TOP1 or the second doped region TOP2 is the second width X2, and the width of the second doped region TOP2 is the second width X2. The second width X2 is not less than the first width X1.

According to an embodiment of the present invention, the cross voltage from the high voltage level to the ground terminal GND is composed of the field oxide layer FOX, the first top doped region TOP1 (or the second top doped region TOP2), the first well region W1 and the semiconductor substrate SUB share the burden, thereby improving the withstand voltage of the semiconductor device 500 . According to an embodiment of the present invention, since the third parasitic diode DP3 is formed between the first well region W1 and the semiconductor substrate SUB, the third parasitic diode DP3 provides an electrostatic coupling to the first node N1 of the high voltage level VH The removal path of charge.

In other words, when the first node N1 of the resistance element R is subjected to electrostatic discharge, since the first node N1 is coupled to the first doped region D1, electrostatic charges will be formed through the first well region W1 and the semiconductor substrate SUB The third parasitic diode DP3 discharges the electrostatic charges to the ground terminal GND through the second doped region D2. According to an embodiment of the present invention, the first top doped layer TOP1 and the second top doped layer TOP2 are not only used to increase the vertical electric field bearing capacity of the semiconductor device 300, but also used to increase the lateral electric field bearing capacity of the semiconductor device 300 .

FIG. 5 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention. Comparing the semiconductor device 500 in FIG. 5 with the semiconductor device 300 in FIG. 3 , the semiconductor device 500 further includes a third doped region D3.

The third doped region D3 is formed in the third well region W3, is located between the first doped region D1 and the second doped region D2 and is adjacent to the second doped region D2, and has the second conductive type. According to an embodiment of the present invention, the third doped region D3 can be formed by an ion implantation step. For example, phosphorous ions or arsenic ions can be implanted in the predetermined area of the third doped region D3 to form the third doped region D3. In this embodiment, the doping concentration of the third doped region D3 is higher than that of the second well region W2. As shown in FIG. 5 , the third doped region D3 is further coupled to the ground terminal GND.

According to an embodiment of the present invention, the cross voltage from the high voltage level to the ground terminal GND is composed of the field oxide layer FOX, the first top doped region TOP1 (or the second top doped region TOP2), the first well region W1 and the semiconductor substrate SUB share the burden, thereby improving the withstand voltage of the semiconductor device 500 . According to an embodiment of the present invention, since the first doped region D1, the second doped region D2 and the third doped region D3 form a parasitic bipolar transistor NPN and the first node N1 is coupled to the first doped region D1, when the first node N1 of the resistance element R is subjected to electrostatic discharge, the parasitic bipolar transistor NPN is turned on immediately to quickly discharge the electrostatic charge to the ground terminal GND. According to an embodiment of the present invention, the first top doped layer TOP1 and the second top doped layer TOP2 are not only used to increase the vertical electric field bearing capacity of the semiconductor device 500, but also used to increase the lateral electric field bearing capacity of the semiconductor device 500 .

FIG. 6 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention. Comparing the semiconductor device 600 in FIG. 6 with the semiconductor device 300 in FIG. 3 , the semiconductor device 600 further includes a fourth doped region D4 and a fifth doped region D5 .

The fourth doped region D4 is formed in the second well region W2, adjacent to the first doped region D1, and has the first conductivity type. According to an embodiment of the present invention, the fourth doped region D4 can be formed by an ion implantation step. For example, boron ions or indium ions may be implanted in the region where the fourth doped region D4 is to be formed to form the fourth doped region D4.

The fifth doped region D5 is formed in the semiconductor substrate SUB and has the second conductivity type. According to an embodiment of the present invention, the fifth doped region D5 can be formed by an ion implantation step. For example, boron ions or indium ions may be implanted in the region where the fifth doped region D5 is to be formed to form the fifth doped region D5. As shown in FIG. 6, the fifth doped region D5 is coupled to the ground terminal GND, and is separated from the third well region W3.

According to an embodiment of the present invention, since the first doped region D1, the fourth doped region D4, the second doped region D2 and the fifth doped region D5 form a parasitic silicon controlled rectifier (SCR) And the first node N1 is coupled together with the first doped region D1 and the fourth doped region, when the first node N1 of the resistance element R is subjected to electrostatic discharge, the parasitic silicon controlled rectifier is turned on immediately and the first node The electrostatic charge received by N1 is discharged to the ground terminal GND.

The semiconductor device proposed by the present invention, in addition to increasing the withstand voltage of the resistance element, can also provide a path for eliminating electrostatic charges, so that the polysilicon resistor can not only meet the needs of high-voltage applications, but also provide electrostatic discharge protection at one end of the polysilicon resistor, providing required protection features.

Although the embodiments of the present disclosure and their advantages have been disclosed above, it should be understood that those skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the protection scope of the present disclosure is not limited to the process, machine, manufacture, material composition, device, method and steps in the specific embodiments described in the specification, and anyone with ordinary knowledge in the technical field can implement some In the disclosure content of the examples, it is understood that the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps can be used as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described here. Some examples of this disclosure use . Therefore, the protection scope of the present disclosure includes the above-mentioned process, machine, manufacture, composition of matter, device, method and steps. In addition, each patent application scope constitutes an individual embodiment, and the protection scope of the present disclosure also includes combinations of various patent application scopes and embodiments.

100, 300, 500, 600: semiconductor devices 200,400: resistance element SUB: semiconductor substrate W1: the first well area W2: the second well area W3: The third well area TOP1: the first top doped layer TOP2: the second top doped layer FOX: field oxide layer PLY: polysilicon layer R: resistance element G: distribution width H: Well area width PAD: welding pad N1: the first node N2: second node VH: high voltage level VL: low voltage level GND: ground terminal D: doped area DP1: The first parasitic diode DP2: Second parasitic diode DP3: The third parasitic diode D1: the first doped region D2: the second doped region D3: the third doped region D4: the fourth doped region D5: fifth doped region X1: first width X2: second width NPN: Parasitic bipolar transistor

FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention; Figure 2 shows a top view of the polysilicon layer described in Figure 1 according to the present invention; FIG. 3 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention; Figure 4 shows a top view of the polysilicon layer described in Figure 3 according to the present invention; FIG. 5 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention; and FIG. 6 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

100: Semiconductor device

SUB: semiconductor substrate

W1: the first well area

W2: the second well area

W3: The third well area

TOP1: the first top doped layer

TOP2: the second top doped layer

FOX: field oxide layer

PLY: polysilicon layer

R: resistance element

PAD: welding pad

N1: the first node

N2: second node

VH: high voltage level

VL: low voltage level

GND: ground terminal

D: doped area

DP1: The first parasitic diode

DP2: Second parasitic diode

G: distribution width

H: Well area width

Claims (10)

A semiconductor device comprising: A semiconductor substrate having a first conductivity type; a first well region formed in the semiconductor substrate and having a second conductivity type; a second well formed in the first well and having the first conductivity type; a field oxide layer formed on the above-mentioned second well region; and A polysilicon layer is formed on the field oxide layer and forms a resistance element. The semiconductor device of claim 1 further includes: a first top doped layer formed in the first well region and having the first conductivity type; and A second top-doped layer formed in the first well region and having the first conductivity type, wherein the first top-doped layer and the second top-doped layer are located on both sides of the second well region, And they are respectively separated from the above-mentioned second well area. The semiconductor device of claim 1 further includes: a third well region formed in the above-mentioned semiconductor substrate and having the above-mentioned first conductivity type; and A doped region is formed in the third well region and has the first conductivity type, wherein the doped region is coupled to a ground terminal. A semiconductor device comprising: A semiconductor substrate having a first conductivity type; a first well region formed in the semiconductor substrate and having a second conductivity type; a second well formed in the first well and having the second conductivity type; a first doped region formed in the second well region and having the second conductivity type; a field oxide layer formed on the first well region and surrounding the first doped region; and A polysilicon layer is formed on the field oxide layer and forms a resistance element. Such as the semiconductor device of claim 4, further comprising: a first top doped layer formed in the first well region and having the first conductivity type; and A second top-doped layer formed in the first well region and having the first conductivity type, wherein the first top-doped layer and the second top-doped layer are located on both sides of the second well region, Wherein the resistance element is further formed on the first top doped layer and the second top doped layer. Such as the semiconductor device of claim 4, further comprising: a third well region formed in the above-mentioned semiconductor substrate and having the above-mentioned first conductivity type; and A second doped region is formed in the third well region and has the first conductivity type. The semiconductor device according to claim 6, wherein the resistance element has a first terminal coupled to a high voltage level and a second terminal coupled to a low voltage level, wherein the first doped region is coupled to the high voltage level, and the second doped region is coupled to a ground terminal. Such as the semiconductor device of claim 7, further comprising: A third doped region, formed in the third well region, adjacent to the second doped region and having the second conductivity type, wherein the third doped region is coupled to the ground terminal, wherein the first A doping region, the second doping region and the third doping region form a parasitic bipolar transistor. Such as the semiconductor device of claim 7, further comprising: A fourth doped region, formed in the second well region, adjacent to the first doped region and having the first conductivity type; and A fifth doped region is formed in the above-mentioned semiconductor substrate and has the above-mentioned second conductivity type. The semiconductor device according to claim 9, wherein the fourth doped region is coupled to the high voltage level, the fifth doped region is coupled to the ground terminal, wherein the fifth doped region is connected to the third The well regions are separated from each other, wherein the first doped region, the fourth doped region, the second doped region and the fifth doped region form a parasitic silicon controlled rectifier.

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