JP6594725B2 - Semiconductor non-volatile memory device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor nonvolatile memory device capable of changing a threshold voltage by applying an electric signal from the outside, and a manufacturing method thereof.

  Electronic circuits used in electronic devices are driven by a power source such as a battery. If the voltage of the power source fluctuates, the electronic circuit may malfunction or cause various abnormal phenomena. In general, a power management IC that monitors power supply fluctuations is installed between an electronic circuit and a power supply to achieve stable operation. In particular, in semiconductor integrated circuits such as microcomputers and CPUs, whose voltage has been decreasing in recent years, there has been a strict requirement for power management ICs to improve the accuracy of the constant voltage output and the voltage value to be monitored. ing.

An example of a power management IC that outputs a constant voltage from a power supply to an electric circuit is a step-down series regulator shown in FIG.
In this semiconductor integrated circuit, a power supply voltage applied between a ground terminal 105 and a power supply terminal 106 is divided by a voltage dividing circuit 103 including a PMOS output element 104 and a resistance element 102. The voltage divided by the resistance element 102 is input to one input terminal of the error amplifier 101, and compared with a fixed reference voltage value generated from the reference voltage circuit 100, the error amplifier 101 determines the PMOS output element 104 according to the magnitude. , And the source / drain resistance of the PMOS output element 104 is changed. As a result, the output terminal 107 has a function of outputting a constant output voltage having no power supply voltage dependency according to the reference voltage value of the reference voltage circuit 100 and the resistance voltage dividing ratio of the voltage dividing circuit 103. This output voltage is calculated by the following equation (1).

Output voltage = reference voltage value x voltage divider circuit resistance division ratio (1)
In adjusting the output voltage, the voltage dividing ratio of the voltage dividing circuit 103 is changed by changing the resistance value of the resistance element 102 by a method described later, and a desired output voltage value is set based on the equation (1). Therefore, it is necessary to process and modify the voltage dividing circuit of the semiconductor integrated circuit for each target output voltage.

A voltage detector having a function of outputting a signal when the power supply voltage becomes a constant voltage as shown in FIG. 4 is one of the power management ICs.
In this semiconductor integrated circuit, the power supply voltage input from the power supply terminal 106 is converted into a voltage divided by the voltage dividing circuit 103 formed of the resistance element 102, and the reference voltage value of the reference voltage circuit 100 is compared with the comparator 108, The voltage signal is output from the output terminal 107 depending on the size. By such a mechanism, a power supply voltage is monitored, and a voltage detector having a function of outputting a signal in order to perform an appropriate process when a certain voltage is exceeded or below is realized.

  In the example of FIG. 4 as well, the voltage dividing ratio of the voltage dividing circuit 103 is changed by changing the resistance element 102, and a desired voltage detection value is set based on the equation (1). Therefore, it is necessary to process and modify the voltage dividing circuit of the semiconductor integrated circuit for each target output voltage.

  As a resistance element used in a voltage dividing circuit of a semiconductor integrated circuit, a diffusion resistor in which an impurity having a conductivity type opposite to that of a semiconductor substrate is implanted into a single crystal silicon semiconductor substrate, a resistor made of polycrystalline silicon in which an impurity is implanted, or the like is used. . In the design of the voltage dividing circuit, when a plurality of resistors are used, the length, width, and resistivity are all set to be the same. By doing so, each resistance element is equally affected by variations in the shape of the etching process that determines the shape and variations in impurity implantation. Even if the absolute values of the resistance elements vary, the resistance ratio between the resistance elements This is because it can be kept constant.

  FIG. 5 shows a case where a resistance element having a constant resistance value based on the constant shape and the specific resistivity is used in the voltage dividing circuit. Various resistance values are realized by connecting the unit resistance elements 200 in series or in parallel as in the resistance groups 201 to 204 in FIG. Since the unit resistance element 200 is a resistance element having the same shape and the same resistivity as described above, the resistance ratio of the resistance group composed of unit resistance elements having a high resistance ratio can be maintained with high accuracy.

  Further, fuses 301 to 304 made of, for example, polycrystalline silicon are installed in parallel with the resistance groups 201 to 204 so that they can be cut by laser irradiation from the outside. The resistance value between the 109 terminal A and the 110 terminal B can be changed as necessary according to whether the fuse is cut or not cut by the laser irradiation. The voltage dividing ratio with the fixed resistor formed between the 110 terminal B and the 111 terminal C is output from the 110 terminal B.

  As described above, in a voltage dividing circuit having a highly accurate resistance ratio, a desired voltage dividing ratio can be obtained with high accuracy by laser-cutting a polycrystalline silicon fuse, and various targets can be used while using the same semiconductor integrated circuit. It is possible to produce products with an output voltage of.

A general output voltage adjustment method is as shown in FIG.
First, the output voltage of the product finished at the semiconductor processing factory is measured as it is (FIG. 2 (1)). Next, based on a calculation formula or database prepared in advance according to the output voltage, the polycrystalline silicon fuse installed in the voltage dividing circuit is processed with a laser to trim the output voltage (FIG. 2 (2)). Finally, the output voltage of the processed product is measured again, and it is confirmed whether it meets the desired specification standard (FIG. 2 (3)). Here, products that do not meet the specifications will be shipped. In addition, there is an on-line trimming method in which the resistor is gradually processed while monitoring the output voltage, and the processing is stopped when the desired output voltage is reached. The method of FIG. 2 is called an off-line trimming method in contrast to the on-line trimming method.

Next, a reference voltage circuit similarly used in FIGS. 3 and 4 will be described with reference to FIGS.
The reference voltage circuit is the most basic circuit conventionally, and includes a depletion type NMOS transistor 402 and an enhancement type NMOS transistor 401. As shown in FIG. 6 (1), each transistor is formed on a P-type well region 5 in the semiconductor substrate 1 and includes a gate electrode 6, a gate insulating film 9, and an N-type source / drain region 12. The difference is that in the impurity region for determining the threshold voltage formed under the gate insulating film 9, the N-type channel impurity region 10 is present in the depletion type NMOS transistor 402, and the P-type channel impurity is present in the enhancement type NMOS transistor 401. That is, the region 11 is formed. Each has a drain terminal 2, a source terminal 3 for controlling the transistor operation, and a body terminal 4 for fixing the potential of the P-type well region.

Such a depletion type NMOS transistor 402 and an enhancement type NMOS transistor 401 are connected in series between a power supply terminal 403 and a ground terminal 404 as shown in FIG. 6B, and a constant current is supplied from the depletion type NMOS transistor 402 as a current source. Is input to the drain terminal 2 of the enhanced NMOS transistor 401 serving as a load element, and the voltage generated at the drain terminal of the enhanced NMOS transistor 401 is output to the reference voltage output terminal 405 as a constant voltage. (For example, see Patent Document 1)
The constant voltage output from the reference voltage circuit at this time is expressed by the following equation (2) when the threshold voltage and transconductance of the depletion type NMOS transistor are Vtd and Ktd, and the threshold voltage and transconductance of the enhancement type NMOS transistor are Vte and Kte. become that way.

Reference voltage circuit constant voltage = √ (Ktd / Kte) × | Vtd | + Vte (2)
That is, the variation that occurs in the output voltage of Equation (1) is due to the fact that each parameter that determines the constant voltage output from the reference voltage circuit varies. This variation is absorbed by adjusting the resistance voltage dividing ratio of the voltage dividing circuit.

JP 2008-198775 A

  Semiconductor non-volatile memory device capable of adjusting threshold voltage with high accuracy and enabling adjustment of output voltage without relying on trimming method by laser processing in order to reduce variation in circuit characteristics of semiconductor integrated circuit device and its manufacture Provide a method.

In order to solve the above-mentioned problems, the present invention has been made as follows.
That is, a semiconductor substrate, a first conductivity type well region formed in the semiconductor substrate, a high concentration source region and a first high concentration drain having a second conductivity type first high concentration impurity formed apart from each other. A first gate insulating film formed on the semiconductor substrate adjacent to the first high concentration source region between the high concentration source region and the first high concentration drain region, and the high concentration source region and A second gate insulating film formed on the semiconductor substrate between the first high-concentration drain regions and adjacent to the first high-concentration drain region; and a second gate insulation separated from the high-concentration source region A second high-concentration drain region of a second conductivity type formed in a region including the region under the film and overlapping the first high-concentration drain region, and spaced apart from the high-concentration source region, Lower and second gate insulating films The first conductivity region is formed under the second conductivity type first low concentration drain region and the first gate insulating film formed in a region including the lower region and overlapping the first high concentration drain region and the second high concentration drain region. A second conductivity type channel impurity region formed between the source region and the first low-concentration drain region, and a high concentration impurity formed on the first gate insulating film and the second gate insulating film. A floating gate electrode made of crystalline silicon; a third gate insulating film formed on the floating gate electrode; a control gate electrode formed on the third gate insulating film and made of polycrystalline silicon containing high-concentration impurities; The one conductivity type well region includes a high concentration source region, a first high concentration drain region, a second high concentration drain region, a first low concentration drain region, and a channel impurity region. And a semiconductor nonvolatile memory device which is formed to a position deeper than these areas there.

In order to solve the above-mentioned problems, the present invention is as follows.
That is, a P-type well region forming step for forming a P-type well region made of P-type impurities on a semiconductor substrate;
An element isolation insulating film forming step of forming a LOCOS oxide film around the P-type well region;
An N-type high-concentration region forming step of forming an N-type high-concentration region made of N-type impurities in the drain formation scheduled region;
An N-type low-concentration region forming step of forming a first N-type low-concentration impurity region, which has a lower N-type impurity concentration than the N-type high concentration region and is deeply diffused;
A channel region forming step of forming an N-type impurity region in a channel formation scheduled region in the P-type well region;
A second gate insulating film is formed in the drain formation planned region so as to overlap the N-type high concentration region, and a first gate insulating film thinner than the second gate insulating film is formed in the channel formation planned region. Forming a gate insulating film to be formed;
A polycrystalline silicon layer containing impurities is formed on the first gate insulating film and the second gate insulating film, a third gate insulating film is formed on the polycrystalline silicon, and the third gate insulating film is formed. A gate electrode formation step of forming a polycrystalline silicon layer containing impurities on the gate insulating film;
A source / drain formation step of forming an N-type impurity region in the source formation scheduled region and the drain formation scheduled region;
The manufacturing method of the semiconductor non-volatile memory element which has this.

  According to the present invention, it is possible to provide a semiconductor nonvolatile memory element whose threshold voltage can be adjusted by an external electrical signal, and to adjust the output voltage of the semiconductor integrated circuit device with high accuracy and easily.

It is a process flowchart which shows the output voltage adjustment method of the semiconductor correction circuit apparatus of this invention. It is a process flowchart which shows the output voltage adjustment method of the conventional semiconductor correction circuit apparatus. 2 is a configuration outline of a step-down type series regulator using a conventional semiconductor integrated circuit device. It is a structure outline | summary of the voltage detector by the conventional semiconductor integrated circuit device. It is an example of the voltage dividing circuit which combined the conventional resistive element. (1) It is a schematic cross section which comprises the conventional reference voltage circuit. (2) An example of a conventional reference voltage circuit. (1) It is a schematic cross section which comprises the reference voltage circuit of this invention. (2) An example of the reference voltage circuit of the present invention. 1 is a schematic configuration diagram of a step-down type series regulator using a semiconductor integrated circuit device according to the present invention. 1 is a schematic configuration diagram of a voltage detector using a semiconductor integrated circuit device according to the present invention. 1 is a schematic cross-sectional view of a first embodiment of a semiconductor nonvolatile memory element of the present invention. It is a schematic cross section of the 2nd Example of the semiconductor non-volatile memory element of this invention. It is a schematic cross section of the 3rd Example of the semiconductor non-volatile memory element of this invention. It is a schematic cross section of the 4th Example of the semiconductor non-volatile memory element of this invention. It is a schematic cross section of the 5th Example of the semiconductor non-volatile memory element of this invention. It is a schematic cross section of the 6th Example of the semiconductor non-volatile memory element of this invention. It is a schematic cross section of the 7th Example of the semiconductor non-volatile memory element of this invention. It is a schematic cross section of the 8th Example of the semiconductor non-volatile memory element of this invention. It is an equivalent circuit diagram of the gate insulating film capacitance viewed from the drain terminal of the present invention. It is a figure explaining the electrical characteristic at the time of employ | adopting this invention for a pressure | voltage fall type | mold series regulator. It is a process flow figure showing a manufacturing process of the 1st example of a semiconductor nonvolatile memory element of the present invention. FIG. 21 is a process flow diagram illustrating the manufacturing process of the first embodiment of the semiconductor nonvolatile memory element according to the present invention, following FIG. 20; It is a process flowchart which shows the manufacturing process of the 2nd Example of the semiconductor non-volatile memory element of this invention. It is a process flowchart which shows the manufacturing process of the 3rd Example of the semiconductor non-volatile memory element of this invention. FIG. 24 is a process flow diagram illustrating the manufacturing process of the third embodiment of the semiconductor nonvolatile memory element according to the present invention, following FIG. 23; It is a process flowchart which shows the manufacturing process of the 4th Example of the semiconductor non-volatile memory element of this invention. It is a 2nd process flowchart which shows the manufacturing process of the 1st and 2nd gate insulating film of the semiconductor non-volatile memory element of this invention. It is a 3rd process flowchart which shows the manufacturing process of the 1st and 2nd gate insulating film of the semiconductor non-volatile memory element of this invention. It is a 4th process flowchart which shows the manufacturing process of the 1st and 2nd gate insulating film of the semiconductor non-volatile memory element of this invention. It is a 5th process flowchart which shows the manufacturing process of the 1st and 2nd gate insulating film of the semiconductor non-volatile memory element of this invention.

Embodiments of the present invention will be described below with reference to the drawings.
First, an embodiment in which the present invention is applied to the conventional semiconductor integrated circuit shown in FIGS. 3 and 4 will be described with reference to FIGS. As shown in FIGS. 8 and 9, an adjustment input terminal 112 that can input an applied voltage / current from the outside is added to the reference voltage circuit 100. A specific element in the reference voltage circuit is replaced with a semiconductor nonvolatile memory element, and the semiconductor nonvolatile memory element can change a threshold voltage in accordance with an input voltage / current from the outside to the adjustment input terminal 112.

Therefore, a method for adjusting the output voltage will be described with reference to FIG.
First, the output voltage of the product finished in the semiconductor processing factory is measured as it is (step (1) in FIG. 1).

  Next, a voltage / current is applied to the semiconductor nonvolatile memory element in the reference voltage circuit via the adjustment input terminal to change the threshold voltage of the semiconductor nonvolatile memory element (step (2) in FIG. 1). In the semiconductor integrated circuit configured as shown in FIGS. 8 and 9, if the reference voltage value output from the reference voltage circuit changes, the output voltage also changes proportionally according to the equation (1). The amount of applied current is proportional to the amount of output voltage.

  Thereafter, the output voltage is measured, and if the output voltage is outside the tolerance specification standard required for the product, the process returns to the step of FIG. 1 (2), and the voltage / current application to the semiconductor nonvolatile memory element is resumed. At this time, the reference voltage value of the reference voltage circuit is set in advance so that the initial output voltage value is outside the specification standard, and the voltage / current is gradually applied to the semiconductor nonvolatile memory element in one direction of + or −. A method of approaching the specification standard is preferable because it is easy to adjust.

  The process of FIG. 1 (2) and the process of FIG. 1 (3) are repeated, and when the output voltage value falls within the specification standard, a series of processing is finished (step of FIG. 1 (4)). The processes in Fig. 1 (2) and (3) can be performed by continuous electrical processing rather than intermittently. Therefore, if program software is created and automatic control is performed, products outside the specification standards are specified. It can be completed in a very short time.

  By adopting such a method, the conventional three-step process such as the process of FIG. 2 (1) to the process of (3) that cannot be redone can be completed by a single electrical process. The output voltage adjustment method is simplified, and the construction period can be greatly shortened. Furthermore, online trimming adjustment while checking the output voltage suppresses the occurrence of defects outside the specifications and can be expected to improve yield.

  In addition, since it is possible to eliminate the influence of high heat (temperature coefficient of resistance, recrystallization) such as on-line trimming by resistance processing using a conventional laser, there is no need to worry about output voltage error and its readjustment, A stable output voltage can be maintained.

In addition, since this adjustment method is an electrical process regardless of the product form (wafer, package), even if the product form changes and the characteristics change due to the effect, it can be electrically readjusted through the terminals. . For example, if the output voltage adjusted in the wafer state changes due to the influence of thermal history or resin stress after mounting the package and falls outside the specification standard, it can be adjusted again in the package state to meet the specification standard. is there. Alternatively, by adjusting the output voltage only in the final form and omitting the investigation in the wafer state, it is possible to further reduce the test frequency and the process.
Further, since the test frequency is eased and the laser trimming process is not required, the effect of suppressing the investment in the apparatus such as a measuring apparatus or a laser apparatus is high.

  Further, the voltage dividing circuit 103 including the resistance element 102 in FIGS. 8 and 9 does not need to be highly accurate, and the output voltage value is adjusted by the method of the present invention in a form including it even if the accuracy is poor. Therefore, unlike the conventional example, it is not necessary to prepare a plurality of uniform resistance elements and to devise the pattern layout, and the fuse element is also unnecessary, so the chip size can be reduced and the layout load can be reduced. There is an advantage that you can expect.

  Next, a reference voltage circuit for realizing the present invention will be described with reference to FIGS. 7 (1) and (2). As shown in FIG. 7B, in the reference voltage circuit, a depletion type NMOS transistor 402 and an enhancement type NMOS transistor 401 are connected in series between an input adjustment terminal 406 and a ground terminal 404, and a depletion type NMOS transistor 402 as a current source. Is output to the reference voltage output terminal 405 as a constant voltage generated at the drain terminal of the enhanced NMOS transistor 401 serving as a load element.

  However, here, as shown in FIG. 7 (1), for the depletion type NMOS transistor 402 used in the present invention, a polycrystalline silicon gate electrode is stacked, the control gate electrode 8 controls the voltage of the upper layer, and the lower layer injects charges. The structure is a floating gate electrode 7 that accumulates.

  When the voltage at the input terminal 406 is increased in this circuit configuration example of FIG. 7 (2), the voltage between the reference voltage output terminal 405 and the ground terminal 404 is always fixed at a constant value. This is borne between the adjustment terminal 406 and the reference voltage output terminal 405. Therefore, the drain-source voltage of the depletion type NMOS transistor 402 increases as the applied voltage of the input terminal 406 increases, and a charge carrier, in this case, a hole via a gate insulating film, and a floating gate having a low potential, are described later. By injecting into the electrode 7, the floating gate electrode can be charged to the positive side. This is equivalent to a decrease in the threshold voltage of the depletion type NMOS transistor when viewed from the control gate electrode side. As a result, the current of the depletion type NMOS transistor increases, and the potential of the reference voltage output terminal 405 also increases accordingly.

  When the reference voltage value of the reference voltage circuit increases, the output voltage of the step-down series regulator of FIG. 8 increases according to equation (1). That is, the output voltage of the step-down series regulator circuit can be arbitrarily changed by controlling the voltage at the reference voltage circuit input terminal. In this example, the adjustment input terminal 112 corresponds to the input adjustment terminal 406 in FIG.

In this case, since the threshold voltage of the semiconductor nonvolatile memory element changes in the negative direction by voltage adjustment via the input adjustment terminal, Vtd, which is originally a negative value, further changes to the negative side according to the equation (2). The value of | Vtd |, which is the value, increases, and the reference voltage output from the reference voltage circuit changes in the increasing direction. Accordingly, the output voltage of the step-down type series regulator circuit is also changed in the direction of increasing, so that the output voltage of the step-down type series regulator of the present invention is lower than the required specification before adjustment by the input adjustment terminal. If designed in this way, output voltage adjustment by this input adjustment terminal can meet a wide range of output voltage requirement specifications.
In addition, adjustment to a predetermined target voltage value can be performed with high accuracy only by electrical control without using a laser trimming process.

  A specific example will be described with reference to FIG. In the graphs shown in FIGS. 19 (1) and 19 (2), the value on the horizontal axis includes the voltage input to the input adjustment terminal 406 of the reference voltage circuit as shown in FIG. 7, and the value on the vertical axis includes the reference voltage circuit. 19 (1) shows the output voltage characteristics before adjustment by the input adjustment terminal, and FIG. 19 (2) shows the output voltage characteristics after adjustment. It is.

  First, before the input adjustment, as shown in FIG. 19A, when the reference voltage circuit input voltage is increased, the input voltage increases until the voltage (a) point at which the reference voltage circuit operates normally. Accordingly, the output voltage rises, and when the output voltage reaches the voltage calculated by the equation (1), the output voltage is stabilized at a constant value up to the input voltage (b) point. Up to this point, the electrical characteristics are completely the same as those of the conventional step-down series regulator.

  Thereafter, when the input voltage reaches a sufficiently high input voltage (b) sufficient to inject carriers into the floating gate electrode of the semiconductor nonvolatile memory element, the injection of carriers into the semiconductor nonvolatile memory element starts, and at the same time, the semiconductor The threshold voltage of the nonvolatile memory element changes. Therefore, the output voltage starts to rise again according to the carrier injection amount. When the application of input voltage beyond that point is stopped when the desired output voltage (c) point is reached, carrier injection into the semiconductor nonvolatile memory element is stopped, and the carrier is stored in the floating gate electrode. The electrical characteristics after the above actions are as shown in FIG.

  That is, since the threshold voltage of the semiconductor nonvolatile memory element changes according to the amount of carriers injected into the semiconductor nonvolatile memory element, | Vtd | increases according to the equation (2), and the reference voltage circuit constant voltage and (1 The stabilized output voltage based on the equation (5) also changes to a high value in (c). As for this output voltage, when a voltage of point (b) or higher is applied to the input adjustment terminal, carrier injection into the semiconductor nonvolatile memory element starts again, and the output voltage starts to rise again.

  The point to be noted here is that, first, in order to enable adjustment of the output voltage as shown in FIG. 19 (1), the semiconductor nonvolatile memory element is not destroyed even when the input voltage reaches (c). The element design is to achieve a sufficiently high drain breakdown voltage.

  Second, after adjusting the output voltage to a desired value, the maximum input voltage when actually using the product is set to a voltage sufficiently lower than the point (b), and the output voltage is reinjected during use of the product. It is to prevent it from changing. In other words, the operating voltage of the semiconductor integrated circuit device using the present invention must be a product specification of (b) or less. For this reason, a semiconductor nonvolatile memory element having characteristics adapted to individual product specifications is prepared in advance.

  Similarly, by realizing the reference voltage circuit in the voltage detection circuit of FIG. 4 with the same circuit, the output voltage of each semiconductor integrated circuit device can be similarly controlled and controlled by the voltage control of the input adjustment terminal attached to the reference voltage circuit. It is possible to set.

  In the reference voltage circuit, the present invention can be applied to any circuit having any configuration as long as the basic operation is based on the combination of the current source element and the load element. Needless to say, it can be applied.

  In addition, the semiconductor nonvolatile memory element described here refers to the injection of charges into the floating gate electrode by hot carrier injection, the injection of carriers by the FN tunnel current through the gate insulating film, and the level existing in the insulating film. It refers to all elements that can realize a threshold voltage shift by carrier injection, such as a method of trapping carriers.

Next, details of the semiconductor nonvolatile memory element used in the present invention will be described.
FIG. 10 is a cross-sectional view of the semiconductor nonvolatile memory element showing the first embodiment of the present invention. The element shown in FIG. 10 is formed in a P-type well region 5 containing boron having an impurity concentration of about 7 × 10 ¹⁵ / cm ³ to 7 × 10 ¹⁶ / cm ³ formed on the semiconductor substrate 1. A depletion type NMOS transistor is constituted by an N-type source / drain electrode, an N-type channel impurity region, a gate insulating film and a gate electrode in a region surrounded by a LOCOS oxide film 13 having a thickness of several thousand to 2 μm used for element isolation. ing.

  Characteristically, the gate electrode has a laminated structure of a floating gate electrode 7 made of polycrystalline silicon and a control gate electrode 8, and the control gate electrode is connected to the source terminal of the depletion type NMOS transistor by a metal wiring or the like (not shown). The floating gate electrode is surrounded by the first gate insulating film 9, the second gate insulating film 14, and the third gate insulating film 15, and has no electrical connection.

  Carriers such as electrons and holes are injected into the floating gate electrode 7 from the drain terminal via the second gate insulating film 14. When positive or negative carriers are injected into the floating gate electrode 7, the threshold voltage of the depletion type NMOS transistor changes in accordance with the injection amount, as with the fixed charge existing between the gate electrode / channel region in a normal MOSFET. To do.

  The injected carriers are maintained under a structural condition that does not escape due to heat or electrical stress during normal operation, so that the threshold voltage of the depletion type NMOS transistor can be adjusted to a desired value and maintained. it can.

  The threshold voltage in a state where carriers are not injected into the floating gate electrode 7 is set to have a negative value according to the impurity amount of the N-type channel impurity region 10, and even if the gate / source voltage is 0V, the drain / When a voltage is applied between the sources, a normally-on state in which a current flows is set.

The N-type source / drain region 12 functions as a source / drain terminal by injecting As and P N-type impurities of 1 × 10 ²⁰ / cm ³ or more into a low resistance. Between the channel impurity region 10, an N-type high concentration impurity region 17 containing As and P N-type impurities of 5 × 10 ¹⁸ / cm ³ or more and 1 × 10 ¹⁷ / cm ³ or more of 1 × 10 ¹⁸ / cm ^{And a} first N-type low concentration region 18 made of ³ or less As and P N-type impurities.

  The first N-type low concentration region 18 plays a role of electrolytic relaxation by the drain side depletion layer extension at the time of drain voltage application and a high breakdown voltage thereby, and the N-type high concentration impurity region 17 serves as a carrier to the floating gate electrode 7. It is used as a lower electrode when implanting.

The first reason for setting the impurity concentration of the N-type high-concentration impurity region 17 to 5 × 10 ¹⁸ / cm ³ is that the N-type high concentration applies a positive voltage when holes are injected as carriers into the floating gate electrode. This is to prevent depletion of the surface of the region and relaxation of the electric field between the floating gate electrode / N-type high concentration region and a decrease in injection efficiency.

  The second reason is that the drain / well spreading from the N-type low concentration region 18 to the drain side when a high voltage is applied to the N-type high concentration impurity region to inject holes as carriers into the floating gate electrode. This is to prevent the expansion of the depletion layer and to prevent a decrease in carrier injection efficiency.

By the way, the N-type high concentration impurity region 17 and the floating gate electrode 7 have an overlapping portion 16, and the second gate insulating film 14 existing in the overlapping portion is a gate insulating material on the N-type channel impurity region 10. The film 9 has a different thickness. Generally, the gate insulating film is set to a predetermined thickness from the viewpoint of long-term reliability in accordance with the operating voltage of the semiconductor integrated circuit including the MOSFET. However, the second gate insulating film 14 in the present semiconductor nonvolatile memory element is determined under conditions suitable for injecting carriers into the floating gate electrode from here, and in order to avoid the escape of charges within the operating voltage range, Use a thickness that is greater than the film thickness determined by long-term reliability at the operating voltage.
Therefore, in this embodiment, the second gate insulating film 14 is thicker than the gate insulating film 9 on the N-type channel impurity region 10.

  Another feature of the semiconductor nonvolatile memory element of the present invention is specialized in analog adjustment of the characteristics of the semiconductor nonvolatile memory element and the semiconductor integrated circuit device including the semiconductor nonvolatile memory element, and replaces some conventional elements. It is for that. Therefore, it is not assumed that a memory array is configured for information storage, and a structure such as a select gate for specifying an address required at the time of memory array configuration is not required.

Next, details of the electrical operation of the present invention will be described.
For example, the potential of the floating gate electrode 7 changes to a negative potential when electrons having a negative charge are injected. In that case, a positive charge is induced in the channel region in response to the negative charge, or electrons in the N-type channel impurity region 10 decrease, and the threshold voltage of the N-channel MOSFET changes to the positive side.

  On the other hand, when positively charged holes are injected into the floating electrode 7, the potential of the floating gate electrode shifts to the positive side and changes to a state in which the electron concentration in the N-type channel impurity region 10 becomes higher. The threshold voltage of this N-channel MOSFET changes to the negative side.

  The configuration of the present invention is a depletion type NMOS transistor in which the threshold voltage takes a negative value when no carrier is injected due to the presence of the N-type channel impurity 10, so that a positive potential is applied to the drain terminal of the floating gate electrode 7. Then, by injecting holes as carriers from the N-type high concentration impurity region 17 side, the negative threshold voltage is changed in a more negative direction, and the threshold voltage is controlled with high accuracy.

  A general semiconductor nonvolatile memory element is used to hold necessary information digitally by controlling a binary value such that a threshold voltage is 0 V or more or 0 V or less and combining a plurality of such elements. . The present invention is different from the conventional utilization method in that only one element is used and information is determined and held in an analog manner by the amount of carriers in the floating state.

  In the present invention, by taking advantage of such a threshold voltage changing function and non-volatile characteristics, carriers are injected into the semiconductor non-volatile memory element in advance before shipment to the customer to adjust the threshold voltage of the semiconductor non-volatile memory element. The circuit characteristics of the semiconductor integrated circuit device including the semiconductor non-volatile memory element are adjusted to a desired value. However, after that, the carrier is not taken in and out during use operation, and advanced rewrite for repetitive rewriting is performed. Reliability is not required for the second gate insulating film.

  In the present invention, carriers are injected into the floating gate electrode as follows. First, in the state where carriers are not injected, the amount of impurities in the N-type channel impurity region 10 is set so that the threshold voltage is a negative value but is higher (positive side) than the original target value.

  Next, in the test stage of the semiconductor integrated circuit device after the semiconductor manufacturing process, the source potential and the control gate electrode potential are set to a common low potential, and the drain potential is changed to a positive high potential. In this state, the floating gate potential depends on the thickness ratio of the first gate insulating film 9, the second gate insulating film 14, and the third gate insulating film 15, and the capacitance ratio determined by the size of the control gate electrode and the floating gate electrode. The drain potential, the source potential, and the control gate electrode potential are intermediate values. By adjusting the size and film thickness, the drain potential is set to a value close to the source potential and the control gate electrode potential. The insulating film 14 is designed so that most of its drain / source voltage is applied.

  In this depletion type NMOS transistor, even if the potential of the control gate electrode 8 is 0V, the drain voltage flows as the drain potential increases because the threshold voltage is a negative value. However, the current characteristic changes from the unsaturated characteristic region to the saturated characteristic region. After switching, it stabilizes to a constant saturation current value independent of the drain potential. Since the potential of the depletion layer end generated on the drain side in the N-type channel impurity region 10 is fixed to a low constant value (pinch-off voltage) determined by the gate-source voltage and the threshold voltage, the drain-source voltage and the pinch-off voltage are fixed. The voltage difference is applied to the depletion layer generated in the first N-type low concentration impurity region. Since this depletion layer does not reach the sufficiently high concentration of the N-type high concentration impurity region 17, the potential of the N-type high concentration impurity region 17 is the same as the drain potential applied to the drain terminal 2 to which it is applied. Thus, it is easy to control the potential difference between the N-type high concentration impurity region 17 and the control gate electrode 8.

  At this time, by arbitrarily setting the concentration and the length in the planar direction of the first N-type low concentration impurity region 18, it is possible to control the spread amount of the depletion layer generated in the N-type low concentration impurity region, The upper limit of the applied drain voltage due to avalanche breakdown can be increased. As a result, the potential applied to the N-type high concentration impurity region 17 can be set to a high value, so that the potential for carrier injection can be ensured even if the second gate insulating film is set thick.

For example, the impurity concentration of the first N-type low concentration region 18 is between 1 × 10 ¹⁷ / cm ³ and 1 × 10 ¹⁸ / cm ³ , and the planar direction from the channel region to the N-type high concentration impurity region 17 is set. By setting the length to 1.5 μm or more, the drain withstand voltage can be set to 20 V or more, and a carrier injection voltage of 20 V or more can be secured.

  Here, for example, when the thickness of the second gate insulating film 14 is set to 400 mm, a tunnel phenomenon can be generated with an applied voltage of about 20 V or more. Therefore, the drain voltage is set to 20 V or more in the drain structure. Thus, positive charge hole injection based on the tunneling phenomenon is realized in the overlapping portion 16 between the N-type high concentration impurity region 17 and the floating gate electrode 7. On the other hand, since the N-type channel impurity region 10 is not more than the pinch-off voltage described above, the N-type channel impurity region 10, the floating gate electrode 7, and the like can be obtained as long as the insulating film thickness corresponding to the pinch-off voltage is secured. The tunneling phenomenon does not occur in the first gate insulating film 9 between.

  As described above, the drain voltage applied in the test stage is preferably a voltage sufficiently higher than the operating voltage of the semiconductor integrated circuit device including the semiconductor nonvolatile memory element. Thus, carriers are prevented from being injected into the floating gate electrode during the fluctuation of the power supply voltage within the operating voltage of the semiconductor integrated circuit device, and the fluctuation of the threshold voltage of the semiconductor nonvolatile memory element and the semiconductor integrated circuit device thereby The change in circuit characteristics can be suppressed. For example, in the above example, the operating voltage of the semiconductor integrated circuit device is desirably 10 V or less. Thus, in order to provide a sufficient potential difference (20 V−10 V = 10 V in the above example) between the operating voltage and the carrier injection voltage, the thickness of the second gate insulating film 2 and the first N-type low concentration impurity It is necessary to set the area condition.

  The amount of carriers to be accumulated in the floating gate electrode can be determined by gradually increasing the drain voltage as shown in FIG. 19, but the hole charge amount accumulated in the floating gate electrode 7 is the drain amount. It can also be controlled by the product of the voltage value and its application time. As described above, since the threshold voltage of the depletion type NMOS transistor further shifts to the negative side according to the accumulated amount of hole charge, a high constant drain voltage is applied until the desired threshold voltage is reached, and the output voltage is It is also possible to adjust the threshold voltage of the N-channel MOSFET with high accuracy during the application time while monitoring.

FIG. 11 is a cross-sectional view of a semiconductor nonvolatile memory device showing a second embodiment of the present invention. 11, in addition to the structure of FIG. 10, the second N-type low-concentration impurity region 19 made of As or P having an impurity concentration of about 2 × 10 ¹⁶ / cm ³ to 2 × 10 ¹⁷ / cm ³ is formed in the first N A type low concentration impurity region 18 is added below. In the case of FIG. 10, although depending on the conditions of the N-type low concentration impurity region 18, it is easy to increase the drain breakdown voltage to about 30V. However, in the depletion layer of the first N-type low-concentration impurity region 18 and the P-type well region 5 therebelow, the extension of the depletion layer toward the first N-type low-concentration impurity region is restricted, and a high breakdown voltage of 30 V or higher Difficult to make. Therefore, by adding the second N-type impurity region 19 as shown in FIG. 11 and ensuring the extension of the depletion layer corresponding to the diffusion depth, a drain breakdown voltage of 30 V or more can be obtained. This is effective in dealing with a semiconductor integrated circuit device having a higher operating voltage and securing a larger margin between the operating voltage and the tunneling voltage.

  FIG. 12 is a cross-sectional view of a semiconductor nonvolatile memory element showing a third embodiment of the present invention. In FIG. 12, an oxide film thicker than the first gate insulating film 9 and the second gate insulating film 14 is formed between the floating gate electrode 7 and the first N-type low concentration impurity region 18. By adopting such a configuration, it is possible to mitigate the increase in electric field between the low potential floating gate electrode 7 and the first N-type low-concentration impurity region 18 generated when the drain voltage is increased. The drain breakdown voltage can be increased to about 60V.

  The thick oxide film 13 may be set to an arbitrary thickness depending on the required degree of relaxation of the electric field, and preferably has a thickness of 1000 mm or more when withstanding a drain voltage exceeding 30V. Further, by forming the LOCOS oxide film in the element isolation region at the same time, an increase in the number of processes can be avoided.

  FIG. 13 is a sectional view of a semiconductor nonvolatile memory element showing a fourth embodiment of the present invention. In FIG. 13, the second N-type low-concentration impurity region 19 in FIG. 12 is extended in the direction toward the source terminal 3 so as to overlap the N-type channel impurity region 10. In addition, a P-type low concentration impurity region 20 having an impurity concentration higher than that of the second N-type low concentration impurity region 19 is formed so as to surround the source terminal.

This P-type low-concentration impurity region 20 is a region that does not exceed the thick oxide film 13 in the vicinity of the first gate insulating film, and B or BF2 has an impurity concentration of about 2 × 10 ¹⁶ / cm ³ to 2 × 10 ¹⁷ / cm ^3. Thus, it is formed at a concentration higher than the concentration of the second N-type low concentration impurity region 19. In this way, the P-type low-concentration impurity region 20 has a higher concentration than the second N-type low-concentration impurity region 19, so that depletion layers on the channel side and the drain side that are generated when the drain voltage is increased are further reduced. It can be extended to the drain side, and is effective when it is necessary to obtain a drain breakdown voltage of 60 V or higher.

  In the first to fourth embodiments so far, as shown in FIGS. 10 to 13, the floating gate electrode and the control gate electrode are stacked using a polycrystalline silicon layer. Such a method using a polycrystalline silicon layer suppresses an increase in gate electrode area and facilitates cost reduction, but increases the number of steps and makes processing difficult. The difficulty is, for example, the selection of dry etching conditions when processing the floating gate electrode and the control electrode and the third oxide film therebetween, the etching resistance of the resist serving as a mask, the polycrystalline silicon stringer generated in the step portion, There are various problems associated with deterioration of flatness due to the high aspect gate electrode structure.

FIGS. 14 to 17 show a method for realizing a semiconductor nonvolatile memory element using only one polycrystalline silicon layer in order to overcome such difficulty. The structure corresponds to each of the structures shown in FIGS. It is said.
First, FIG. 14 shows a fifth embodiment in which the polycrystalline silicon two-layer gate electrode structure of FIG. 10 is formed as one layer.

  FIGS. 14 (2) and (3) are cross-sectional views corresponding to the portions AA 'and BB' in the plan view 14 (1), and the two-layered polycrystalline silicon structure of FIG. The electrode 7 has a single layer structure. As shown in FIG. 14B, the control electrode and the third gate insulating film are not formed on the floating gate electrode 7. Instead, the floating gate electrode 7 extends outside the channel region as shown in FIG. 14A and is arranged so as to overlap the control gate electrode 8 using the impurity diffusion region in the semiconductor substrate. The control gate electrode 8 using the impurity diffusion region in the semiconductor substrate has a potential extraction portion 6. For example, the control gate electrode 8 may be used for both the impurity of the N-type high concentration impurity region 17 and the structure / process, and the extraction portion 6 may be used for the N-type high concentration impurity of the source / drain region.

  Further, the third gate insulating film 15 between the floating gate electrode and the control electrode as used in FIG. 10 is formed between the floating gate electrode and the control gate electrode which is an impurity diffusion region in the semiconductor substrate. In this case, an oxide film formed at the same time as the first gate insulating film formed outside the channel region is used.

  The configuration of FIG. 14 requires two occupied areas of the control gate electrode and the floating gate electrode in the semiconductor integrated circuit device, which leads to an increase in the chip occupied area and an increase in cost. However, since the present invention is not used for a purpose such as a memory array in which a large number of the present semiconductor nonvolatile memory elements are arranged in a semiconductor integrated circuit, the increase in the occupied area is not large, and the increase in cost is caused by the semiconductor integrated circuit device. As a matter of little. On the other hand, as described above, there is an advantage that the effect of stabilizing the quality and reducing the process by eliminating the complexity and difficulty of the process can be enjoyed.

  In the structure of FIG. 14, when a circuit that uses a common low potential by connecting the gate potential, the source potential, and the voltage of the P-type well region with a metal wiring is used, the control electrode of FIG. The impurity 8 may be a P-type high concentration impurity, or may be the P-type well region 5 as it is.

  This is because the non-volatile semiconductor memory device of the present invention is of a normally-on type in which current flows in accordance with the drain voltage even when the gate-source voltage is 0 V due to the presence of the N-type channel impurity region 10. Therefore, if the P-type well region is connected to the source terminal by some metal wiring (not shown) or the like, the eight impurity diffusions serving as the control gate electrode have the same potential relationship even in the P-type.

  FIG. 15 shows a sixth embodiment in which the polycrystalline silicon two-layer gate electrode structure of FIG. 11 is formed as one layer, and the effect is the same as that described in FIG. 15 (2) and 15 (3) are cross-sectional views corresponding to the portions A-A 'and B-B' in the plan view 15 (1).

  FIG. 16 shows a seventh embodiment in which the polycrystalline silicon two-layer gate electrode structure of FIG. 12 is formed as one layer, and the effect is the same as that described in FIG. 16 (2) and 16 (3) are cross-sectional views corresponding to the portions A-A 'and B-B' in the plan view 16 (1).

  FIG. 17 shows an eighth embodiment in which the polycrystalline silicon two-layer gate electrode structure of FIG. 13 is formed as one layer, and the effect is the same as that described in FIG. 17 (2) and 17 (3) are cross-sectional views corresponding to the portions A-A 'and B-B' in the plan view 17 (1).

Next, three types of gate insulating films used in the present invention will be described.
First, the second gate insulating film used when injecting carriers into the floating gate electrode due to the tunneling phenomenon in the invention is preferably a silicon oxide film formed by a thermal oxidation method with high film thickness controllability and film quality stability. In addition, since the carriers are only injected into the floating gate once or several times in the test stage after the semiconductor manufacturing process is completed, no special film formation conditions or additional processing are required to obtain strong resistance to the number of rewrites. On the other hand, the film thickness of the second gate insulating film is such that a desired tunnel current value can be obtained for a drain voltage application sufficiently higher than an operating voltage applied to the semiconductor integrated circuit device in a test process after the semiconductor manufacturing process is completed. Set to a thick film thickness.

  On the other hand, it is desirable that the first gate insulating film 9 and the third gate insulating film 15 have a higher capacitance value. That is, when a drain voltage is applied and holes are injected into the floating gate electrode in the test process, the voltage is efficiently applied to the second gate insulating film, so that the potential of the floating gate electrode determined by capacitive coupling is sufficiently lowered. It is.

  The equivalent capacitive coupling circuit between the drain terminal 2 to which a high potential is applied, the control gate electrode 8 set to a low potential, the P-type well region and the body terminal 4 having the same potential as the P-type well region is shown in FIG. It becomes like this. As can be seen, the first and third gate insulating films have a high capacity, and the ratio of the capacitance to the low-capacitance second gate insulating film having a large insulating film thickness is increased, so that the intermediate potential of this capacitive coupling is increased. As a result, the floating gate voltage 7 is lowered, a high voltage can be applied to the second insulating film 14 between the drain terminal 2 and the floating gate electrode 7, and the tunneling phenomenon can be promoted.

  For this reason, the first and third gate insulating films are required to have a large planar electrode size. This is because the capacitance value can be increased, but an area that is 10 times or more the planar size of the second gate insulating film is sufficient.

  For the purpose of increasing the capacitance value, the first and third gate insulating films are desirably as thin as possible. Since the potentials of the floating gate electrode, the control gate electrode, and the P-type well region are fixed to the same low voltage in terms of circuit, the insulating film thickness is not restricted by the operating voltage of the semiconductor integrated circuit device. Therefore, in the case of a thermal oxide film, a film thickness of about 100 to 200 mm is desirable considering leakage due to the high temperature environment of carriers in the floating electrode.

Further, from the viewpoint of high capacity, it is desirable that the first and third gate insulating films have a higher relative dielectric constant, which can be realized by using SiON, SiN, HfO ₂ or the like rather than a silicon thermal oxide film. Films other than the silicon thermal oxide film generally have large fluctuations in characteristics such as threshold voltage due to instability of characteristics at the film interface. It will not be a problem because it will fit together.

  Further, the thinning of the gate insulating film and the use of a high relative dielectric constant film have an advantage that the gate electrode size can be reduced and the cost can be reduced accordingly. Furthermore, since this method leads to an increase in the capacitance value C per unit area in the general formula (3), the threshold voltage fluctuation amount is reduced with respect to a decrease in Q due to carrier leakage in the floating gate electrode. It also has the advantage of being small.

V = Q / C (3)
As described above, by adopting the semiconductor nonvolatile memory element of the present invention, threshold voltage adjustment is easy and long-term stability is high, and circuit characteristic variation based on element characteristic variation can be absorbed by electrical adjustment in the test process. An accurate semiconductor integrated circuit device can be provided.

  Next, a manufacturing method for manufacturing the semiconductor nonvolatile memory device having the structure of the first embodiment shown in FIG. 10 is described in the process flow of FIGS. 20 (1) to (4) and FIGS. 21 (5) to (8). This will be described with reference to the drawings.

  First, a P-type or N-type semiconductor substrate 1 is prepared, and a P-type well region 5 is formed by performing thermal diffusion after injecting a P-type impurity of B or BF2 into the formation region of the semiconductor nonvolatile memory element by an ion implantation method. (1).

  The polarity of the semiconductor substrate 1 is selected according to the demand of the semiconductor integrated circuit constituting the semiconductor nonvolatile memory element of the present invention. That is, since the potential of the P-type well region is not the lowest potential on the semiconductor integrated circuit and it is desired to electrically isolate the P-type well region, it is desirable to prepare an N-type semiconductor substrate. When the well region has the lowest potential on the semiconductor integrated circuit, a cheaper P-type semiconductor substrate can be used.

The impurity concentration in the P-type well region 5 is a value between 7 × 10 ¹⁵ / cm ³ and 7 × 10 ¹⁶ / cm ³ , and the impurity implantation amount and thermal diffusion conditions are set to a depth of 6 μm to 10 μm. Choose. More specifically, the impurity implantation area density is 1 × 10 ¹² / cm ² to 1 × 10 ¹³ / cm ² , and thermal diffusion is performed at 1100 ° C. to 1200 ° C. for several hours to 10 and several hours.

  Next, a LOCOS method or the like is used to electrically isolate elements from each other, and an element isolation region 13 made of a silicon oxide film is formed around the P-type well region 5 and at the same time, a semiconductor nonvolatile semiconductor surrounded by the element isolation region The memory element region is defined (2).

  Next, an N-type impurity of As or P is implanted into a region to be a drain region of the semiconductor nonvolatile memory element by an ion implantation method, and the N-type high concentration impurity region 17 and the first N-type low concentration impurity region are implanted. 18 is formed (3).

The N-type high-concentration impurity region 17 serves as a lower electrode for tunneling injection of carriers such as electrons and holes to the upper floating gate electrode via a silicon oxide film later. In order to suppress depletion of the surface of the N-type high concentration impurity region, it is desirable to implant and form As with an impurity concentration of 5 × 10 ¹⁸ / cm ³ or more. The implantation energy at this time is set to such a magnitude that it can pass through the oxide film on the surface of the semiconductor substrate, for example, about 100 keV.

The first N-type low-concentration impurity region 18 is implanted with an impurity concentration of 1 × 10 ¹⁷ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less in order to obtain a drain breakdown voltage of a desired value or more. It is desirable to form. Furthermore, by setting the implantation energy to be 90 keV or more, the diffusion can be deeper than the previous N-type high concentration impurity region 17, and the PN with the P-type well region 5 under the N-type high concentration impurity region 17. The junction breakdown voltage can be set high.

  Next, in order to make the semiconductor nonvolatile memory element a normally-on type depletion type MOSFET, ion implantation of As or P N-type impurities into the channel formation scheduled region is performed so that the threshold voltage becomes a desired negative value. The N-type channel impurity region 10 is formed by the method (4).

  Next, by a thermal oxidation method or a CVD method, the first gate insulating film 9 having a thickness of about 100 to 200 mm in the channel formation scheduled region and the film thickness in the drain formation scheduled region are larger than the first gate insulating film. A second gate insulating film 14 having a thickness of about several hundreds of inches is formed (5).

  In order to form a gate insulating film having two thicknesses, a thicker second gate insulating film is first formed as a silicon oxide film by thermal oxidation on the entire surface of the element region, and then the region other than the region where the drain is to be formed is formed. The second gate insulating film is removed by performing a photolithographic technique and etching process using HF, and then the first gate insulating film is formed as a silicon oxide film by a thermal oxidation method.

  In this method, the second gate insulating film is exposed to a thermal oxidation process at the time of forming the first gate insulating film, and the silicon oxide film constituting the second gate insulating film is regrown. However, since the second gate insulating film is already thick, the speed at which oxygen reaches the silicon is reduced during the thermal oxidation process when forming the first gate insulating film, which is a thin gate insulating film. The film thickness growth is very slow and the growth amount is small. Therefore, the film thickness of the second gate insulating film after the second thermal oxidation process is dominantly influenced by the first thermal oxidation process, and the film thickness can be easily predicted.

Next, a polycrystalline silicon layer is deposited on the first and second gate insulating films, and high-concentration impurity implantation is performed by an ion implantation method or a thermal diffusion method so as to be 1 × 10 ¹⁹ / cm ³ or more. Then, the floating gate electrode 7 of the semiconductor nonvolatile memory element is formed by performing a photolithography technique and a dry etching process. At this time, the overlapping portion for injecting carriers by tunneling is set between the floating gate electrode 7 and the second gate insulating film (6).

Next, an insulating film is deposited on the floating gate electrode of the semiconductor nonvolatile memory element by a thermal oxidation method or a CVD method in order to form the third gate insulating film 15. Subsequently, a polycrystalline silicon layer is deposited, and high-concentration impurity implantation is performed by an ion implantation method or a thermal diffusion method so as to be 1 × 10 ¹⁹ / cm ³ or more, and control is performed using a photolithography technique and a dry etching process. The gate electrode 8 is formed by patterning (7).

At this time, the floating gate electrode and the control gate electrode may be collectively formed by one photolithography and dry etching treatment. That is, a polycrystalline silicon layer is deposited on the first and second gate insulating films, and high-concentration impurity implantation is performed by an ion implantation method or a thermal diffusion method so as to be 1 × 10 ¹⁹ / cm ³ or more. Subsequently, a third gate insulating film is deposited as it is by thermal oxidation or CVD, and then a polycrystalline silicon layer is deposited, and a high-concentration impurity is implanted so as to be 1 × 10 ¹⁹ / cm ³ or more. Then, the control gate electrode 8 and the floating gate electrode 7 are formed by batch patterning using a photolithographic technique and a dry etching process.

Next, in order to form the source / drain region 12 of the semiconductor nonvolatile memory element, an N-type impurity of As or P is implanted by an ion implantation method so as to be 1 × 10 ²⁰ / cm ³ or more (8).
The description so far is based on the process flow diagrams of FIGS. 20 (1) to (4) and FIGS. 21 (5) to (8).

  Next, although not shown in the figure, an insulating film made of an oxide film is deposited on the entire surface, a contact hole is formed at a predetermined position, and then the potential of the gate, source, drain, and body of the semiconductor nonvolatile memory element is applied. The metal wiring is formed by sputtering and patterning the metal film.

  In order to manufacture the structure shown in the fifth embodiment in which the two-layer gate electrode structure of polycrystalline silicon in FIG. 10 described in FIG. This is common up to the step of forming the floating gate electrode 7 on the first and second gate insulating films. Thereafter, the source / drain regions 12 of the semiconductor nonvolatile memory element can be formed and manufactured in the same manner. The control gate electrode 8 can be manufactured, for example, using both the impurity of the N-type high concentration impurity region 17 and the structure / process.

Next, a manufacturing method for manufacturing the semiconductor nonvolatile memory element having the structure of the second embodiment shown in FIG. 11 will be described with reference to the process flow charts of FIGS. Since the difference between the second embodiment and the first embodiment is the addition of the second N-type low-concentration impurity region 19 in FIG. 11, FIG. 22 also simplifies the latter half of the process accordingly.
First, a P-type or N-type semiconductor substrate 1 is prepared, and a P-type well region 5 and a second N-type low-concentration impurity region 19 are formed in the semiconductor nonvolatile memory element formation region (1). ).

In this P-type well region 5, the amount of impurity implantation is performed so that the P-type impurity of B or BF2 has a depth of 6 μm to 10 μm at an impurity concentration of 7 × 10 ¹⁵ / cm ³ to 7 × 10 ¹⁶ / cm ^3. And select the thermal diffusion conditions. More specifically, the impurity implantation area density is 1 × 10 ¹² / cm ² to 1 × 10 ¹³ / cm ² , and thermal diffusion is performed at 1100 ° C. to 1200 ° C. for several hours to 10 and several hours.

In the N-type low concentration impurity region 19, P or As N-type impurities are implanted so that the depth is 3 μm to 6 μm at an impurity concentration of 2 × 10 ¹⁶ / cm ³ to 2 × 10 ¹⁷ / cm ^3. And select the heat diffusion conditions. This thermal diffusion may be combined with the heat treatment for forming the P-type well region, or may be performed after that.

  Next, although not shown, a LOCOS method or the like is used to electrically isolate elements from each other, and an element isolation region 13 is formed by a silicon oxide film, and at the same time, a semiconductor nonvolatile memory element region surrounded by the element isolation region Is specified.

  Next, an N-type impurity of As or P is implanted into a region to be a drain region of the semiconductor nonvolatile memory element by an ion implantation method, and the N-type high concentration impurity region 17 and the first N-type low concentration impurity region are implanted. 18 is formed (2).

The N-type high concentration impurity region 17 is preferably formed by implanting As at an impurity concentration of 5 × 10 ¹⁸ / cm ³ or more, and the implantation energy is about 100 keV that can pass through the oxide film on the surface of the semiconductor substrate. Good.

The first N-type low concentration impurity region 18 is preferably formed by implanting P with an impurity concentration of 1 × 10 ¹⁷ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less. By setting the implantation energy at 90 keV or higher, diffusion deeper than the previous N-type high concentration impurity region 17 can be achieved, and the PN junction breakdown voltage with the P-type well region 5 under the N-type high concentration impurity region 17 can be increased. Can be set high.
Thereafter, the N-type channel impurity region described with reference to FIG. 20 (4) is formed, and the first gate insulating film and the second gate insulating film described with reference to FIG. 21 (5) are formed.

Next, returning to FIG. 22 again, a polycrystalline silicon layer is deposited on the first and second gate insulating films, and high-concentration impurity implantation is performed so that the concentration becomes 1 × 10 ¹⁹ / cm ³ or more. Alternatively, the floating gate electrode 7 of the semiconductor nonvolatile memory element is formed by performing a thermal diffusion method and performing a photolithography technique and a dry etching process (3).

Next, the third gate insulating film and the floating gate electrode described with reference to FIG.
Next, in order to form a source / drain region of the semiconductor nonvolatile memory element, an N-type impurity of As or P is implanted by an ion implantation method so as to be 1 × 10 ²⁰ / cm ³ or more (4).

  Next, although not shown in the figure, an insulating film made of an oxide film is deposited on the entire surface, a contact hole is formed at a predetermined position, and then the potential of the gate, source, drain, and body of the semiconductor nonvolatile memory element is applied. The metal wiring is formed by sputtering and patterning the metal film.

  In order to manufacture the structure shown in the sixth embodiment described with reference to FIG. 15 in which the polycrystalline silicon two-layer gate electrode structure of FIG. This is common up to the step of forming the floating gate electrode 7 on the first and second gate insulating films. Thereafter, the source / drain regions 12 of the semiconductor nonvolatile memory element can be formed and manufactured in the same manner. The control gate electrode 8 can be manufactured, for example, using both the impurity of the N-type high concentration impurity region 17 and the structure / process.

  Next, a manufacturing method for manufacturing the semiconductor nonvolatile memory element having the structure of the third embodiment shown in FIG. 12 is described as a process flow of FIGS. 23 (1) to (4) and FIGS. 24 (5) to (6). This will be described with reference to the drawings.

First, a P-type or N-type semiconductor substrate 1 is prepared, a P-type well region 5 is formed in a formation region of a semiconductor nonvolatile memory element, and a second N-type low concentration impurity region 19 and a first N-type impurity region 19 are formed therein. A type low concentration impurity region 18 is formed. The P-type well region 5 and the second N-type low concentration impurity region 19 are formed by the method described in the manufacturing method of the second embodiment, and the first N-type low concentration impurity region 18 is formed of As or P. The N-type impurity is adjusted to an impurity concentration of 1 × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁸ / cm ³ . Further, the position is formed in advance so as to cover the bottom of the thick oxide film formed in the vicinity of the N-type channel impurity region to be formed later (1).

  Next, an element isolation region 13 for electrically isolating elements from each other is formed by a LOCOS method, and then a thick oxide film is formed on the first N-type low concentration impurity region 18. The thick oxide film on the first N-type low-concentration impurity region 18 preferably has a thickness of 1000 mm or more. However, as described with reference to FIG. 12, the method is used together with the LOCOS oxide film 13 in the element isolation region to suppress the increase in the number of processes. You may take (2).

  Next, an N-type impurity region 17 is formed by implanting As or P N-type impurities into the region to be the drain region of the semiconductor nonvolatile memory element by ion implantation. Next, in order to make the semiconductor nonvolatile memory element a normally-on type depletion type MOSFET, an N-type impurity of As or P is implanted into the channel formation planned region by an ion implantation method to form an N-type channel impurity region 10. (3).

  Next, a second gate insulating film having a thickness larger than that of the first gate insulating film is in contact with the LOCOS oxide film previously formed on a part of the drain formation scheduled region by a thermal oxidation method or a CVD method. 14 is formed on the N-type high concentration impurity region 17, and then the first gate insulating film 9 is formed on the channel formation scheduled region. As shown in FIG. 21 (5), the gate insulating film having two thicknesses is formed by first forming a thick second gate insulating film and then the second gate in a region other than the region where the drain is to be formed. The insulating film is removed by performing a photolithographic technique and an etching process using HF, and then a first gate insulating film is formed (4).

Next, a polycrystalline silicon layer is deposited on the first and second gate insulating films, and high-concentration impurity implantation is performed by an ion implantation method or a thermal diffusion method so as to be 1 × 10 ¹⁹ / cm ³ or more. The floating gate electrode 7 of the semiconductor nonvolatile memory element is formed by performing a photolithography technique and a dry etching process. At this time, the floating gate electrode 7 and the second gate insulating film 14 are set to overlap each other for carrier injection by tunneling (5).

Next, although not shown, the third gate insulating film 15 and the control gate electrode 8 are formed in the same manner as described with reference to FIG.
Then, in order to form the source / drain regions of the semiconductor nonvolatile memory element, an N-type impurity of As or P is implanted by ion implantation so as to be 1 × 10 ²⁰ / cm ³ or more (6).
The description so far is based on the process flow diagrams of FIGS. 23 (1) to (4) and FIGS. 24 (5) to (6).

  Next, although not shown in the figure, an insulating film made of an oxide film is deposited on the entire surface, a contact hole is formed at a predetermined position, and then the potential of the gate, source, drain, and body of the semiconductor nonvolatile memory element is applied. The metal wiring is formed by sputtering and patterning the metal film.

  In order to manufacture the structure shown in the seventh embodiment in which the two-layer gate electrode structure of polycrystalline silicon shown in FIG. This is common up to the step of forming the floating gate electrode 7 on the first and second gate insulating films. Thereafter, the source / drain regions 12 of the semiconductor nonvolatile memory element can be formed and manufactured in the same manner. The control gate electrode 8 can be manufactured, for example, using both the impurity of the N-type high concentration impurity region 17 and the structure / process.

Next, a manufacturing method for manufacturing the semiconductor nonvolatile memory element having the structure of the fourth embodiment shown in FIG. 13 will be described with reference to the process flow charts of FIGS.
First, a P-type or N-type semiconductor substrate 1 is prepared, and a P-type low-concentration impurity region 20 and a second N-type low-concentration impurity region 19 are partially overlapped with a formation region of a semiconductor nonvolatile memory element. Form. The N-type low-concentration impurity region 19 is formed by using a P-type or As-type N-type impurity so as to have a depth of 3 μm to 6 μm at an impurity concentration of 2 × 10 ¹⁶ / cm ³ to 2 × 10 ¹⁷ / cm ^3. The implantation and thermal diffusion conditions are selected, and the P-type low-concentration impurity region 20 is simultaneously N-type with an impurity concentration of about 2 × 10 ¹⁶ / cm ³ to 2 × 10 ¹⁷ / cm ³ for B or BF 2 as described with reference to FIG. By setting the concentration higher than that of the low concentration impurity region 19, the drain breakdown voltage is improved (1).

Next, although not shown, the first N-type low-concentration impurity region 18 is formed in a later drain formation planned region by using As or P N-type impurities from 1 × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁸ / cm. The impurity concentration is adjusted to be up to ³ .

  Next, an element isolation region 13 for electrically isolating elements from each other is formed by a LOCOS method, and then a thick oxide film is formed on the first N-type low concentration impurity region 18. The thick oxide film on the first N-type low-concentration impurity region 18 preferably has a thickness of 1000 mm or more. However, as described with reference to FIG. 12, the method is used together with the LOCOS oxide film 13 in the element isolation region to suppress the increase in the number of processes. You may take (2).

Next, although not shown, the N-type channel impurity region 10 and the first and second gate insulating films 9 and 14 are formed.
Next, a polycrystalline silicon layer is deposited on the first and second gate insulating films, and high-concentration impurity implantation is performed by an ion implantation method or a thermal diffusion method so as to be 1 × 10 ¹⁹ / cm ³ or more. Then, the floating gate electrode 7 of the semiconductor nonvolatile memory element is formed by performing a photolithography technique and a dry etching process (3).

Next, although not shown, the third gate insulating film 15 and the control gate electrode 8 are formed.
Next, in order to form a source / drain region of the semiconductor nonvolatile memory element, an N-type impurity of As or P is implanted by an ion implantation method so as to be 1 × 10 ²⁰ / cm ³ or more (4).

  Next, although not shown in the figure, an insulating film made of an oxide film is deposited on the entire surface, and after a contact hole is formed at a predetermined position, a metal is applied to give the potential of the gate, source, drain, and body of the semiconductor nonvolatile memory element. Wiring is formed by sputtering and patterning a metal film.

  In order to manufacture the structure shown in the eighth embodiment described with reference to FIG. 17 in which the polycrystalline silicon two-layer gate electrode structure of FIG. This is common up to the step of forming the floating gate electrode 7 on the first and second gate insulating films. Thereafter, the source / drain regions 12 of the semiconductor nonvolatile memory element can be formed and manufactured in the same manner. The control gate electrode 8 can be manufactured, for example, using both the impurity of the N-type high concentration impurity region 17 and the structure / process.

  In the manufacturing methods of the first to fourth embodiments, the methods for forming the first insulating film and the second insulating film are common. If this is the first manufacturing method for forming the gate insulating film, the following second to fifth methods can be employed for the purpose of improving performance or reducing costs.

The second method does not use the three-step process of forming the thick oxide film, partially removing the oxide film, and forming the thin oxide film in the first method, but a single thermal oxidation process. Thus, the first and second thickness gate insulating films are simultaneously formed.
Specifically, as shown in FIG. 26A, first, the N-type high concentration impurity region 17 is first formed with a high impurity concentration of 1 × 10 ¹⁹ / cm ³ or more using As.

  Next, accelerated oxidation is performed only on the N-type high-concentration impurity region 17 by generating a gate insulating film by wet oxidation using water vapor or by a pyrogenic oxidation method in which oxygen gas and hydrogen gas are introduced into the furnace and reacted. The shape shown in FIG. 26 (2) is obtained by thickening the effect and forming other regions thin.

In this case, for example, if the thickness of the first gate insulating film is 150 mm, the thickness of the second gate insulating film can be about 300 mm. This accelerated oxidation effect becomes more prominent due to the ingress and reaction of oxygen as the degree of disorder of the lattice of the semiconductor substrate increases. Therefore, if the impurity concentration in the semiconductor substrate is high, whether the impurity is N-type or P-type, the lattice disorder Can be earned according to However, particularly when used as a gate insulating film, an oxide film grown on an N-type impurity is desirable. Therefore, this method can be said to be an effective method for an N-channel type semiconductor nonvolatile memory element. Here, the reason why the P-type impurity is not preferable is that the P-type impurity enters the oxide film during the thermal oxidation process, so that the deterioration of the oxide film becomes remarkable and the application to the present invention is inappropriate.
The above-described method has an effect that the three-stage process can be reduced to one stage, and the process cost and the process time can be reduced.

Next, a third method for forming the first and second gate insulating films will be described with reference to FIGS.
In the third method, first, a polycrystalline silicon layer 21A having a thickness of 100 to 400 mm is deposited in advance on the entire surface (1).

Next, the polycrystalline silicon layer 21A in a region other than the second gate insulating film planned region is removed by a photolithography technique and an etching technique to leave a polycrystalline silicon layer 21B (2).
Next, thermal oxidation is performed to form a first gate insulating film in that state, and silicon oxide films (9, 14) are formed on the semiconductor substrate. At that time, the second gate insulating film is set to a thickness at which the polycrystalline silicon 21B is completely oxidized by the thermal oxidation process at the time of generating the first gate insulating film. It can be composed of an oxide film obtained by oxidizing polycrystalline silicon. The reason why polycrystalline silicon is used here is that the oxidation speed can be 1.5 to 2 times faster than that of normal single crystal silicon due to the disorder of the lattice contained therein (3).

  Compared with the first method, this third method does not require a long-time and high-temperature heat treatment to form a thick second gate insulating film, so that N-type channel impurities and first and second N-type It has the effect of suppressing the dispersion of relatively low-concentration impurities such as low-concentration impurities due to high-temperature heat treatment, and promoting higher accuracy of device characteristics.

  The fourth method will be described based on FIGS. 28 (1) to (3). First, a base silicon oxide film having a thickness of 10 to 100 Å is formed in advance on the entire surface by a thermal oxidation method, and then a 100 to 200 Ｓｉ SiN layer 22 is deposited on the entire surface by a method such as LPCVD (1).

Next, the SiN layer in a region other than the first gate insulating film planned region is removed by photolithography (2).
Next, in this state, a silicon oxide film having a film thickness of about several hundreds of inches for forming the second gate insulating film is formed by a thermal oxidation method. At that time, since the first gate insulating film is covered with SiN having low reactivity, an oxide film hardly grows thereon. As a result, the first gate insulating film can be composed of a silicon oxide film of several tens of liters and a stacked film of 100 to 200 liters of SiN, and the second gate insulating film can be composed of several hundreds of liters of silicon film (3).

  In the fourth method, the capacity of the thick first gate insulating film can be increased, and the charge Q can be reduced due to the reduction of the gate electrode size and the associated cost reduction, the leakage of carriers in the floating gate electrode, and the like. On the other hand, there is an advantage that the threshold voltage fluctuation amount can be reduced.

  The fifth method will be described based on FIGS. 29 (1) to (4). First, as in the first method, a second gate insulating film having a thickness of 100 to 1000 mm is formed as a silicon oxide film by thermal oxidation on the entire surface (1).

Next, as in the first method, the second gate insulating film in the channel formation scheduled region is removed by the photolithography technique and the etching technique (2).
Next, the first gate insulating film is formed by a thermal oxidation method, but here it is thinner than the first method and has a thickness of 30 to 100 mm (3).

  Next, thermal nitriding is performed at a temperature of 1000 ° C. or higher in an ammonia atmosphere. Then, nitrogen diffuses to the interface with the semiconductor substrate under the first gate insulating film and reacts with the semiconductor substrate to form SiN having a thickness of about 1 to 20 mm. On the other hand, since the second gate insulating film is sufficiently thick, the amount of nitrogen reaching the interface with the semiconductor substrate by diffusion is very small, and SiN having a high insulating property is not formed so as to inhibit carrier tunneling ( 4).

  Since the silicon oxide film constituting the first gate insulating film in the fifth method is as thin as 100 mm or less, there is a concern about the dissipation of carriers in the floating gate electrode due to a leakage current at a high temperature. However, since high insulation is obtained by SiN under the oxide film, this leakage is suppressed and at the same time, the capacity of the first gate insulating film can be increased.

  For the formation of SiN, the fourth method is performed in the same manner. However, the CVD method such as the fourth method has a problem that the controllability of the film thickness of 100 mm or less is deteriorated and the element characteristics vary. In the method by thermal nitriding such as the fifth method, it is possible to stably form thinner SiN, which is effective for improving the accuracy of device characteristics.

  The present invention can be applied not only to the step-down series regulators and voltage detectors described so far. By adopting a memory terminal capable of varying the threshold voltage by an input electric signal from the input adjustment terminal, the output voltage can be varied by the input electric signal in various semiconductor integrated circuit devices including the reference voltage circuit. Therefore, it goes without saying that the present invention can be applied to uses other than the power management IC.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Drain terminal 3 Source terminal 4 Body terminal 5 P-type well region 6 Gate electrode 7 Floating gate electrode 8 Control gate electrode 9 First gate insulating film 10 N-type channel impurity region 11 P-type channel impurity region 12 N-type Source / drain region 13 LOCOS oxide film 14 Second gate insulating film 15 Third gate insulating film 16 Carrier injection region 17 N type high concentration impurity region 18 First N type low concentration impurity region 19 Second N type low Concentration impurity region 20 P-type low concentration impurity region 21 Polycrystalline silicon layer 22 SiN layer 100 Reference voltage circuit 101 Error amplifier 102 Resistor element 103 Voltage divider circuit 104 PMOS output element 105 Ground terminal 106 Power supply terminal 107 Output terminal 108 Comparator 109 Terminal A
110 Terminal B
111 Terminal C
112 Input adjustment terminal 200 Unit resistance element 201 Resistance group 1
202 Resistance group 2
203 Resistance group 3
204 Resistance group 4
301 Fuse 1
302 Fuse 2
303 Fuse 3
304 Fuse 4
401 Enhanced NMOS transistor 402 Depletion type NMOS transistor 403 Power supply terminal 404 Ground terminal 405 Reference voltage output terminal 406 Input adjustment terminal

Claims (22)

A semiconductor substrate;
A first conductivity type well region formed in the semiconductor substrate;
A high-concentration source region and a first high-concentration drain region having a high-concentration impurity of a second conductivity type formed separately in the well region;
A first gate insulating film formed on the semiconductor substrate between the high concentration source region and the first high concentration drain region and adjacent to the high concentration source region;
A second gate insulating film formed on the semiconductor substrate between the high-concentration source region and the first high-concentration drain region and adjacent to the first high-concentration drain region;
A second high-concentration drain region of a second conductivity type formed in a region that is separated from the high-concentration source region, includes a region under the second gate insulating film, and overlaps the first high-concentration drain region And the first high-concentration drain region and the second high-concentration drain, which are separated from the high-concentration source region and include regions under the first gate insulating film and under the second gate insulating film. A first low-concentration drain region of a second conductivity type formed in a region overlapping with the region, and between the high-concentration source region and the first low-concentration drain region under the first gate insulating film A channel impurity region of the second conductivity type formed on the floating gate electrode made of polycrystalline silicon containing high-concentration impurities formed on the first gate insulating film and the second gate insulating film;
A third gate insulating film formed on the floating gate electrode;
A control gate electrode made of polycrystalline silicon containing a high concentration impurity formed on the third gate insulating film;
Have
The second gate insulating film has a uniform thickness greater than that of the first gate insulating film,
The well region includes the high-concentration source region, the first high-concentration drain region, the second high-concentration drain region, the first low-concentration drain region, and the channel impurity region. A semiconductor non-volatile memory device, wherein the semiconductor non-volatile memory device is formed to a deeper position .   The first high-concentration drain region, the second high-concentration drain region, and a region including a part of the first low-concentration drain region are formed to a position deeper than the first low-concentration drain region. The semiconductor nonvolatile memory element according to claim 1, further comprising a second low-concentration drain region.   The first gate insulating film and the second gate insulating film are formed between the first gate insulating film and the second gate insulating film and on a region including a part of the first low-concentration drain region. 3. The semiconductor nonvolatile memory element according to claim 2, further comprising an insulating film having a thickness greater than that of the gate insulating film. The second low concentration drain region is disposed in a region including the second high concentration drain region and the first low concentration drain region,
4. The semiconductor nonvolatile memory device according to claim 3, wherein the well region includes the high-concentration source region and the channel impurity region, and has a higher impurity concentration than the second low-concentration drain region. The impurity in the second low-concentration drain region is As or P of 2 × 10 ¹⁶ cm ³ or more and 2 × 10 ¹⁷ cm ³ or less, according to any one of claims 2 to 4. Semiconductor non-volatile memory device. A semiconductor substrate;
A first conductivity type well region formed in the semiconductor substrate;
A high-concentration source region and a first high-concentration drain region having a high-concentration impurity of a second conductivity type formed separately in the well region;
A first gate insulating film formed on the semiconductor substrate between the high concentration source region and the first high concentration drain region and adjacent to the high concentration source region;
A second gate insulating film formed on the semiconductor substrate between the high-concentration source region and the first high-concentration drain region and adjacent to the first high-concentration drain region;
A second high-concentration drain region of a second conductivity type formed in a region that is separated from the high-concentration source region, includes a region under the second gate insulating film, and overlaps the first high-concentration drain region And the first high-concentration drain region and the second high-concentration drain, which are separated from the high-concentration source region and include regions under the first gate insulating film and under the second gate insulating film. A first low-concentration drain region of a second conductivity type formed in a region overlapping with the region, and between the high-concentration source region and the first low-concentration drain region under the first gate insulating film A channel impurity region of the second conductivity type formed on the floating gate electrode made of polycrystalline silicon containing high-concentration impurities formed on the first gate insulating film and the second gate insulating film;
A control gate electrode made of a diffusion region having a high-concentration impurity of the second conductivity type, formed in the well region at a position separated from the channel impurity region;
A third gate insulating film formed between the floating gate electrode extending above the diffusion region serving as the control gate electrode and the diffusion region serving as the control gate electrode;
The second gate insulating film is thicker and more uniform than the first gate insulating film,
The well region includes the high-concentration source region, the first high-concentration drain region, the second high-concentration drain region, the first low-concentration drain region, and the channel impurity region. A semiconductor non-volatile memory device, wherein the semiconductor non-volatile memory device is formed to a deeper position . The impurity of the first high-concentration drain region is As or P having a concentration of 1 × 10 ²⁰ cm ³ or more;
The impurity of the second high-concentration drain region is As or P of 5 × 10 ¹⁸ cm ³ or more,
The impurity in the first low-concentration drain region is As or P of 1 × 10 ¹⁷ cm ³ or more and 1 × 10 ¹⁸ cm ³ or less,
7. The semiconductor nonvolatile memory element according to claim 1, wherein the impurity in the well region is boron having a concentration of 7 × 10 ¹⁵ cm ³ to 7 × 10 ¹⁶ cm ³ .   8. The semiconductor nonvolatile memory element according to claim 1, wherein the first gate insulating film has a thickness of 100 to 200 mm. 9. The semiconductor nonvolatile memory element according to claim 1, wherein the first gate insulating film is SiON and the second gate insulating film is SiO _{2. 9} . 10. The semiconductor nonvolatile memory element according to claim 1, wherein the first gate insulating film is SiN and the second gate insulating film is SiO _2. 10. A P-type well region forming step of forming a P-type well region made of a P-type impurity on a semiconductor substrate;
An element isolation insulating film forming step of forming a LOCOS oxide film around the P-type well region;
An N-type high-concentration region forming step of forming an N-type high-concentration region made of N-type impurities in the drain formation scheduled region;
An N-type low-concentration region forming step for forming a first N-type low-concentration impurity region, which has a lower N-type impurity concentration than the N-type high-concentration region and is deeply diffused;
A channel region forming step of forming an N-type impurity region in a channel formation scheduled region in the P-type well region;
A second gate insulating film having a uniform thickness is formed in the drain formation planned region so as to overlap the N-type high concentration region, and the channel formation planned region is thinner than the second gate insulating film. A gate insulating film forming step of forming one gate insulating film;
A floating gate electrode made of a polycrystalline silicon layer containing impurities is formed on the first gate insulating film and the second gate insulating film, and a third gate insulating film is formed on the floating gate electrode. Forming a control gate electrode made of a polycrystalline silicon layer containing impurities on the third gate insulating film; and
A source / drain formation step of forming an N-type impurity region in the source formation scheduled region and the drain formation scheduled region;
A method for manufacturing a semiconductor non-volatile memory device.   The P-type well region forming step includes a step of forming a second N-type low concentration region diffused deeper than the first N-type low concentration impurity region in the drain formation scheduled region. The method for manufacturing a semiconductor nonvolatile memory element according to claim 11. A P-type well region forming step of forming a P-type well region made of a P-type impurity on a semiconductor substrate;
In the P-type well region, a first N-type low-concentration impurity region and a second N-type low-concentration impurity region having a lower impurity concentration than that of the first N-type low-concentration impurity region and deeply diffused are formed. An N-type low concentration region forming step;
An element isolation insulating film forming step of forming a LOCOS oxide film around the P-type well region and on the first N-type low-concentration impurity region;
An N-type high-concentration region forming step of forming an N-type high-concentration region made of N-type impurities in the drain formation scheduled region;
A channel region forming step of forming an N-type impurity region in a channel formation scheduled region in the P-type well region;
A second gate insulating film is formed on a part of the N-type high concentration region in contact with the LOCOS oxide film formed on the first N-type low concentration impurity region. A gate insulating film forming step of forming a first gate insulating film thinner than the second gate insulating film;
A floating gate electrode made of a polycrystalline silicon layer containing impurities is formed on the first gate insulating film and the second gate insulating film, and a third gate insulating film is formed on the floating gate electrode. Forming a control gate electrode made of a polycrystalline silicon layer containing impurities on the third gate insulating film; and
A source / drain formation step of forming an N-type impurity region in the source formation scheduled region and the drain formation scheduled region;
A method for manufacturing a semiconductor non-volatile memory device. A first low-concentration region forming step of forming a P-type low-concentration impurity region and a second N-type low-concentration impurity region on a semiconductor substrate so as to partially overlap;
A second low concentration region forming step for forming a first N type low concentration impurity region in the second N type low concentration impurity region;
An element isolation insulating film forming step of forming a LOCOS oxide film around the P-type low-concentration impurity region and the second N-type low-concentration impurity region and on the first N-type low-concentration impurity region;
An N-type high-concentration region forming step of forming an N-type high-concentration region made of N-type impurities in the drain formation scheduled region;
A channel region forming step of forming an N-type impurity region in a channel formation scheduled region in the P-type low-concentration impurity region;
A second gate insulating film is formed on a part of the N-type high concentration region in contact with the LOCOS oxide film formed on the first N-type low concentration impurity region. A gate insulating film forming step of forming a first gate insulating film thinner than the second gate insulating film;
A floating gate electrode made of a polycrystalline silicon layer containing impurities is formed on the first gate insulating film and the second gate insulating film, and a third gate insulating film is formed on the floating gate electrode. Forming a control gate electrode made of a polycrystalline silicon layer containing impurities on the third gate insulating film; and
A source / drain formation step of forming an N-type impurity region in the source formation scheduled region and the drain formation scheduled region;
A method for manufacturing a semiconductor non-volatile memory device.   15. The method of manufacturing a semiconductor nonvolatile memory element according to claim 11, wherein the gate insulating film forming step includes a step of simultaneously forming the first gate insulating film and the second gate insulating film. .   In the step of forming the gate insulating film, a polycrystalline silicon layer having a thickness of 100 to 400 mm is formed, only the polycrystalline silicon layer on the channel formation scheduled region is removed, and the polycrystalline silicon layer remaining without being removed is removed. 15. The method of manufacturing a semiconductor nonvolatile memory element according to claim 11, further comprising: forming the second gate insulating film by completely converting the film into a silicon oxide film. The gate insulating film forming step includes
A silicon oxide film having a thickness of 10 to 100 mm is formed in the semiconductor non-volatile memory element formation region by a thermal oxidation method, and a silicon nitride film of 100 to 200 mm is deposited on the silicon oxide film. 1 gate insulating film is formed,
The method includes forming the second gate insulating film in the drain formation scheduled region by removing only the silicon nitride film on a region other than the channel formation scheduled region and forming a silicon oxide film by a thermal oxidation method. The method for manufacturing a semiconductor nonvolatile memory element according to any one of 11 to 14. In the gate insulating film forming step, a gate insulating film made of a silicon oxide film having a thickness of 100 to 1000 mm is formed by a thermal oxidation method, and only the gate insulating film on the channel formation scheduled region is removed. Forming a gate insulating film,
Next, a silicon oxide film having a thickness of 30 to 100 mm is formed by a thermal oxidation method. A silicon nitride film having a thickness of 1 to 20 mm is formed under the silicon oxide film having a thickness of 30 to 100 mm in an ammonia atmosphere at 1000 ° C. The method for manufacturing a semiconductor nonvolatile memory element according to claim 11, comprising a step of forming the first gate insulating film by forming the first gate insulating film by a thermal nitridation method that performs heat treatment as described above. A P-type well region forming step of forming a P-type well region made of a P-type impurity on a semiconductor substrate;
An element isolation insulating film forming step of forming a LOCOS oxide film around the P-type well region;
An N-type high-concentration region forming step of forming an N-type high-concentration region made of N-type impurities in the drain formation scheduled region;
An N-type low-concentration region forming step for forming a first N-type low-concentration impurity region, which has a lower N-type impurity concentration than the N-type high-concentration region and is deeply diffused;
A channel region forming step of forming an N-type impurity region in a channel formation scheduled region in the P-type well region;
A second gate insulating film having a uniform thickness is formed in the drain formation planned region so as to overlap the N-type high concentration region, and the channel formation planned region is thinner than the second gate insulating film. A gate insulating film forming step of forming one gate insulating film;
Forming a floating gate electrode made of a polycrystalline silicon layer containing an impurity on the first gate insulating film and the second gate insulating film; and
A source / drain formation step of forming an N-type impurity region in the source formation scheduled region and the drain formation scheduled region;
A method for manufacturing a semiconductor non-volatile memory device.   The P-type well region forming step includes a step of forming a second N-type low concentration region diffused deeper than the first N-type low concentration impurity region in the drain formation scheduled region. The method for manufacturing a semiconductor nonvolatile memory element according to claim 19. A P-type well region forming step of forming a P-type well region made of a P-type impurity on a semiconductor substrate;
In the P-type well region, a first N-type low-concentration impurity region and a second N-type low-concentration impurity region having a lower impurity concentration than that of the first N-type low-concentration impurity region and deeply diffused are formed. An N-type low concentration region forming step;
An element isolation insulating film forming step of forming a LOCOS oxide film around the P-type well region and on the first N-type low-concentration impurity region;
An N-type high-concentration region forming step of forming an N-type high-concentration region made of N-type impurities in the drain formation scheduled region;
A channel region forming step of forming an N-type impurity region in a channel formation scheduled region in the P-type well region;
A second gate insulating film is formed on a part of the N-type high concentration region in contact with the LOCOS oxide film formed on the first N-type low concentration impurity region. A gate insulating film forming step of forming a first gate insulating film thinner than the second gate insulating film;
A gate electrode forming step of forming a floating gate electrode made of a polycrystalline silicon layer containing impurities on the first gate insulating film and the second gate insulating film;
A source / drain formation step of forming an N-type impurity region in the source formation scheduled region and the drain formation scheduled region;
A method for manufacturing a semiconductor non-volatile memory device. A first low-concentration region forming step of forming a P-type low-concentration impurity region and a second N-type low-concentration impurity region on a semiconductor substrate so as to partially overlap;
A second low concentration region forming step for forming a first N type low concentration impurity region in the second N type low concentration impurity region;
An element isolation insulating film forming step of forming a LOCOS oxide film around the P-type low-concentration impurity region and the second N-type low-concentration impurity region and on the first N-type low-concentration impurity region;
An N-type high-concentration region forming step of forming an N-type high-concentration region made of N-type impurities in the drain formation scheduled region;
A channel region forming step of forming an N-type impurity region in a channel formation scheduled region in the P-type low-concentration impurity region;
A second gate insulating film is formed on a part of the N-type high concentration region in contact with the LOCOS oxide film formed on the first N-type low concentration impurity region. A gate insulating film forming step of forming a first gate insulating film thinner than the second gate insulating film;
Forming a floating gate electrode made of a polycrystalline silicon layer containing an impurity on the first gate insulating film and the second gate insulating film; and
A source / drain formation step of forming an N-type impurity region in the source formation scheduled region and the drain formation scheduled region;
A method for manufacturing a semiconductor non-volatile memory device.

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