KR20160095637A - Semiconductor nonvolatile memory element and manufacturing method thereof - Google Patents

Abstract

A device constituting a constant current source in a semiconductor-integrated circuit device uses a non-volatile semiconductor memory device. The non-volatile semiconductor memory device includes a control gate electrode, a floating gate electrode, source and drain terminals, a first thin gate insulation film under the control gate electrode, and a second gate insulation film which has a thickness for preventing damage even when a voltage exceeding an operating voltage of the semiconductor-integrated circuit device is applied. A charge exceeding the operating voltage is injected from the drain terminal through the second gate insulation film to adjust a threshold voltage. Accordingly, the normally-on type non-volatile semiconductor memory device can prevent leakage of an injection carrier within an operating voltage range.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor nonvolatile memory device,

The present invention relates to a semiconductor nonvolatile memory device capable of varying a threshold voltage by applying an electric signal from the outside, and a manufacturing method thereof.

An electronic circuit used in an electronic device is driven by a power source such as a battery. If the voltage of the power source fluctuates, the electronic circuit may malfunction or cause various abnormal phenomena. Therefore, It is general that a power management IC such as monitoring the fluctuation of the power source is provided between the electronic circuit and the power source to perform stable operation. Particularly in a semiconductor integrated circuit device such as a microcomputer or a CPU in which a low voltage is recently being developed, there is a demand for a high accuracy in the constant voltage output of the power management IC and the voltage value to be monitored.

As a power management IC for outputting a constant voltage from a power source to an electric circuit, for example, a step-down type series regulator shown in Fig. 3 can be mentioned.

In this semiconductor integrated circuit device, the power supply voltage applied between the ground terminal 105 and the power supply terminal 106 is divided by the PMOS output element 104 and the voltage dividing circuit 103 composed of the resistance element 102 . The voltage divided by the resistance element 102 is input to one input terminal of the error amplifier 101 and compared with a constant reference voltage value generated from the reference voltage circuit 100 and the error amplifier 101 The input voltage of the PMOS output element 104 is controlled to change the source / drain resistance of the PMOS output element 104. [ As a result, the output terminal 107 has a function of outputting a constant output voltage having no dependency on the power supply voltage in accordance with the reference voltage value of the reference voltage circuit 100 and the resistance voltage division ratio of the voltage division circuit 103. [ This output voltage is calculated by the following equation (1).

Output voltage = reference voltage value x voltage division circuit resistance division ratio (1)

To adjust the output voltage, the resistance value of the resistance element 102 is changed by a method described later, thereby changing the partial pressure ratio of the voltage dividing circuit 103 and setting the desired output voltage value based on the equation (1). Therefore, the voltage dividing circuit of the semiconductor integrated circuit needs to be processed and modified for each target output voltage.

Also, as shown in Fig. 4, a voltage detector having a function of outputting a signal when the power supply voltage becomes a constant voltage is also one of the power management ICs.

In this semiconductor integrated circuit device, the power supply voltage input from the power supply terminal 106 is converted into a voltage divided by the voltage dividing circuit 103 composed of the resistance element 102, and the reference voltage value of the reference voltage circuit 100 Is compared by the comparator 108, and the voltage signal is outputted from the output terminal 107 by the magnitude of the comparison. The power supply voltage is monitored by such a mechanism, and a voltage detector having a function of outputting a signal for performing a process to be performed when the voltage is equal to or higher than a predetermined voltage is realized.

4, the voltage division ratio of the voltage dividing circuit 103 is changed by changing the resistance value of the resistance element 102, and a desired voltage detection value is set based on the expression (1). Therefore, the voltage dividing circuit of the semiconductor integrated circuit device needs to be processed and modified for each target output voltage.

As a resistance element used in a voltage-dividing circuit of a semiconductor integrated circuit device, a diffusion resistor in which impurities of a conductivity type opposite to that of the semiconductor substrate are injected into the single-crystal silicon semiconductor substrate or a resistor made of polycrystalline silicon into which impurities are implanted is used. In the design of the voltage dividing circuit, when a plurality of resistors are used, their length, width, and resistivity are all set to be the same. Thus, even if the shape deviation and the impurity implantation deviation during the etching process for determining the shape are equally applied to the respective resistors, even if the absolute value of the resistors deviates, the resistance ratio between the resistors can be kept constant It is because.

Fig. 5 shows a case in which a resistance element having a constant resistance value based on the constant shape and constant resistivity is used in the voltage dividing circuit. Various resistance values are realized by connecting the unit resistance elements 200 in series or in parallel, like the resistance groups 201 to 204 of FIG. As described above, since the unit resistance element 200 is a resistance element having the same shape and the same resistivity, the resistance ratio of the resistance group composed of a unit resistance element having a high resistance ratio can be maintained with high accuracy.

Fuses 301 to 304 made of polycrystalline silicon, for example, are provided in parallel to the resistors 201 to 204 so that they can be cut by laser irradiation from the outside. The resistance value between the terminal 109 and the terminal 110 can be changed as required according to the cut / cut of the fuse by the laser irradiation. The terminal 110 is connected to the terminal 110 through the terminal 110,

As described above, in the voltage dividing circuit having a high-precision resistance ratio, the desired partial pressure ratio can be obtained with high precision by laser cutting the polysilicon fuse, and a product having various target output voltages can be obtained while using the same semiconductor integrated circuit device So that it can be produced.

A general method of adjusting the output voltage is as shown in Fig.

First, the output voltage of a finished product at the semiconductor processing factory is measured as it is (Fig. 2 (1)). Next, the polycrystalline silicon fuse provided in the voltage dividing circuit is laser-processed based on a calculation formula or a database prepared in advance according to the output voltage to trim the output voltage (Fig. 2 (2)). Finally, the output voltage of the processed product is measured again, and it is confirmed whether or not it falls within the desired specifications (Fig. 2 (3)). Products not included in the specifications are not shipped here. There is also an on-line trimming method that gradually processes the resistor while monitoring the output voltage and stops processing when the desired output voltage is reached. The method of FIG. 2 is called an offline trimming method in contrast to the online trimming method.

Next, reference voltage circuits used in the same manner in Figs. 3 and 4 will be described with reference to Figs. 6 (1) and (2).

The reference voltage circuit is composed of a depression type NMOS transistor 402 and an enhancement type NMOS transistor 401 in the most basic circuit of the related art. 6 (1), each transistor is formed on the P-type well region 5 in the semiconductor substrate 1, and the gate electrode 6, the gate insulating film 9, the N-type source / Type channel impurity region 10 in the depression type NMOS transistor 402 is the impurity region for determining the threshold voltage to be formed below the gate insulating film 9, And the P-type channel impurity region 11 is formed in the enhancement type NMOS transistor 401. And has a drain terminal 2, a source terminal 3, and a body terminal 4 for fixing the potential of the P-type well region for controlling the transistor operation.

Such a depression type NMOS transistor 402 and an enhancement type NMOS transistor 401 are connected in series between a power supply terminal 403 and a ground terminal 404 as shown in Fig. 6 (2) Type NMOS transistor 401 is input to the drain terminal 2 of the enhancement type NMOS transistor 401 which is a load element by outputting a constant current from the constant current source 402 and supplies the voltage generated at the drain terminal of the enhancement type NMOS transistor 401 to a constant voltage To the reference voltage output terminal 405 (see, for example, Patent Document 1).

When the threshold voltage and the transconductance of the depression type NMOS transistor are denoted by Vtd and Ktd and the threshold voltage and the transconductance of the enhancement type NMOS transistor are denoted by Vte and Kte, ).

Reference voltage circuit constant voltage = √ (Ktd / Kte) × | Vtd | + Vte (2)

That is, the deviation caused in the output voltage of the equation (1) is caused by a variation in each parameter for determining the constant voltage output from the reference voltage circuit. This deviation is absorbed by adjustment of the resistance / voltage ratio of the voltage divider circuit.

Japanese Patent Application Laid-Open No. 2008-198775

There is provided a semiconductor nonvolatile memory device capable of adjusting a threshold voltage with high accuracy which enables adjustment of an output voltage without depending on a trimming method by laser processing in order to reduce a circuit characteristic deviation of the semiconductor integrated circuit device and a manufacturing method thereof do.

In order to solve the above-described problems, the present invention has been made as follows.

A high concentration source region and a first high concentration drain region each having a first conductivity type well region formed in the semiconductor substrate and a second conductivity type first high concentration impurity formed in a gap between the semiconductor substrate and the high concentration source region; A first gate insulating film formed between the heavily doped drain region and the semiconductor substrate adjacent to the first heavily doped source region and a second gate insulating film formed on the semiconductor substrate between the heavily doped source region and the first heavily doped drain region and adjacent to the first heavily doped drain region A second heavily doped drain region of a second conductivity type formed in an area overlapping with the first heavily doped drain region and including a region below the second gate insulating film and spaced apart from the heavily doped source region; A region below the first gate insulating film and below the second gate insulating film is included apart from the source region A first lightly doped drain region of a second conductivity type formed in a region overlapping the first heavily doped drain region and the second heavily doped drain region and a second lightly doped drain region formed below the first gate insulating film and between the heavily doped source region and the first heavily doped drain region A floating gate electrode formed of polycrystalline silicon formed on the first gate insulating film and the second gate insulating film and containing a high concentration impurity and a third gate insulating film formed on the floating gate electrode, A control gate electrode formed on the third gate insulating film and made of polycrystalline silicon containing a high concentration impurity; and a well region of the first conductivity type formed in the high concentration source region, the first high concentration drain region, the second high concentration drain region, A lightly doped drain region, and a channel impurity region. Is formed to a position was in the semiconductor nonvolatile memory device.

Further, in order to solve the above-described problems, the present invention is as follows.

A P-type well region forming step of forming a P-type well region made of a P-type impurity on the semiconductor substrate;

An element isolation insulating film forming step of forming a LOCOS oxide film around the P-type well region;

An N-type high-concentration impurity region forming step of forming an N-type high-concentration impurity region made of an N-type impurity,

An N-type low-concentration region forming step of forming a first N-type low-concentration impurity region having a lower N-type impurity concentration than the N-type high-concentration impurity region and diffused deeply;

A channel region forming step of forming an N-type impurity region in the channel formation scheduled region in the P-type well region,

A gate insulating film forming step of forming a second gate insulating film so as to overlap with the N-type high concentration impurity region in the drain formation scheduled region and forming a first gate insulating film thinner than the second gate insulating film in the channel forming region; ,

Forming a polycrystalline silicon layer containing an impurity on the first gate insulating film and the second gate insulating film; forming a third gate insulating film on the polycrystalline silicon; forming, on the third gate insulating film, A gate electrode forming step of forming a silicon layer,

And a source / drain forming step of forming an N-type impurity region in the source forming region and the drain forming region.

According to the present invention, it is possible to provide a semiconductor nonvolatile memory element whose threshold voltage can be adjusted by an external electrical signal, so that the output voltage of the semiconductor integrated circuit device can be adjusted with high precision and further easily.

1 is a process flow chart showing an output voltage adjusting method of the semiconductor integrated circuit device of the present invention.
2 is a process flow chart showing a method of adjusting an output voltage of a conventional semiconductor integrated circuit device.
3 is a schematic diagram of a circuit configuration of a step-down type series regulator by a conventional semiconductor integrated circuit device.
4 is a schematic diagram of a circuit configuration of a voltage detector by a conventional semiconductor integrated circuit device.
5 is an example of a voltage divider circuit combining a conventional resistance element.
6 (1) is a schematic sectional view showing a conventional reference voltage circuit, and (2) is an example of a conventional reference voltage circuit.
7 (1) is a schematic cross-sectional view showing the reference voltage circuit of the present invention, and (2) is an example of the reference voltage circuit of the present invention.
8 is a diagram showing the outline of the circuit configuration of the step-down type series regulator by the semiconductor integrated circuit device of the present invention.
Fig. 9 shows the outline of the circuit configuration of the voltage detector by the semiconductor integrated circuit device of the present invention.
10 is a schematic cross-sectional view of the semiconductor nonvolatile memory device of the first embodiment of the present invention.
11 is a schematic cross-sectional view of a semiconductor nonvolatile memory device according to a second embodiment of the present invention.
12 is a schematic cross-sectional view of a semiconductor nonvolatile memory device according to a third embodiment of the present invention.
13 is a schematic cross-sectional view of a semiconductor nonvolatile memory device of a fourth embodiment of the present invention.
14 is a schematic cross-sectional view of a semiconductor nonvolatile memory device of a fifth embodiment of the present invention.
15 is a schematic cross-sectional view of a semiconductor nonvolatile memory device according to a sixth embodiment of the present invention.
16 is a schematic cross-sectional view of a semiconductor nonvolatile memory device of a seventh embodiment of the present invention.
17 is a schematic cross-sectional view of a semiconductor nonvolatile memory device of an eighth embodiment of the present invention.
18 is an equivalent circuit diagram of the gate insulating film capacitance seen from the drain terminal of the present invention.
19 is a view for explaining electrical characteristics when the present invention is applied to a step-down type series regulator.
20 is a cross-sectional view (in order of a process) showing a manufacturing process of the semiconductor nonvolatile memory device of the first embodiment of the present invention.
FIG. 21 is a cross-sectional view of the semiconductor nonvolatile memory device according to the first embodiment of the present invention, which is followed by FIG.
22 is a cross-sectional view showing a manufacturing process of a semiconductor nonvolatile memory device according to a second embodiment of the present invention.
23 is a cross-sectional view showing the manufacturing steps of the third embodiment of the semiconductor nonvolatile memory device of the present invention in the order of steps.
FIG. 24 is a cross-sectional view showing the manufacturing steps of the third embodiment of the semiconductor nonvolatile memory device of the present invention following FIG. 23; FIG.
25 is a cross-sectional view showing the manufacturing steps of the fourth embodiment of the semiconductor nonvolatile memory device of the present invention in the order of steps.
26 is a sectional view of the semiconductor nonvolatile memory device according to the second embodiment of the present invention, showing the steps of manufacturing the first and second gate insulating films.
27 is a cross-sectional view of the semiconductor nonvolatile memory device according to the third embodiment of the present invention, showing the steps of manufacturing the first and second gate insulating films.
28 is a cross-sectional view of a semiconductor nonvolatile memory element according to a fourth embodiment of the present invention, showing the steps of manufacturing the first and second gate insulating films.
29 is a cross-sectional view of a semiconductor nonvolatile memory element according to a fifth embodiment of the present invention, showing the steps of manufacturing the first and second gate insulating films.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, Figs. 8 and 9 show an embodiment in which the present invention is applied to the conventional semiconductor integrated circuit device shown in Figs. 3 and 4. Fig. As shown in Figs. 8 and 9, an adjustment input terminal 112 for inputting an applied voltage and current from the outside to the reference voltage circuit 100 is added. The semiconductor nonvolatile memory element can change the threshold voltage in accordance with the input voltage / current from the outside to the adjustment input terminal 112 by replacing the specific element in the reference voltage circuit with the semiconductor nonvolatile memory element.

Therefore, a method of adjusting the output voltage will be described with reference to Fig.

First, the output voltage of the finished product is directly measured in the semiconductor processing factory (the process of FIG. 1 (1)).

Next, the voltage and current are applied to the semiconductor nonvolatile memory element in the reference voltage circuit through the adjustment input terminal to change the threshold voltage of the semiconductor nonvolatile memory element (step of FIG. 1 (2)). In the semiconductor integrated circuit device having the configuration as shown in Figs. 8 and 9, when the reference voltage value output from the reference voltage circuit changes, the output voltage also changes proportionally according to the expression (1) And the amount of output voltage is proportional.

Thereafter, the output voltage is measured. When the output voltage is outside the tolerance specification specification required for the product, the process returns to the process of FIG. 1 (2) to resume voltage and current application to the semiconductor nonvolatile memory element. At this time, there is a method in which the reference voltage value of the reference voltage circuit is set so that the initial output voltage value is different from the specifications, and the voltage and current are gradually applied to the semiconductor nonvolatile memory element in one direction of + or - This is preferable because it is easy to adjust.

The process of FIG. 1 (2) and the process of FIG. 1 (3) are repeated to finish a series of processes at the time when the output voltage value falls within the specifications. The processes of Figs. 1 (2) and (3) are not actually intermittent but can be carried out by electrical continuous processing. Therefore, when program software is created and automatically controlled, It can be done in a very short time to fit in.

By adopting such a method, it is possible to complete the three-step process, which can not be reverted back to the process of (3) in the conventional process of FIG. 2 (1), by one electrical process, So that the air shortening can be significantly reduced. In addition, since the on-line trimming adjustment is performed while checking the output voltage, it is possible to suppress the occurrence of defects other than the specification, and to improve the yield.

In addition, it is possible to eliminate influence of high temperature (temperature coefficient of resistance, recrystallization) such as on-line trimming by resistive processing using conventional laser, so there is no need to worry about output voltage error and its rebalancing, .

In addition, since this adjustment method is an electrical process that does not correlate the product type (wafer, package), it can be electrically reconfigured through the terminal even if the product form changes and the characteristic changes due to the change. For example, when the output voltage adjusted in the wafer state changes due to the influence of thermal history, resin stress, or the like after the package is mounted and deviates from the specifications, it can be adjusted again in the package state to fit the specifications. It is also possible to further shorten the test frequency and shorten the process by omitting the irradiation in the wafer state.

In addition to the above-mentioned relaxation of the test frequency, since the laser trimming process is not required, the effect of suppressing the device investment of the measuring apparatus and the laser apparatus is also high.

The voltage dividing circuit 103 including the resistance element 102 in Figs. 8 and 9 does not have to be highly accurate, and even if the accuracy is poor, the output voltage value can be adjusted according to the method of the present invention Therefore, it is not necessary to prepare a plurality of uniformized resistive elements and to study the pattern layout thereof, as in the conventional example, and there is no need for a fuse element, so that there is an advantage that reduction in chip size and reduction in layout load can be expected .

Next, a reference voltage circuit for realizing the present invention will be described with reference to Figs. 7 (1) and (2). 7B, the reference voltage circuit has a configuration in which a depression type NMOS transistor 402 and an enhancement type NMOS transistor 401 are connected in series between an adjusting input terminal 406 and a ground terminal 404, A constant current is output from the depression type NMOS transistor 402 as the current cause to output a voltage generated at the drain terminal of the enhancement type NMOS transistor 401 serving as the load element to the reference voltage output terminal 405 as a constant voltage.

Here, as shown in Fig. 7 (1), for the depression type NMOS transistor 402 used in the present invention, a polycrystalline silicon gate electrode is stacked to form a control gate electrode 8 for controlling the voltage of the upper layer, And a floating gate electrode 7 for injecting and accumulating ions.

7 (2), when the voltage of the adjustment input terminal 406 is raised, the voltage between the reference voltage output terminal 405 and the ground terminal 404 is always fixed at a constant value. Therefore, The rising portion is burdened between the adjusting input terminal 406 and the reference voltage output terminal 405. Therefore, the drain-source voltage of the depression type NMOS transistor 402 rises as the voltage applied to the adjustment input terminal 406 rises, and a hole having a charge in the manner described later, here, through the gate insulating film, The floating gate electrode 7 can be injected into the floating gate electrode 7 having a low potential, so that the floating gate electrode can be charged to the positive side. This is equivalent to lowering the threshold voltage of the depression type NMOS transistor when viewed from the control gate electrode side. As a result, the current of the depression type NMOS transistor rises and the potential of the reference voltage output terminal 405 rises accordingly.

When the reference voltage value of the reference voltage circuit rises, the output voltage of the step-down type series regulator of Fig. 8 rises according to the expression (1). That is, by controlling the voltage of the input terminal of the reference voltage circuit, the output voltage of the step-down type series regulator can be arbitrarily changed. In this example, the adjustment input terminal 112 corresponds to the adjustment input terminal 406 in Fig.

In this case, since the threshold voltage of the semiconductor nonvolatile memory element changes in the minus direction due to the voltage adjustment through the adjustment input terminal, the original negative value Vtd is further changed to the minus side according to the expression (2) Vtd | And the reference voltage output from the reference voltage circuit changes in a direction in which the reference voltage is increased. If the output voltage of the step-down type series regulator of the present invention is designed to be lower than the required specification before the adjustment by the adjustment input terminal, the output voltage of the step-down type series regulator is also increased. By adjusting the output voltage by the adjustment input terminal, it is possible to cope with a wide range of output voltage requirement specifications.

In addition, this method can be carried out with high precision only by electrical control, without involving the laser trimming process, in accordance with a predetermined target voltage value.

Specific examples thereof will be described with reference to Fig. In the graphs shown in Figs. 19 (1) and (2), when the value of the horizontal axis indicates the voltage input to the adjustment input terminal 406 of the reference voltage circuit as shown in Fig. 7, Fig. 19 (1) shows the output voltage characteristics before the adjustment by the adjustment input terminal, and Fig. 19 (2) shows the output voltage characteristics after the adjustment.

19 (1), as shown in Fig. 19 (1), up to the point (a) of the voltage at which the reference voltage circuit operates normally, the output voltage rises as the input voltage increases, , The output voltage is stabilized to a constant value up to the input voltage (b) point. Up to this point, there is no change in electrical characteristics with the conventional step-down type series regulator.

 Then, when the input voltage reaches a sufficiently high input voltage (b) that the carrier is injected into the floating gate electrode of the semiconductor nonvolatile memory element, the injection of carriers into the semiconductor nonvolatile memory element is started and at the same time, The threshold voltage of the volatile memory element changes. Therefore, the output voltage begins to increase again depending on the amount of carriers injected. At the point when the desired output voltage (c) point is reached, stopping the application of the further input voltage stops the carrier injection to the semiconductor nonvolatile memory element, and the carrier is stored in the floating gate electrode. The electric characteristics after the above actions are performed are as shown in Fig. 19 (2).

That is, since the threshold voltage of the semiconductor nonvolatile memory element changes in accordance with the amount of carrier injected into the semiconductor nonvolatile memory element, the threshold voltage of the semiconductor nonvolatile memory element changes according to the formula (2) The stabilized output voltage based on the reference voltage circuit constant voltage and the formula (1) is also shifted to the high value of (c). In this output voltage, carrier injection into the semiconductor nonvolatile memory element starts again when a voltage equal to or higher than point (b) is applied to the adjustment input terminal, and the output voltage starts rising again.

It should be noted here that firstly, in order to enable the adjustment of the output voltage as shown in Fig. 19 (1), sufficiently high drain breakdown is performed so that the semiconductor nonvolatile memory element is not destroyed even if the input voltage reaches (c) Voltage is applied to the device.

Secondly, after adjusting the output voltage to a desired value, the maximum value of the input voltage when used as an actual product is set to a voltage sufficiently lower than the point (b) so that the output voltage is not changed by re- . In short, the operating voltage of the semiconductor integrated circuit device using the present invention must be set to a product specification of the point (b) or less. Therefore, a semiconductor nonvolatile memory element having characteristics matching individual product specifications of the semiconductor integrated circuit device is prepared in advance.

Similarly, the reference voltage circuit in the voltage detection circuit of Fig. 4 can also be realized by the same circuit so that the output voltage of each semiconductor integrated circuit device is controlled and set by the voltage control of the adjustment input terminal connected to the reference voltage circuit It is possible.

Further, in the reference voltage circuit, it is needless to say that the present invention can be applied to any circuit as long as it operates based on the above-described combination of the element serving as the current source and the element serving as the load none.

The semiconductor nonvolatile memory element described herein refers to a semiconductor nonvolatile memory element which is formed by implanting a charge into a floating gate electrode by hot carrier injection, injecting a carrier by an FN tunnel current through a gate insulating film, and trapping a carrier at a level existing in the insulating film , And the overall device which can realize the shift of the threshold voltage by the injection of carriers.

Next, the details of the semiconductor nonvolatile memory device used in the present invention will be described.

FIG. 10 shows a cross-sectional view of a semiconductor nonvolatile memory element showing the first embodiment of the present invention. 10 is formed in the P-type well region 5 containing boron having an impurity concentration of about 7 × 10 ¹⁵ / cm 3 to 7 × 10 ¹⁶ / cm 3 formed on the semiconductor substrate 1. An N-type source / drain region 12, an N-type channel impurity region 10 and a gate insulating film 9 (14, 14) are formed in a region surrounded by a gate insulating film And 15 and the gate electrodes 7 and 8 constitute a depression type NMOS transistor.

The gate electrode is formed in a laminated structure of a floating gate electrode 7 made of polycrystalline silicon and a control gate electrode 8. The control gate electrode is connected to the source terminal of this depression type NMOS transistor And the floating gate electrode is surrounded by the first gate insulating film 9, the second gate insulating film 14 and the third gate insulating film 15 and is in a state of not having an electrical connection.

A carrier such as an electron or a hole is injected into the floating gate electrode 7 through the second gate insulating film 14 from the drain terminal. When a positive or negative carrier is injected into the floating gate electrode 7, the threshold voltage of the depression type NMOS transistor is set to be equal to the fixed charge existing between the gate electrode and the channel region in the normal MOSFET Change.

The injected carrier is kept under conditions that do not escape due to heat or electric stress during normal operation, so that the threshold voltage of the depression type NMOS transistor can be adjusted and maintained at a desired value.

The threshold voltage in a state in which carriers are not injected into the floating gate electrode 7 is set to a negative arbitrary value in accordance with the amount of impurities in the N-type channel impurity region 10, so that the depletion type NMOS transistor Even if the voltage between the gate and the source is 0 V, the voltage is applied between the drain and the source so that the current flows into the normally-on state.

The N-type source / drain region 12 functions as a source / drain terminal by injecting an N-type impurity such as As or P of 1 x 10 ²⁰ / cm 3 or more to reduce the resistance. The drain terminal side further includes a channel impurity region An N-type high-concentration impurity region 17 containing N-type impurity of 5 × 10 ¹⁸ / cm 3 or more and an N-type impurity region 17 of 1 × 10 ¹⁷ / cm 3 to 1 × 10 ¹⁸ / And a first N-type low-concentration region 18 made of N-type impurity.

The first N-type lightly doped region 18 serves to mitigate the electric field caused by elongation of the drain side depletion layer upon application of a drain voltage and to increase the voltage of the N-type lightly doped region 17, And is used as a lower electrode when carriers are injected into the floating gate electrode 7.

The first reason why the impurity concentration of the N-type high-concentration impurity region 17 is 5 × 10 ¹⁸ / cm 3 or more is that when the hole is injected into the floating gate electrode as a carrier, the N-type high-concentration impurity The surface of the region is depleted and the electric field between the floating gate electrode and the N-type high concentration impurity region is relaxed to prevent the implantation efficiency from being lowered.

The second reason is that when the high voltage is applied to the N-type high-concentration impurity region to inject holes as carriers into the floating gate electrode, the elongation of the drain-to-well depletion layer diffused from the N-type low- Thereby preventing the lowering of the injection efficiency of the carrier.

The N-type high-concentration impurity region 17 and the floating gate electrode 7 have the overlapping portion 16 and the second gate insulating film 14 existing in the overlapping portion has the N-type channel impurity region 10, The gate insulating film 9 has a thickness different from that of the gate insulating film 9. [ Generally, the gate insulating film is set to a predetermined thickness from the viewpoint of long-term reliability in accordance with the operating voltage of the semiconductor integrated circuit device including the MOSFET. The second gate insulating film 14 in this semiconductor nonvolatile memory element is determined to be a condition suitable for injecting a carrier into the floating gate electrode and in order to avoid the escape of charges within the operating voltage range, A thickness larger than the thickness determined by the long-term reliability in voltage is adopted.

Therefore, in the present embodiment, the second gate insulating film 14 is thicker than the gate insulating film 9 on the N-type channel impurity region 10.

A separate feature of the semiconductor nonvolatile memory device of the present invention is specialized for analogical adjustment of the characteristics of the semiconductor nonvolatile memory device and the semiconductor integrated circuit device including the semiconductor nonvolatile memory device and is intended to replace some conventional devices . Therefore, it is not assumed that a memory array is configured for information accumulation, and a structure such as a select gate for specifying an address required in the memory array configuration is not required.

Next, details of the electric operation of the present invention will be described.

For example, the potential of the floating gate electrode 7 changes to a minus potential when an electron having a negative charge is injected. In this case, a positive charge is induced in the channel region in response to this negative charge, or electrons in the N-type channel impurity region 10 decrease, and the threshold voltage of the N-channel MOSFET changes to the positive side.

On the other hand, when a hole having a positive charge is injected into the floating gate electrode 7, the potential of the floating gate electrode is shifted to the positive side, and the electron density of the N-type channel impurity region 10 changes to a state of becoming more energized, As a result, the threshold voltage of the N-channel type MOSFET changes to the minus side.

Since the structure of the present invention is a depression type NMOS transistor in which the threshold voltage takes a negative value in a state in which carriers are not injected due to the presence of the N type channel impurity 10, And a hole is injected as a carrier from the side of the N-type high concentration impurity region 17 so that the negative threshold voltage is changed in a minus direction and the threshold voltage is controlled with high accuracy.

A typical semiconductor nonvolatile memory device is controlled by a binary value (e.g., a threshold voltage greater than 0 V and a threshold voltage less than 0 V). And is used to digitally hold necessary information by combining a plurality of the elements. The present invention differs from conventional methods in that only one element is used to determine and maintain information analogously to the amount of carriers in the plot.

In the present invention, by taking advantage of this threshold voltage changing function and the nonvolatile characteristic, carriers are injected into the semiconductor nonvolatile memory element before shipment to the customer to adjust the threshold voltage of the semiconductor nonvolatile memory element, The circuit characteristics of the semiconductor integrated circuit device including the device are adjusted to a desired value. Thereafter, thereafter, the customer does not insert and remove the carrier during the use operation, and a high reliability for repeated rewriting is required for the second gate insulating film Do not.

In the present invention, the carrier is injected into the floating gate electrode as follows. First, in the state where the carrier is not implanted, the impurity amount of the N-type channel impurity region 10 is set so that the threshold voltage is a negative value but becomes higher (positive side) than the original target value.

Next, in the test step of the semiconductor integrated circuit device after the semiconductor manufacturing process, the source potential and the control gate electrode potential are made common low and the drain potential is changed to the positive side high potential. In this state, the floating gate potential is set such that the film thickness of the first gate insulating film 9, the second gate insulating film 14, and the third gate insulating film 15 and the capacitance ratio determined by the control gate electrode and the floating gate electrode size Is set to a value intermediate between the drain potential, the source potential, and the control gate electrode potential. By adjusting the size and the film thickness, a low value close to the source potential and the control gate electrode potential is set so that the second gate insulating film 14 ) Is designed to apply most of the voltage between the drain and the source.

In the present depression type NMOS transistor, even if the potential of the control gate electrode 8 is 0 V, since the threshold voltage is a negative value, the drain current flows in accordance with the rise of the drain potential, but the current characteristic is switched from the non- And stabilized at a constant saturation current value independent of the drain potential. Since the potential of the depletion layer end generated at the drain side in the N-type channel impurity region 10 is fixed to a low constant (pinch-off voltage) determined by the gate-source voltage and the threshold voltage, / Voltage between the source and the pinch-off voltage is applied to the depletion layer generated in the first N-type low-concentration impurity region. Since the impurity concentration of the depletion layer n does not reach the sufficiently high concentration N-type high-concentration impurity region 17, the potential of the N-type high-concentration impurity region 17 is set such that the drain potential applied to the drain terminal 2 is intact So that it is easy to control the potential difference between the N-type high concentration impurity region 17 and the control gate electrode 8.

At this time, the amount of diffusion of the depletion layer generated in the N-type low-concentration impurity region can be controlled by arbitrarily setting the impurity concentration and the planar length of the first N-type low-concentration impurity region 18, The upper limit of the drain voltage can be increased. As a result, the potential applied to the N-type high concentration impurity region 17 can be set to a high value, so that even if the second gate insulating film is set thick, a potential for carrier injection can be ensured.

For example, the impurity concentration of the first N-type lightly doped region 18 is set to be within the range of 1 × 10 ¹⁷ / cm 3 to 1 × 10 ¹⁸ / cm 3, and the impurity concentration in the plane direction from the channel region to the N-type high concentration impurity region 17 The drain withstand voltage can be set to 20 V or more, and a carrier injection voltage of 20 V or more can be ensured.

For example, when the thickness of the second gate insulating film 14 is set to 400 ANGSTROM, the tunneling phenomenon can be generated with an applied voltage of about 20 V or more. Therefore, in the above drain structure, Hole injection of a positive charge based on the tunneling phenomenon is realized in the overlapping portion 16 of the N-type high concentration impurity region 17 and the floating gate electrode 7. [ On the other hand, since the N-type channel impurity region 10 is below the pinch-off voltage described above, if only the thickness of the insulating film corresponding to the pinch-off voltage is secured, the N-type channel impurity region 10 and the floating gate electrode 7 The tunneling phenomenon does not occur in the first gate insulating film 9 between the source and drain regions.

It is preferable that the drain voltage applied in the test step is performed at a voltage sufficiently higher than the operating voltage of the semiconductor integrated circuit device including the present semiconductor nonvolatile memory device. This prevents the carrier from being injected into the floating gate electrode during the fluctuation of the power supply voltage within the operating voltage of the semiconductor integrated circuit device and prevents fluctuations in the threshold voltage of the semiconductor nonvolatile memory element and the fluctuation of the circuit characteristics of the semiconductor integrated circuit device The change can be suppressed. For example, in the above example, the operating voltage of the semiconductor integrated circuit device is preferably 10 V or less. In order to set a sufficient potential difference (20 V - 10 V = 10 V in this example) between the operating voltage and the carrier injection voltage, the thickness of the second gate insulating film 14 and the thickness of the first N-type low concentration impurity region 18 It is necessary to set the condition.

The amount of carriers to be accumulated in the floating gate electrode can be determined by a method of gradually increasing the drain voltage as shown in Fig. 19, but the amount of hole charge accumulated in the floating gate electrode 7 is determined by the drain voltage value and its application time Can be controlled by the product of As described above, since the threshold voltage of the present depression type NMOS transistor is further shifted to the negative side according to the accumulated amount of the hole charges, a high constant drain voltage is applied until the desired threshold voltage is reached, It is also possible to adjust the threshold voltage of the N-channel type MOSFET with high precision in time.

11 is a cross-sectional view of a semiconductor nonvolatile memory element showing a second embodiment of the present invention. 11, in addition to the structure of FIG. 10, a second N-type low-concentration impurity region 19 made of As or P having an impurity concentration of about 2 × 10 ¹⁶ / cm 3 to 2 × 10 ¹⁷ / Is added under the impurity region (18). 10, it is easy to set the drain breakdown voltage to about 30 V at a high breakdown voltage, depending on the conditions of the N-type low-concentration impurity region 18.

However, in the depletion layer of the first N-type low-concentration impurity region 18 and the underlying P-type well region 5, the depletion layer is restricted to the first N-type low-concentration impurity region side, It is difficult to increase the pressure. Therefore, the drain breakdown voltage exceeding 30 V can be obtained by securing the extension of the depletion layer corresponding to the diffusion depth by adding the second N-type impurity region 19 as shown in FIG. This is effective in coping with a semiconductor integrated circuit device having a higher operating voltage and securing a larger margin of the operating voltage and the tunneling voltage.

12 is a cross-sectional view of a semiconductor nonvolatile memory element showing a third embodiment of the present invention. 12, an oxide film thicker than the first gate insulating film 9 and the second gate insulating film 14 is formed between the floating gate electrode 7 and the first N-type low concentration impurity region 18. [ By adopting such a configuration, it is possible to relax the high voltage between the floating gate electrode 7 of low potential and the first N-type low concentration impurity region 18, which is generated when the drain voltage is raised, It is possible to increase the internal pressure.

The thickness of the thick oxide film 13 may be set to an arbitrary thickness according to the degree of relaxation of the required electric field. In the case where the thick oxide film 13 can withstand a drain voltage exceeding 30 V, a thickness of 1000 A or more is preferable. In addition, by forming the LOCOS oxide film at the same time as the LOCOS oxide film in the device isolation region, an increase in the process can be avoided.

13 is a cross-sectional view of a semiconductor nonvolatile memory element according to a fourth embodiment of the present invention. 13, the second N-type low-concentration impurity region 19 in FIG. 12 is extended to the side of the source terminal 3 to the extent that it overlaps with the N-type channel impurity region 10. In addition, a P-type low-concentration impurity region 20 having a higher impurity concentration than the second N-type low-concentration impurity region 19 is formed so as to surround the source terminal.

This P-type low concentration impurity region 20 has an impurity concentration of about 2 × 10 ¹⁶ / cm 3 to about 2 × 10 ¹⁷ / cm 3 in the region not exceeding the thick oxide film 13 in the vicinity of the first gate insulating film, Is formed at a concentration higher than the concentration of the second N-type low-concentration impurity region (19). As described above, since the concentration of the P-type low-concentration impurity region 20 is higher than that of the second N-type low-concentration impurity region 19, the depletion layer on the channel side and the drain side, which occurs when the drain voltage is increased, This is effective when it is necessary to obtain a drain breakdown voltage of 60 V or more.

In the first to fourth embodiments so far, as shown in Figs. 10 to 13, the floating gate electrode and the control gate electrode are laminated by using the polycrystalline silicon layer. However, the two- Such a method used is easy to reduce the cost by suppressing an increase in the area of the gate electrode, but the process is increased and processing is complicated. For example, the complexity is determined by selecting the dry etching conditions for collectively processing the floating gate electrode 7, the control electrode 8, and the third gate oxide film 15 therebetween, and the etching resistance , Polycrystalline silicon stringers generated in the stepped portion, and deterioration of flatness due to the gate electrode structure of a high aspect ratio.

14 to 17 show a method for realizing the semiconductor nonvolatile memory element using only one layer of the polycrystalline silicon layer in order to overcome such complexity, and have a structure corresponding to each of the structures in FIGS. 10 to 13.

First, Fig. 14 shows a fifth embodiment in which the two-layer gate electrode structure of polycrystalline silicon shown in Fig. 10 is a single layer.

14 (2) and (3) are sectional views corresponding to the portions AA 'and BB' in the plan view 14 (1), and the two-layered laminated polycrystalline silicon structure of FIG. 10 is referred to as one layer of the floating gate electrode 7 . The control electrode and the third gate insulating film are not formed on the floating gate electrode 7 as shown in Fig. 14 (2). Instead, this floating gate electrode 7 is extended outside the channel region as shown in Fig. 14 (1), and overlaps with the control gate electrode 8 using the impurity diffusion region in the semiconductor substrate. The control gate electrode 8 using the impurity diffusion region in the semiconductor substrate has the potential extraction portion 6. The control gate electrode 8 may be used in combination with the impurity in the N-type high concentration impurity region 17, for example, and the extraction portion 6 may also be used as the N-type high concentration impurity in the source / drain region.

The third gate insulating film 15 between the floating gate electrode and the control electrode used in FIG. 10 is composed of an oxide film on the surface of the semiconductor substrate formed between the floating gate electrode and the control gate electrode, which is an impurity diffusion region in the semiconductor substrate An oxide film formed at the same time as the first gate insulating film formed outside the channel region is used.

In the configuration shown in Fig. 14, two occupation areas of the control gate electrode and the floating gate electrode are required in the semiconductor integrated circuit device, which leads to an increase in the chip occupied area and an increase in cost. However, since the present invention is not used in applications such as a memory array in which a large number of semiconductor nonvolatile memories are aligned in a semiconductor integrated circuit device, the occupied area is not increased so much, It does not matter. On the other hand, as described above, there is an advantage that the quality can be stabilized and the process can be reduced by eliminating the complexity and difficulty of the process.

In the structure of Fig. 14, when a circuit is used in which the gate potential, the source potential, and the voltage of the p-type well region are connected to each other through a metal wiring, The impurity of the electrode 8 may be a P-type high-concentration impurity, or may remain the P-type well region 5.

This is because the semiconductor nonvolatile memory device of the present invention has a normally-on type in which the current flows in accordance with the drain voltage even when the gate-source voltage is 0 V due to the presence of the N-type channel impurity region 10. This is because, if the P-type well region is connected to the source terminal and the metal wiring or the like, which is not shown in the drawing, the impurity diffusion that becomes the control gate electrode 8 becomes the same potential relation even if it is P-type.

Fig. 15 shows a sixth embodiment in which the two-layer gate electrode structure of polycrystalline silicon of Fig. 11 is a single layer, and the effect is the same as that described in Fig. 15 (2) and (3) are cross-sectional views corresponding to portions A-A 'and B-B' in a plan view 15 (1).

Fig. 16 shows a seventh embodiment in which the two-layer gate electrode structure of polycrystalline silicon shown in Fig. 12 is a single layer, and the effect is the same as that described in Fig. 16 (2) and (3) are cross-sectional views corresponding to portions A-A 'and B-B' in a plan view 16 (1).

Fig. 17 shows an eighth embodiment in which the two-layer gate electrode structure of polycrystalline silicon shown in Fig. 13 is one layer, and the effect is the same as that described in Fig. 17 (2) and (3) are cross-sectional views corresponding to portions A-A 'and B-B' in a plan view 17 (1).

Next, three types of gate insulating films used in the present invention will be described.

First, as the second gate insulating film used for injecting carriers into the floating gate electrode by the tunneling phenomenon in the invention, a silicon oxide film by a thermal oxidation method having high film thickness controllability and film stability is preferable. Further, since the carriers are only injected into the floating gate once or several times in the test step after the end of the semiconductor manufacturing process, there is no need for special film forming conditions or additional processing for obtaining strong resistance to the number of times of rewriting. On the other hand, the film thickness of the second gate insulating film is set to be thicker enough to obtain a desired tunnel current value for a drain voltage sufficiently higher than the operation voltage applied to the semiconductor integrated circuit device in the test step after the end of the semiconductor manufacturing process Setting.

On the other hand, it is preferable that the first gate insulating film 9 and the third gate insulating film 15 have high capacitance values. In order to sufficiently lower the potential of the floating gate electrode determined by the capacitive coupling in order to efficiently apply a voltage to the second gate insulating film in injecting holes into the floating gate electrode by applying a drain voltage in a test process to be.

The equivalent capacitance coupling circuit between the drain terminal 2 for applying the high potential and the control gate electrode 8 for setting the low potential, the P-type well region and the body terminal 4 which is the same potential as the P- 18. As can be seen, the first gate insulating film and the third gate insulating film are formed in a large capacity to increase the ratio of the insulating film thickness to the second gate insulating film capacity, The high potential can be applied to the second insulating film 14 between the drain terminal 2 and the floating gate electrode 7 and the tunneling phenomenon can be promoted.

For this reason, it is required that the first and third gate insulating films have a large electrode size in a plane. This is because it is possible to increase the capacity value, but it is sufficient that the area is at least 10 times as large as the plane size of the second gate insulating film.

Further, for the purpose of increasing the capacitance value, the first and third gate insulating films are preferably as thin as possible. Since the potentials of the floating gate electrode, the control gate electrode, and the P-type well region are fixed at the same low potential by the circuit, the restriction of the insulating film thickness by the operation voltage of the semiconductor integrated circuit device does not function. Therefore, in the case of a thermal oxide film, considering the leakage due to the high-temperature environment of the carrier in the floating electrode, a film thickness of about 100 to 200 ANGSTROM is preferable.

From the viewpoint of the high capacity, it is preferable that the relative dielectric constant of the first and third gate insulating films is high and can be realized by using SiON, SiN, or HfO ₂ rather than the silicon thermal oxide film. In general, a film other than the silicon thermal oxide film has a characteristic variation such as a threshold voltage due to instability of the film interface. In the present invention, even if there is a characteristic deviation, the film can finally be adjusted by adjustment in the test step It does not matter.

The adoption of the thin film of the first and third gate insulating films and the high dielectric constant film has the merit that the gate electrode size can be reduced and the cost can be reduced. Since this method leads to increasing the capacitance value C per unit area in the general formula (3), it is possible to reduce the amount of fluctuation in the threshold voltage with respect to the decrease in Q due to leakage of carriers in the floating gate electrode It also has merit.

        V = Q / C (3)

As described above, by employing the semiconductor nonvolatile memory device of the present invention, it is possible to easily adjust the threshold voltage, to achieve long-term stability, and to absorb the circuit characteristic variation based on the device characteristic variation by electrical adjustment in the test process. A semiconductor integrated circuit device of the present invention can be provided.

Next, a manufacturing method for manufacturing the semiconductor nonvolatile memory device of the structure of the first embodiment of FIG. 10 is described based on the process flow charts of FIGS. 20 (1) to (4) and 21 (5) to .

First, a P-type or N-type semiconductor substrate 1 is prepared, P-type impurity of B or BF2 is implanted into the region for forming a semiconductor nonvolatile memory element by ion implantation method, 5) are formed (1).

The polarity of the semiconductor substrate 1 is selected in accordance with the demand of the semiconductor integrated circuit device having the semiconductor nonvolatile memory device of the present invention. That is, when it is desired to electrically isolate the P-type well region from the lowest potential on the semiconductor integrated circuit device, it is preferable to prepare an N-type semiconductor substrate, but the P- When the well region is the lowest potential on the semiconductor integrated circuit device, a more inexpensive P-type semiconductor substrate can be used.

An impurity implantation amount and a thermal diffusion condition are selected so that the impurity concentration of the P-type well region 5 is a value between 7 × 10 ¹⁵ / cm 3 and 7 × 10 ¹⁶ / cm 3 and a depth of 6 μm to 10 μm. More specifically, the impurity implantation area density is 1 × 10 ¹² / cm 2 to 1 × 10 ¹³ / cm 2, and thermal diffusion is performed at a temperature of 1100 ° C. to 1200 ° C. for several hours to several tens of hours.

Next, a device isolation region 13 made of a silicon oxide film is formed around the P-type well region 5 using a LOCOS method or the like so as to electrically isolate the devices from each other, and a semiconductor And defines a nonvolatile memory element region (2).

Next, N-type impurity such as As or P is implanted into the region to be a drain region of the present semiconductor nonvolatile memory element by ion implantation to form an N-type high concentration impurity region 17 and a first N-type low concentration impurity region 18 (3).

The N-type high concentration impurity region 17 serves as a lower electrode for later tunneling the carriers such as electrons and holes through the silicon oxide film to the upper floating gate electrode. The high voltage at the positive side is applied In order to suppress the depletion of the surface of the N-type high-concentration impurity region, it is preferable to implant As with an impurity concentration of 5 x 10 ¹⁸ / cm 3 or more. It is preferable that the implantation energy at this time is such that it can pass through the oxide film on the surface of the semiconductor substrate and is set to, for example, about 100 keV.

The first n-type low concentration impurity region 18 is preferably formed by implanting P at an impurity concentration of 1 x 10 ¹⁷ / cm 3 or more and 1 x 10 ¹⁸ / cm 3 or less in order to obtain a drain breakdown voltage of a desired value or more Do. By setting the implantation energy to 90 keV or more, deep diffusion can be made deeper than the N-type high concentration impurity region 17, and the PN junction with the P-type well region 5 below the N-type high concentration impurity region 17 The internal pressure can be set high.

Next, in order to make the present semiconductor nonvolatile memory element a depression type MOSFET of a normally-on type, N type impurity of As or P is implanted into a region where a channel is to be formed by ion implantation so that the threshold voltage becomes a negative desired value, Thereby forming an N-type channel impurity region 10 (4).

Next, by a thermal oxidation method, a CVD method, or the like, a first gate insulating film 9 having a film thickness of about 100 to 200 angstroms is formed in the channel forming region and a second gate insulating film 9 having a thicker film thickness than the first gate insulating film A second gate insulating film 14 of about 100 angstroms is formed (5).

In order to form the gate insulating film of two film thicknesses, first, the second thick gate insulating film is formed as the silicon oxide film by the thermal oxidation method on the entire surface of the device region, and then the second gate insulating film Etching is performed by a photolithography technique and HF or the like, and then the first gate insulating film is formed as a silicon oxide film by a thermal oxidation method.

In this method, the second gate insulating film is exposed to the thermal oxidation treatment at the time of forming the first gate insulating film, and the silicon oxide film constituting the second gate insulating film is re-grown. However, since the second gate insulating film already has a thick film thickness, the speed at which oxygen reaches silicon reaches a slow speed during the thermal oxidation treatment at the time of forming the first gate insulating film, which is a thin gate insulating film, little. Therefore, the film thickness of the second gate insulating film after the second thermal oxidation treatment is dominated by the first thermal oxidation process, and the film thickness is also easily predicted.

Next, a polycrystalline silicon layer is deposited on the first and second gate insulating films, and impurity implantation at a high concentration is performed by ion implantation or thermal diffusion so as to have a concentration of 1 x 10 ¹⁹ / cm 3 or more. Then, photolithography and dry etching Thereby forming the floating gate electrode 7 of the semiconductor nonvolatile memory element. At this time, the floating gate electrode 7 and the second gate insulating film are overlapped to perform carrier injection by tunneling (6).

Next, an insulating film is deposited on the floating gate electrode of the semiconductor nonvolatile memory element by a thermal oxidation method, a CVD method or the like so as to form the third gate insulating film 15. Thereafter, a polycrystalline silicon layer is deposited, and impurity implantation at a high concentration is performed by ion implantation or thermal diffusion so as to have a concentration of 1 x 10 ¹⁹ / cm 3 or more. The control gate electrode 8 is formed by photolithography and dry etching, (7).

At this time, the floating gate electrode and the control gate electrode may be collectively formed by one photolithography process and a dry etching process. That is, a polycrystalline silicon layer is deposited on the first and second gate insulating films, and impurity implantation at a high concentration is performed by ion implantation or thermal diffusion so that the concentration is 1 × 10 ¹⁹ / cm 3 or more. The polycrystalline silicon layer is deposited again by the oxidation method or the CVD method and then the polycrystalline silicon layer is deposited again to carry out impurity implantation at a high concentration of 1 x 10 ¹⁹ / cm 3 or more by ion implantation or thermal diffusion, The control gate electrode 8 and the floating gate electrode 7 are formed by collective patterning using an etching process.

Next, in order to form the source / drain region 12 of the semiconductor nonvolatile memory device, the N type impurity of As or P is implanted by an ion implantation method so as to be not less than 1 x 10 ²⁰ / cm 3 (8).

This is the description based on the process flow charts of Figs. 20 (1) to (4) and Figs. 21 (5) to (8).

Next, although not shown, an insulating film made of an oxide film is deposited as a whole, and a contact hole is formed at a predetermined position. Thereafter, in order to impart the potential of the gate, source, drain and body of the semiconductor nonvolatile memory element, Is formed by sputtering and patterning of a metal film.

In order to manufacture the structure shown in the fifth embodiment in which the two-layered gate electrode structure of polycrystalline silicon shown in Fig. 14 is one layer as shown in Fig. 14, in the above manufacturing method, And the step of forming the floating gate electrode 7 on the second gate insulating film. Thereafter, the source / drain regions 12 of the semiconductor nonvolatile memory element are formed and can be manufactured in the same manner. The control gate electrode 8 can be fabricated by combining the structure and the process with, for example, impurities in the N-type high concentration impurity region 17.

Next, a manufacturing method for manufacturing the semiconductor nonvolatile memory device of the structure of the second embodiment of FIG. 11 will be described based on the process flow charts of FIGS. 22 (1) to (4). The difference between the second embodiment and the first embodiment is the addition of the second N-type low-concentration impurity region 19 in FIG. 11, so that the second step is simplified according to FIG.

First, a P-type or N-type semiconductor substrate 1 is prepared, and a P-type well region 5 and a second N-type low-concentration impurity region 19 are formed in the region for forming the semiconductor non- (1).

This P-type well region 5 is formed by implanting P-type impurity of B or BF2 at an impurity concentration of 7 × 10 ¹⁵ / cm 3 to 7 × 10 ¹⁶ / cm 3 at an impurity implantation amount of 6 μm to 10 μm, Select the conditions of diffusion. More specifically, the impurity implantation area density is 1 × 10 ¹² / cm 2 to 1 × 10 ¹³ / cm 2, and thermal diffusion is performed at a temperature of 1100 ° C. to 1200 ° C. for several hours to several tens of hours.

The N-type low-concentration impurity region 19 is formed by implanting impurity and heat so that the N-type impurity of P or As has a depth of 3 탆 to 6 탆 at an impurity concentration of 2 × 10 ¹⁶ / cm 2 to 2 × 10 ¹⁷ / Select the diffusion condition. This thermal diffusion may be used in combination with the heat treatment at the time of forming the P-type well region, or may be performed after that.

Next, although not shown, a device isolation region 13 made of a silicon oxide film is formed by LOCOS or the like in order to electrically isolate the devices, and a semiconductor nonvolatile memory device region .

Next, N-type impurity such as As or P is implanted into the region to be the drain region of the present semiconductor nonvolatile memory element by ion implantation to form the N-type high concentration impurity region 17 and the first N-type low concentration impurity region 18 (2).

The N-type high-concentration impurity region 17 is preferably formed by implanting As at an impurity concentration of 5 10 ¹⁸ / cm 3 or more, and the implantation energy is preferably about 100 keV which can pass through the oxide film on the surface of the semiconductor substrate .

The first n-type low concentration impurity region 18 is preferably formed by implanting P at an impurity concentration of 1 x 10 ¹⁷ / cm 3 to 1 x 10 ¹⁸ / cm 3. By setting the implantation energy to 90 keV or more, deep diffusion can be made deeper than the N-type high concentration impurity region 17, and the PN junction with the P-type well region 5 under the N-type high concentration impurity region 17 Can be set high.

Then, the formation of the N-type channel impurity region described earlier in FIG. 20 (4) and the formation of the first gate insulating film and the second gate insulating film described in FIG. 21 (5) are performed.

22, a polycrystalline silicon layer is deposited on the first and second gate insulating films, and impurity implantation at a high concentration is performed by ion implantation or thermal diffusion so as to be 1 x 10 ¹⁹ / cm 3 or more, Lithography and dry etching are performed to form the floating gate electrode 7 of the semiconductor nonvolatile memory element (3).

Next, the third gate insulating film and the floating gate electrode described in Fig. 21 (7) are formed.

Next, in order to form a source / drain region of the semiconductor nonvolatile memory element, an N-type impurity of As or P is implanted by an ion implantation method so as to be not less than 1 x 10 ²⁰ / cm 3 (4).

Next, although not shown, an insulating film made of an oxide film is deposited as a whole, and a contact hole is formed at a predetermined position. Thereafter, in order to impart the potential of the gate, source, drain and body of the semiconductor nonvolatile memory element, Is formed by sputtering and patterning of a metal film.

Further, in order to manufacture the structure shown in the sixth embodiment in which the two-layered gate electrode structure of polycrystalline silicon shown in Fig. 15 is one layer as shown in Fig. 11, in the above manufacturing method, And the step of forming the floating gate electrode 7 on the second gate insulating film. Thereafter, the source / drain regions 12 of the semiconductor nonvolatile memory element are formed and can be manufactured in the same manner. The control gate electrode 8 can be fabricated by combining the structure and the process with, for example, impurities in the N-type high concentration impurity region 17.

Next, a manufacturing method for manufacturing the semiconductor nonvolatile memory device of the structure of the third embodiment of Fig. 12 is described based on the process flow charts of Figs. 23 (1) to (4) and 24 (5) to .

First, a P-type or N-type semiconductor substrate 1 is prepared, a P-type well region 5 is formed in the region where the semiconductor nonvolatile memory element is formed, and a second N-type low concentration impurity region 19 is formed in the P- And a first N-type low-concentration impurity region 18 are formed. The P-type well region 5 and the second N-type low-concentration impurity region 19 are formed by the method described in the manufacturing method of the second embodiment. The first N-type low-concentration impurity region 18 is formed of As or P And the N-type impurity is adjusted so as to have an impurity concentration of 1 × 10 ¹⁷ / cm 3 to 1 × 10 ¹⁸ / cm 3. The position is formed in advance so as to cover a thick oxide film formed later in the vicinity of the N-type channel impurity region (1).

Next, an element isolation region 13 for electrically isolating the elements from each other by the LOCOS method is formed, and then a thick oxide film is formed on the first N-type low concentration impurity region 18. Next, The thick oxide film on the first N-type low-concentration impurity region 18 preferably has a thickness of 1000 ANGSTROM or more. However, as described with reference to FIG. 12, a method of forming the LOCOS oxide film 13 in the element isolation region at the same time, It may be taken (2).

Next, N-type impurity of As or P is implanted into the region to be a drain region of the present semiconductor nonvolatile memory element by ion implantation to form an N-type high concentration impurity region 17. Next, in order to form the semiconductor nonvolatile memory element into a normally-on type depression type MOSFET, an As or P N type impurity is implanted into a channel forming region by an ion implantation method to form an N type channel impurity region 10 (3).

Next, a second gate insulating film 14, which is thicker than the first gate insulating film and is in contact with the LOCOS oxide film formed earlier, is formed in a part of the drain formation scheduled region by the thermal oxidation method, the CVD method, or the like, and the N type high concentration impurity region ( 17), and then the first gate insulating film 9 is formed on the channel formation scheduled region. In order to divide the gate insulating film of two film thicknesses, as shown in FIG. 21 (5), after forming the thick second gate insulating film first, the second gate insulating film in the region other than the region to be formed with drain is photolithographically By etching and etching with HF or the like, and then forming a first gate insulating film (4).

Next, a polycrystalline silicon layer is deposited on the first and second gate insulating films, and impurity implantation at a high concentration is performed by an ion implantation method or a thermal diffusion method so as to have a concentration of 1 x 10 ¹⁹ / cm 3 or more and photolithography and dry etching treatment Thereby forming the floating gate electrode 7 of the semiconductor nonvolatile memory element. At this time, the floating gate electrode 7 and the second gate insulating film 14 are overlapped to perform carrier injection by tunneling (5).

Next, although not shown, the third gate insulating film 15 and the control gate electrode 8 are formed in the same manner as described in Fig. 21 (7).

Then, in order to form the source / drain regions of the semiconductor nonvolatile memory device, the N-type impurity of As or P is implanted by an ion implantation method so as to be not less than 1 × 10 ²⁰ / cm 3 (6).

This is the description based on the process flow charts of FIGS. 23 (1) to (4) and 24 (5) to (6).

Next, although not shown, an insulating film made of an oxide film is deposited as a whole, and a contact hole is formed at a predetermined position. Thereafter, in order to impart the potential of the gate, source, drain and body of the semiconductor nonvolatile memory element, Is formed by sputtering and patterning of a metal film.

Further, in order to manufacture the structure shown in the seventh embodiment in which the two-layer gate electrode structure of polycrystalline silicon shown in Fig. 16 is one layer as shown in Fig. 16, in the above manufacturing method, And the step of forming the floating gate electrode 7 on the second gate insulating film. Thereafter, the source / drain regions 12 of the semiconductor nonvolatile memory element are formed and can be manufactured in the same manner. The control gate electrode 8 can be fabricated by combining the structure and the process with, for example, impurities in the N-type high concentration impurity region 17.

Next, a manufacturing method for manufacturing the semiconductor nonvolatile memory device of the structure of the fourth embodiment of FIG. 13 will be described with reference to the process flow charts of FIGS. 25 (1) to (4).

First, a P-type or N-type semiconductor substrate 1 is prepared, and a part of the P-type low-concentration impurity region 20 and the second N-type low-concentration impurity region 19 are overlapped with each other in the region where the semiconductor non- . The N-type lightly doped impurity region 19 is formed by implanting impurities such that the impurity concentration is between 2 × 10 ¹⁶ / cm 3 and 2 × 10 ¹⁷ / cm 3 and the depth is from 3 μm to 6 μm by using N type impurities of P or As. The heat diffusion condition is selected and the P-type low concentration impurity region 20 is formed so that B or BF2 is doped into the N-type low concentration impurity region ^{22 at} an impurity concentration of about 2 x 10 ¹⁶ / cm 3 to 2 x 10 ¹⁷ / (19), thereby improving the drain withstand voltage (1).

Next, though not shown, the first N-type low concentration impurity region 18 is formed in the region to be subjected to the subsequent drain formation by using an N-type impurity such as As or P in the range of 1 x 10 ¹⁷ / cm 3 to 1 x 10 ¹⁸ / So as to have the impurity concentration.

Next, an element isolation region 13 for electrically isolating the elements from each other by the LOCOS method is formed, and then a thick oxide film is formed on the first N-type low concentration impurity region 18. Next, The thick oxide film on the first N-type low-concentration impurity region 18 preferably has a thickness of 1000 ANGSTROM or more. However, as described with reference to FIG. 12, a method of forming the LOCOS oxide film 13 in the element isolation region at the same time, It may be taken (2).

Next, although not shown, the N-type channel impurity region 10 is formed and the first and second gate insulating films 9 and 14 are formed.

Next, a polycrystalline silicon layer is deposited on the first and second gate insulating films, and impurity implantation at a high concentration is performed by an ion implantation method or a thermal diffusion method so as to have a concentration of 1 x 10 ¹⁹ / cm 3 or more and photolithography and dry etching treatment Thereby forming the floating gate electrode 7 of the semiconductor nonvolatile memory element (3).

The third gate insulating film 15 and the control gate electrode 8 are formed.

Next, in order to form a source / drain region of the semiconductor nonvolatile memory device, an N-type impurity of As or P is implanted by an ion implantation method so as to be 1 × 10 ²⁰ / cm 3 or more (4).

Although not shown in the figure, after forming an insulating film made of an oxide film as a whole and forming a contact hole at a predetermined position, formation of a metal interconnection for imparting electric potential to the gate, source, drain and body of the semiconductor nonvolatile memory element Is performed by sputtering and patterning of a metal film.

Further, in order to manufacture the structure shown in the eighth embodiment having one layer of the polycrystalline silicon two-layer gate electrode structure of Fig. 13 described with reference to Fig. 17, in the above manufacturing method, And the step of forming the floating gate electrode 7 on the second gate insulating film. Thereafter, the source / drain regions 12 of the semiconductor nonvolatile memory element are formed and can be manufactured in the same manner. The control gate electrode 8 can be fabricated by combining the structure and the process with, for example, impurities in the N-type high concentration impurity region 17.

Incidentally, in the manufacturing methods of the first to fourth embodiments, the method of forming the first insulating film and the second insulating film was common. If this is the first manufacturing method for forming the gate insulating film, the following second to fifth methods can be employed for the purpose of improving the performance or lowering the cost.

The second method does not use the three-step process of forming the thick oxide film, partially removing the oxide film, and forming the thin oxide film in the first method, 2 at the same time.

Specifically, as shown in Fig. 26 (1), the N-type high concentration impurity region 17 is first formed using As to a high impurity concentration of 1 x 10 ¹⁹ / cm 3 or more.

Next, a wet oxidation using water vapor or a pyrogenic oxidation method in which oxygen gas and hydrogen gas are introduced into the furnace and reacted is used to form a gate insulating film, which is thickened only by the N-type high concentration impurity region 17 due to the accelerated oxidation effect , And the other area is thinned to obtain the shape shown in Fig. 26 (2).

In this case, for example, when the film thickness of the first gate insulating film is 150 angstroms, the film thickness of the second gate insulating film can be set to about 300 angstroms. As the impurity concentration in the semiconductor substrate is high, whether the impurity is N-type or P-type, the accelerated oxidation effect becomes more significant as the degree of disturbance of the lattice of the semiconductor substrate becomes larger. can do. In particular, when used as a gate insulating film, an oxide film grown on an N-type impurity region is preferable. Therefore, this method is an effective method for an N-channel type semiconductor nonvolatile memory device. The reason why the P-type impurity is not preferable is that the P-type impurity enters the oxide film during the thermal oxidation treatment, so that the deterioration of the quality of the oxide film becomes remarkable.

In the above method, the three-step process can be reduced to one step, thereby reducing the process cost and the process time.

Next, a third method of forming the first and second gate insulating films will be described with reference to Figs. 27 (1) to (3).

In the third method, first, a polycrystalline silicon layer 21A having a film thickness of 100 to 400 angstroms is deposited on the entire surface (1).

Next, the polycrystalline silicon layer 21A in the region other than the region where the second gate insulating film is to be formed is removed by the photolithography technique and the etching technique, leaving the polycrystalline silicon layer 21B (2).

Next, in this state, thermal oxidation treatment for forming the first gate insulating film is performed to form silicon oxide films 9 and 14 on the semiconductor substrate. At this time, the second gate insulating film is set to a film thickness at which the polycrystalline silicon 21B is completely oxidized by the thermal oxidation treatment at the time of forming the first gate insulating film, so that the second gate insulating film is composed of the oxide film obtained by oxidizing the polycrystalline silicon can do. The reason why the polycrystalline silicon is used here is that the oxidation speed can be made 1.5 to 2 times faster than that of a typical single crystal silicon due to the disruption of the lattice contained therein (3).

This third method requires no heat treatment for a long time and at a high temperature to form a thick second gate insulating film, so that the N-type channel impurity and the first and second N-type low- There is an effect of suppressing the occurrence of a deviation due to the high temperature heat treatment and promoting the high precision of the device characteristics.

The fourth method will be described based on Figs. 28 (1) to (3). First, a base silicon oxide film having a thickness of 10 to 100 angstroms is formed on the entire surface by thermal oxidation, and then an SiN layer 22 having a thickness of 100 to 200 angstroms is deposited on the entire upper surface thereof by LPCVD (One).

Next, the SiN layer in the region other than the predetermined region of the first gate insulating film is removed by photolithography (2).

Next, the silicon oxide film having a film thickness of about several hundreds of angstroms for forming the second gate insulating film is formed by the thermal oxidation method in this state. At this time, since the first gate insulating film is covered with SiN having low reactivity, the oxide film hardly grows thereon. Thus, the first gate insulating film can be formed of a silicon oxide film of several tens of angstroms, a laminated film of SiN of 100 to 200 angstroms, and a silicon film of several hundreds of angstroms of the second gate insulating film (3).

This fourth method can increase the capacity of the first gate insulating film 9 and reduce the charge Q due to the reduction of the gate electrode size and the lower cost and the leakage of the carriers in the floating gate electrode, There is an advantage that the amount of voltage variation can be reduced.

The fifth method will be described with reference to Figs. 29 (1) to (4). First, similarly to the first method, a second gate insulating film of 100 to 1000 angstroms is formed on the entire surface as a silicon oxide film by a thermal oxidation method (1).

Next, as in the first method, the second gate insulating film in the channel forming region is removed by photolithography and etching (2).

Next, the first gate insulating film is formed by thermal oxidation, but here, the film thickness is made 30 to 100 angstroms thinner than the first method (3).

Next, thermal nitridation treatment is performed at a temperature of 1000 캜 or higher in an ammonia atmosphere. Then, nitrogen diffuses to the interface with the semiconductor substrate under the first gate insulating film and reacts with the semiconductor substrate to form a SiN layer with a thickness of about 1 to 20 Å. On the other hand, since the thickness of the second gate insulating film is sufficiently thick, the amount of nitrogen reaching the interface with the semiconductor substrate by diffusion is very small, and a SiN layer with high insulation property is not formed so as to inhibit carrier tunneling (4).

In the fifth method, since the silicon oxide film constituting the first gate insulating film is as thin as 100 Å or less, the scattering of the carriers in the floating gate electrode due to the leakage current at high temperature is a concern. However, since a high insulating property is obtained by the SiN layer under the oxide film, this leakage is suppressed, and at the same time, the high capacity of the first gate insulating film is realized.

The fourth method is also applied to the formation of the SiN film in the same manner. However, in the method by the CVD method as in the fourth method, the controllability of the film thickness of 100 angstroms or less is deteriorated, and there is a problem that the device characteristics are varied. In the method by the thermal nitriding method as in the fifth method, thinner SiN can be stably formed, which is effective for increasing the precision of the device characteristics.

The present invention is not limited to the step-down type series regulator and the voltage detector described so far, and can be applied. By adopting a memory terminal capable of varying the threshold voltage by the input electrical signal from the adjustment input terminal, the output voltage can be varied by the input electrical signal in various semiconductor integrated circuit devices including the reference voltage circuit . Therefore, it goes without saying that the present invention can be applied to applications other than the power management IC.

1: semiconductor substrate
2: drain terminal
3: Source terminal
4: Body terminal
5: P-type well region
6: gate electrode
7: floating gate electrode
8: Control gate electrode
9: First gate insulating film
10: N-type channel impurity region
11: P-type channel impurity region
12: N-type source / drain region
13: LOCOS oxide film
14: second gate insulating film
15: third gate insulating film
16: carrier injection region
17: N-type high concentration impurity region
18: First N-type low concentration impurity region
19: second N-type low concentration impurity region
20: P-type low concentration impurity region
21: polycrystalline silicon layer
22: SiN layer
100: Reference voltage circuit
101: Error amplifier
102: Resistance element
103:
104: PMOS output element
105: Ground terminal
106: Power terminal
107: Output terminal
108: comparator
109: Terminal A
110: Terminal B
111: Terminal C
112: Input for adjustment
200: unit resistance element
201: Resistance 1
202: Resistance 2
203: Resistance 3
204: Resistance 4
301: Fuse 1
302: Fuse 2
303: Fuse 3
304: Fuse 4
401: Enhancement type NMOS transistor
402: Deposition type NMOS transistor
403: Power terminal
404: ground terminal
405: Reference voltage output terminal
406: Input terminal for adjustment

Claims (22)

A semiconductor substrate;
A well region of a first conductivity type formed in the semiconductor substrate,
A heavily doped source region and a first heavily doped drain region each having a heavily doped impurity of a second conductivity type formed in the well region,
A first gate insulating film formed on the semiconductor substrate between the heavily doped source region and the first heavily doped drain region and adjacent to the heavily doped source region;
A second gate insulating film formed on the semiconductor substrate between the heavily doped source region and the first heavily doped drain region and adjacent to the first heavily doped drain region;
A second heavily doped drain region of a second conductivity type formed in a region overlapping with the first heavily doped drain region, the second heavily doped drain region including a region below the second gate insulating film,
And a second conductive type semiconductor layer formed in an area overlapping the first heavily doped drain region and the second heavily doped drain region and including a region below the first gate insulating film and below the second gate insulating film, A first low-concentration drain region of the first conductivity type,
A channel impurity region of a second conductivity type formed below the first gate insulating film and formed between the high concentration source region and the first low concentration drain region;
A floating gate electrode formed on the first gate insulating film and the second gate insulating film and made of polycrystalline silicon containing a high concentration impurity;
A third gate insulating film formed on the floating gate electrode,
A control gate electrode formed of polycrystalline silicon containing a high concentration impurity and formed on the third gate insulating film;
Lt; / RTI &
The second gate insulating film is thicker than the first gate insulating film,
Wherein the well region includes the heavily doped source region, the first heavily doped drain region, the second heavily doped drain region, the first lightly doped drain region, and the channel impurity region, Wherein the semiconductor nonvolatile memory element is a semiconductor nonvolatile memory element. The method according to claim 1,
And a second low concentration drain region formed to a position deeper than the first low concentration drain region in an area including the first high concentration drain region, the second high concentration drain region and a part of the first low concentration drain region Semiconductor nonvolatile memory device. 3. The method of claim 2,
An insulating film having a thickness larger than that of the first gate insulating film and the second gate insulating film is added on a region between the first gate insulating film and the second gate insulating film and including a part of the first lightly doped drain region Wherein the semiconductor nonvolatile memory element is a semiconductor nonvolatile memory element. The method of claim 3,
The second lightly doped drain region is disposed in a region including the second lightly doped drain region and the first lightly-doped drain region,
Wherein the well region includes the heavily doped source region and the channel impurity region and has an impurity concentration higher than that of the second heavily doped drain region. 5. The method according to any one of claims 2 to 4,
Wherein the impurity of the second lightly doped drain region is As or P of 2 x 10 ¹⁶ cm 3 or more and 2 x 10 ¹⁷ cm 3 or less. A semiconductor substrate;
A well region of a first conductivity type formed in the semiconductor substrate,
A heavily doped source region and a first heavily doped drain region each having a heavily doped impurity of a second conductivity type formed in the well region,
A first gate insulating film formed on the semiconductor substrate between the heavily doped source region and the first heavily doped drain region and adjacent to the heavily doped source region;
A second gate insulating film formed on the semiconductor substrate between the heavily doped source region and the first heavily doped drain region and adjacent to the first heavily doped drain region;
A second heavily doped drain region of a second conductivity type formed in a region overlapping with the first heavily doped drain region, the second heavily doped drain region including a region below the second gate insulating film,
And a second conductive type semiconductor layer formed in an area overlapping the first heavily doped drain region and the second heavily doped drain region and including a region below the first gate insulating film and below the second gate insulating film, A first low-concentration drain region of the first conductivity type,
A channel impurity region of a second conductivity type formed below the first gate insulating film and formed between the heavily doped source region and the first lightly doped drain region;
A floating gate electrode formed on the first gate insulating film and the second gate insulating film and made of polycrystalline silicon containing a high concentration impurity;
A control gate electrode formed in the well region at a position separated from the channel impurity region and formed of a diffusion region having a high concentration impurity of the second conductivity type;
A third gate insulating film formed between the floating gate electrode extended above the diffusion region which is the control gate electrode and the diffusion region which is the control gate electrode,
Lt; / RTI &
Wherein the second gate insulating film is thicker than the first gate insulating film,
Wherein the well region includes the heavily doped source region, the first heavily doped drain region, the second heavily doped drain region, the first lightly doped drain region, and the channel impurity region, Wherein the semiconductor nonvolatile memory element is a semiconductor nonvolatile memory element. The method according to claim 6,
The impurity of the first heavily doped drain region is As or P having a concentration of 1 x 10 < ²⁰ > cm <
The impurity of the second high concentration drain region is As or P of 5 x 10 < ¹⁸ > cm <
The impurity of the first lightly doped drain region is As or P of 1 x 10 ¹⁷ cm 3 or more and 1 x 10 ¹⁸ cm 3 or less,
And the impurity in the well region is boron at a concentration of 7 × 10 ¹⁵ cm -3 to 7 × 10 ¹⁶ cm 3. The method according to claim 6,
Wherein the first gate insulating film has a thickness of 100 to 200 ANGSTROM. The method according to claim 6,
In the semiconductor nonvolatile memory device, characterized in that said first gate insulating film SiON, the second gate insulating film of SiO _2. The method according to claim 6,
In the semiconductor nonvolatile memory device which is characterized in that the first gate insulating layer SiN, and the second gate insulating film of SiO _2. A P-type well region forming step of forming a P-type well region made of a P-type impurity on the semiconductor substrate;
An element isolation insulating film forming step of forming a LOCOS oxide film around the P-type well region;
An N-type high-concentration impurity region forming step of forming an N-type high-concentration impurity region made of an N-type impurity,
An N-type low-concentration region forming step of forming a first N-type low-concentration impurity region having a lower N-type impurity concentration than the N-type high-concentration impurity region and diffused deeply;
A channel region forming step of forming an N-type impurity region in the channel formation scheduled region in the P-type well region,
A gate insulating film forming step of forming a second gate insulating film so as to overlap with the N-type high concentration impurity region in the drain formation scheduled region and forming a first gate insulating film thinner than the second gate insulating film in the channel forming region; ,
Forming a floating gate electrode made of a polycrystalline silicon layer containing an impurity on the first gate insulating film and the second gate insulating film; forming a third gate insulating film on the floating gate electrode; A gate electrode forming step of forming a control gate electrode made of a polycrystalline silicon layer containing impurities,
A source / drain formation step of forming an N-type impurity region in the source formation scheduled region and the drain formation scheduled region
Of the semiconductor nonvolatile memory element. 12. The method of claim 11,
Wherein the step of forming the P-type well region includes a step of forming a second N-type low-concentration region diffused in the drain forming expected region deeper than the first N-type low concentration impurity region Gt; A P-type well region forming step of forming a P-type well region made of a P-type impurity on the semiconductor substrate;
An N-type low-concentration region forming step of forming a first N-type low-concentration impurity region in the P-type well region and a second N-type low-concentration impurity region having a lower impurity concentration than the first N-type low-
An element isolation insulating film forming step of forming a LOCOS oxide film around the P type well region and on the first N type low concentration impurity region;
An N-type high-concentration impurity region forming step of forming an N-type high-concentration impurity region made of an N-type impurity,
A channel region forming step of forming an N-type impurity region in the channel formation scheduled region in the P-type well region,
Forming a second gate insulating film in contact with a LOCOS oxide film formed on the first N type low concentration impurity region in a part of the N type high concentration impurity region; A gate insulating film forming step of forming an insulating film;
Forming a floating gate electrode made of a polycrystalline silicon layer containing an impurity on the first gate insulating film and the second gate insulating film; forming a third gate insulating film on the floating gate electrode; A gate electrode forming step of forming a control gate electrode made of a polycrystalline silicon layer containing impurities,
A source / drain formation step of forming an N-type impurity region in the source formation scheduled region and the drain formation scheduled region
Of the semiconductor nonvolatile memory element. A first low-concentration region forming step of forming a P-type low-concentration impurity region and a second N-type low-concentration impurity region so as to partially overlap with each other in the semiconductor substrate;
A second low-concentration region forming step of forming a first N-type low-concentration impurity region in the second N-type low-concentration impurity region;
An element isolation insulating film forming step of forming a LOCOS oxide film around the P-type low-concentration impurity region, the second N-type low-concentration impurity region, and the first N-type low-
An N-type high-concentration impurity region forming step of forming an N-type high-concentration impurity region made of an N-type impurity,
A channel region forming step of forming an N-type impurity region in the channel formation scheduled region in the P-type low concentration impurity region;
Forming a second gate insulating film in contact with a LOCOS oxide film formed on the first N type low concentration impurity region in a part of the N type high concentration impurity region; A gate insulating film forming step of forming an insulating film;
Forming a floating gate electrode made of a polycrystalline silicon layer containing an impurity on the first gate insulating film and the second gate insulating film; forming a third gate insulating film on the floating gate electrode; A gate electrode forming step of forming a control gate electrode made of a polycrystalline silicon layer containing impurities,
A source / drain formation step of forming an N-type impurity region in the source formation scheduled region and the drain formation scheduled region
Of the semiconductor nonvolatile memory element. 15. The method according to any one of claims 11 to 14,
Wherein the step of forming the gate insulating film includes a step of simultaneously forming the first gate insulating film and the second gate insulating film. 15. The method according to any one of claims 11 to 14,
In the step of forming the gate insulating film, a polycrystalline silicon layer having a thickness of 100 to 400 ANGSTROM is formed to remove only the polycrystalline silicon layer on the channel forming region, and the remaining polycrystalline silicon layer is completely oxidized to remove the silicon oxide film Thereby forming the second gate insulating film. ≪ Desc / Clms Page number 19 > 15. The method according to any one of claims 11 to 14,
Wherein the gate insulating film forming step comprises:
A silicon oxide film having a thickness of 10 to 100 angstroms is formed by thermal oxidation in the semiconductor nonvolatile memory element formation region and a silicon nitride film of 100 to 200 angstroms is deposited on the silicon oxide film to form the first gate insulating film ,
And a step of removing only the silicon nitride film on the region other than the channel formation scheduled region and forming the silicon oxide film by thermal oxidation to form the second gate insulating film in a region to be subjected to drain formation . 15. The method according to any one of claims 11 to 14,
Wherein the gate insulating film forming step includes forming a gate insulating film made of a silicon oxide film having a thickness of 100 to 1000 angstroms by thermal oxidation and removing only the gate insulating film on the channel formation scheduled region to form the second gate insulating film,
Next, a silicon oxide film having a thickness of 30 to 100 angstroms is formed by thermal oxidation, a silicon nitride film of 1 to 20 angstroms is formed under the silicon oxide film of 30 to 100 angstroms, And forming the first gate insulating film by a thermal nitriding method which is subjected to heat treatment in the step of forming the first gate insulating film. A P-type well region forming step of forming a P-type well region made of a P-type impurity on the semiconductor substrate;
An element isolation insulating film forming step of forming a LOCOS oxide film around the P-type well region;
An N-type high-concentration impurity region forming step of forming an N-type high-concentration impurity region made of an N-type impurity,
An N-type low-concentration region forming step of forming a first N-type low-concentration impurity region having a lower N-type impurity concentration than the N-type high-concentration impurity region and diffused deeply;
A channel region forming step of forming an N-type impurity region in the channel formation scheduled region in the P-type well region,
A gate insulating film forming step of forming a second gate insulating film so as to overlap with the N-type high concentration impurity region in the drain formation scheduled region and forming a first gate insulating film thinner than the second gate insulating film in the channel forming region; ,
A gate electrode forming step of forming a floating gate electrode made of a polycrystalline silicon layer containing an impurity on the first gate insulating film and the second gate insulating film;
A source / drain formation step of forming an N-type impurity region in the source formation scheduled region and the drain formation scheduled region
Of the semiconductor nonvolatile memory element. 20. The method of claim 19,
Wherein the step of forming the P-type well region includes a step of forming a second N-type low-concentration region diffused in the drain forming expected region deeper than the first N-type low concentration impurity region Gt; A P-type well region forming step of forming a P-type well region made of a P-type impurity on the semiconductor substrate;
An N-type low-concentration region forming step of forming a first N-type low-concentration impurity region in the P-type well region and a second N-type low-concentration impurity region having a lower impurity concentration than the first N-type low-
An element isolation insulating film forming step of forming a LOCOS oxide film around the P type well region and on the first N type low concentration impurity region;
An N-type high-concentration impurity region forming step of forming an N-type high-concentration impurity region made of an N-type impurity,
A channel region forming step of forming an N-type impurity region in the channel formation scheduled region in the P-type well region,
Forming a second gate insulating film in contact with a LOCOS oxide film formed on the first N type low concentration impurity region in a part of the N type high concentration impurity region; A gate insulating film forming step of forming an insulating film;
A gate electrode forming step of forming a floating gate electrode made of a polycrystalline silicon layer containing an impurity on the first gate insulating film and the second gate insulating film;
A source / drain formation step of forming an N-type impurity region in the source formation scheduled region and the drain formation scheduled region
Of the semiconductor nonvolatile memory element. A first low-concentration region forming step of forming a P-type low-concentration impurity region and a second N-type low-concentration impurity region so as to partially overlap with each other in the semiconductor substrate;
A second low-concentration region forming step of forming a first N-type low-concentration impurity region in the second N-type low-concentration impurity region;
An element isolation insulating film forming step of forming a LOCOS oxide film around the P-type low-concentration impurity region, the second N-type low-concentration impurity region, and the first N-type low-
An N-type high-concentration impurity region forming step of forming an N-type high-concentration impurity region made of an N-type impurity,
A channel region forming step of forming an N-type impurity region in the channel formation scheduled region in the P-type low concentration impurity region;
Forming a second gate insulating film in contact with a LOCOS oxide film formed on the first N type low concentration impurity region in a part of the N type high concentration impurity region; A gate insulating film forming step of forming an insulating film;
A gate electrode forming step of forming a floating gate electrode made of a polycrystalline silicon layer containing an impurity on the first gate insulating film and the second gate insulating film;
A source / drain formation step of forming an N-type impurity region in the source formation scheduled region and the drain formation scheduled region
Of the semiconductor nonvolatile memory element.

Images