JPH10209306A - Nonvolatile semiconductor memory and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure a tolerance for showing specified electric characteristics, by providing a drain region having regions different in impurity concn. and source region having more different-impurity concn. regions than the drain region. SOLUTION: A memory cell transistor 30 has a source and drain regions 6, 7 formed to face each other below an FG 3 on a main surface of a semiconductor substrate. The source region 7 is composed of a low impurity concn. region 6a creeping in the FG 3, medium impurity concn. region 6c having outer edges beneath the FG 3 and high impurity concn. region 6b apart from the side face of the FG 3 rather than from the region 6c. The drain region 7 is composed of a low impurity concn. region 7a creeping in the FG 3, medium impurity concn. region 7b having outer edges beneath the FG 3. Thus, tolerance for showing specified electric characteristics is ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device having a structure in which source and drain regions of a storage element are asymmetric.

[0002]

2. Description of the Related Art A DINOR (Divided NOR) flash memory, which is an example of a conventional nonvolatile semiconductor memory device, will be described below with reference to FIG. 9, FIG. 10 and FIG.

FIG. 9 is a sectional view of a main part showing the structure of a memory cell transistor 28 of a conventional DINOR type flash memory. In FIG. 9, reference numeral 1 denotes a semiconductor substrate made of, for example, a P-type silicon substrate; A gate insulating film made of a silicon oxide film formed on one main surface of
Is a floating gate (hereinafter, referred to as "FG") formed on the gate insulating film 2 and formed of a conductive film such as a polycrystalline silicon film or an amorphous silicon film, and 4 is an interlayer insulating film formed on the FG 3 Film, for example, TEOS (Te
(traethoxysilane), silicon nitride film,
And a three-layer laminated film 5 made of TEOS is a control gate (hereinafter, referred to as “CG”) formed on the interlayer insulating film 4 and made of, for example, a polycrystalline silicon film.

[0006] Reference numerals 60 and 70 denote source and drain regions of the memory cell transistor 28, respectively, which are formed on the main surface of the semiconductor substrate 1 so as to face below the FG3, and a part of each is located below the FG3. The low-concentration impurity region 60 formed in a shape such that it penetrates
a, 70a, and high-concentration impurity regions 60b, 70b formed to have outer edges almost immediately below the side surfaces of FG3.

[0005] Here, the high concentration and the low concentration are not absolute impurity concentrations, but indicate that there is a relative difference in impurity concentration between each impurity region. As the absolute value, it is necessary to select an optimum value in consideration of the length of each of the control gate and the floating gate, the type of the implanted ions, and other various conditions according to the electrical characteristics of the memory cell transistor 28.

Symbols such as N− and N ++ in the figure do not indicate absolute impurity concentrations as in the above description, but symbols used to indicate the relative impurity concentration differences between the respective regions. It is.

[0007] 8 and 90 are the gate insulating film 2 and the FG
3, sidewalls formed on the source and drain regions 60 and 70 with the interlayer insulating film 4 and the CG 5 interposed therebetween, and 10 is an overlying oxide film made of a silicon oxide film such as TEOS formed on the CG 5 , Part of the source side is cut off. Reference numeral 11 denotes a side wall of the overlying oxide film 10, which is formed on the source side on the CG 5.

Next, a method of manufacturing a conventional nonvolatile semiconductor memory device having the above-described structure will be described with reference to FIGS.
1 will be described. 10 and 11 show a conventional DIN.
FIG. 6 is a cross-sectional view of a main part showing a method of manufacturing an OR type flash memory for each of a memory cell portion having a memory cell transistor and a peripheral circuit portion having a peripheral transistor in the order of steps.

First, as shown in FIG. 10A, a gate oxide film 2 is formed on a semiconductor substrate 1 made of, for example, a P-type silicon substrate by, for example, a thermal oxidation method.
A first conductive film 3a made of, for example, a polycrystalline silicon film or an amorphous silicon film, which becomes G3, is deposited using a CVD method, and is patterned into a desired shape using a normal photoengraving technique. FG3 is formed in the portion. continue,
TEO is formed on the entire surface of the semiconductor substrate 1 as an interlayer insulating film 4.
Three layers of S, a silicon nitride film and TEOS are sequentially deposited. Next, the interlayer insulating film 4 and the first conductive film 3a formed in the peripheral circuit portion are removed.

Next, a gate oxide film 12 for the peripheral transistor is formed by thermal oxidation, and a gate electrode 13 of the peripheral transistor is partially formed in both the peripheral circuit portion and the memory cell portion.
Then, a second conductive film 5a, which is made of, for example, a polycrystalline silicon film or a compound film of a polycrystalline silicon and a high melting point metal, which becomes CG5, is deposited by a CVD method.
Further, an oxide film 14 of TEOS or the like and a polycrystalline silicon film 15 are sequentially deposited thereon.

Next, as shown in FIG. 10B, a resist is coated on the polycrystalline silicon film 15 and is patterned into a desired shape to form a resist mask 1.
6 is formed.

Next, as shown in FIG. 10C, the polycrystalline silicon film 1 is formed by using the formed resist mask 16.
5 is processed by anisotropic etching, and then the resist mask 16 is removed.

Next, as shown in FIG. 10D, using the polycrystalline silicon film 15 processed into the desired shape as a mask, the silicon oxide film 14 is processed by anisotropic etching to form an oxide film mask. 14a, and then using the oxide film mask 14a, a second conductive film 5 under the oxide film mask 14a.
is processed by anisotropic etching to form the gate electrode 13 and the CG 5 of the peripheral transistor.

Here, the polycrystalline silicon film 15 on the oxide mask 14a is simultaneously removed by the anisotropic etching used for forming the gate electrode 13 and the CG 5. Further, the oxide film mask 14 a in the peripheral circuit portion becomes an overlying oxide film 17 for the gate electrode 13.

Next, as shown in FIG. 11A, the peripheral circuit portion is covered with a resist, and only the memory cell portion is anisotropically etched using the oxide film mask 14a to form an interlayer insulating film 4 and a first insulating film. FG by processing the conductive film 3a of
Form 3 Thereafter, the resist covering the peripheral circuit portion is removed. At this time, when the interlayer insulating film 4 is etched, the oxide film mask 14a in the memory cell portion is also etched, and the film thickness is reduced.

Next, as shown in FIG. 11B, a resist mask 18 is formed to cover the source side and the peripheral circuit portion of the memory cell portion and open to the drain side of the memory cell portion. Is used to implant ions of phosphorus and arsenic into the semiconductor substrate 1 to form the drain region 70 of the memory cell transistor. Here, a small amount of boron may be simultaneously injected. After that, the resist mask 18 is removed.

Next, as shown in FIG. 11C, the word line direction on the surface of the semiconductor substrate 1 which covers the drain side of the memory cell section and the peripheral circuit section (in FIG. 2, the direction perpendicular to the paper). A portion serving as a source region 60 of each memory cell transistor, a separation oxide film isolating a portion serving as a source region 60 of each memory cell transistor, and
Oxide film mask 1 on CG5 of each memory cell transistor
4a, a resist mask 19 having an opening on the surface is formed, and anisotropic etching using the resist mask 19 is performed.
The isolation oxide film is removed so that the portions serving as the source regions 60 of the memory cell transistors arranged in the word line direction are connected, and the surface of the semiconductor substrate 1 covered with the isolation oxide film is exposed. Hereinafter, this anisotropic etching is referred to as SAS
(Self-aligned source) This is called etching.

At this time, the oxide film mask 14a on the CG 5 is also etched at the same time, so that the overlying oxide film 10 of the memory cell transistor is formed.

Next, ion implantation of phosphorus and arsenic is performed in a self-aligning manner using the CG 5 and the resist mask 19 from which a part of the overlying oxide film 10 has been removed to form a source region 60. Here, a small amount of boron may be simultaneously ion-implanted. At this time, on the surface of the semiconductor substrate 1 exposed by the SAS etching step and in the vicinity thereof, a wiring having a structure in which the source regions 60 of the respective memory cell transistors arranged in the word line direction are connected in parallel with the word line (so-called “source line”). ) Is formed.

Next, after removing the resist mask 19, FIG.
As shown in FIG. 1D, the gate insulating films 12 and 2 are processed by performing anisotropic etching using the gate electrode 13 and the CG 5 as a mask, and then, for example, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1. By forming an insulating film made of CVD using a CVD method and performing anisotropic etching,
Gate electrode 13 of peripheral transistor and overlying oxide film 17
The sidewall 20 is formed on the side surface of
3 and source and drain regions 60, 7 on the sides of CG5
The sidewalls 8 and 90 are formed on the zero.

Subsequently, the memory cell portion is covered with a resist,
For example, phosphorus or arsenic is ion-implanted at a high concentration to form source and drain regions 2 of the peripheral transistor.
1 and 22 are formed, and a peripheral transistor 29 is obtained. Thereafter, the resist covering the memory cell portion is removed.

Thereafter, the dopants implanted into the source and drain regions 60 and 70 are thermally diffused by performing a heat treatment, so that the low-concentration impurity regions 60a and 60a each partially penetrate under the FG3. 7
0a and high-concentration impurity regions 60b and 70b having an outer edge almost immediately below the side surface of the FG3 to obtain a DINOR type flash memory including the memory cell transistor 28 shown in FIG.

[0023]

However, in the above-described nonvolatile semiconductor memory device, both the source region 60 and the drain region 70 of the memory cell transistor are formed by ion-implanting the CG 5 in a self-aligned manner. Therefore, a part of the implanted ions is formed immediately below the end of the CG 5, and the low-concentration impurity regions 60 a and 70 a
Since each is formed under G5, CG
There is a problem that the substantial channel length between the source region 60 and the drain region 70 is shorter than the length of the fifth region.

For this reason, in the conventional nonvolatile semiconductor memory device, the control gate length (the length of the CG 5) must be maintained at a certain value or more in order to obtain desired electric characteristics. It was a cause of hindrance to the conversion.

On the other hand, the source and drain regions 60 and 70 of the memory cell transistor are formed by using the side walls 8 and 90 as masks to form the source and drain regions 60 and 70 of the peripheral transistor.
It can be performed by ion implantation to form the drain regions 21 and 22, but in this case,
Since the side walls 8 and 90 are obtained by anisotropically etching the insulating film for forming the side wall 20 of the peripheral transistor, the thickness thereof is defined according to the electrical characteristics of the peripheral transistor 29. Depending on the thickness, the source and drain regions 60 and 70 may be formed at positions far away from immediately below the end of the CG 5, and there is a problem that it becomes difficult for current to flow.

Therefore, in the ion implantation step after the SAS etching shown in FIG.
Prior to the step of forming the side walls 21 and 22 of the peripheral transistor, a side wall having a thickness corresponding to the electrical characteristics of the memory cell transistor 28 is once formed, and thereafter, high-concentration ion implantation is performed using the side wall as a mask. By doing so, it is also possible to solve the above problem.

However, in this case, as a pre-process of high-concentration ion implantation, a resist mask for ion implantation as shown in FIG. 11D, that is, the drain side of the peripheral circuit portion and the memory cell portion is used. It is necessary to form a resist mask that covers the semiconductor device, which causes a new problem that the number of steps increases.

Further, in this case, the sidewall 20 of the peripheral transistor after the high-concentration implantation must be formed in consideration of the thickness of the already formed sidewall. In addition to the variation in the film thickness when depositing the sidewall insulating film, and the variation in the thickness of the sidewall when the insulating film is anisotropically etched, the variation in the thickness of the sidewall insulating film of the peripheral transistor 29 is caused. And the variation in the thickness of the side wall when anisotropic etching is performed overlaps with each other, causing a problem that the variation in the thickness of the sidewall 20 of the peripheral transistor becomes large.

Therefore, the source and drain regions 21 and 2 of the peripheral transistor formed by ion implantation using the side wall 20 having this variation as a mask.
There is also a problem that the channel length between the two has a small margin for achieving the desired electrical characteristics.

Regarding the positions of the source and drain regions 60 and 70 of the memory cell transistor, in a DINOR type flash memory, the operation as a storage element is achieved by extracting charges from the drain region 70 to FG3. It is necessary to form a high-concentration impurity region 70b at the end of the FG3 on the side of the FG3. If it is formed at a position away from the end of the FG3, the charge extraction speed becomes slow. There is also a problem that the operation speed of the flash memory is delayed.

For the above-described reason, in the conventional nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device exhibits predetermined electric characteristics due to a variation in the interval between the source region 60 and the drain region 70 during manufacturing. (Generally called “L margin”) cannot be secured.

The present invention has been made in view of the above points, and even when the gate length of a memory cell transistor is reduced, a predetermined variation in the distance between the source region and the drain region during manufacturing is prevented. It is an object of the present invention to obtain a nonvolatile semiconductor memory device that can secure a margin for exhibiting the electrical characteristics of the nonvolatile semiconductor memory device.

[0033]

A nonvolatile semiconductor memory device according to the present invention includes a storage element formed on one main surface of a semiconductor substrate, and the storage element is provided on a first surface of the semiconductor substrate. A first conductive layer formed via an insulating film of
A second conductive layer formed on the first conductive layer with a second insulating film interposed therebetween, and a source formed on the main surface of the semiconductor substrate so as to face below the first conductive layer. And a drain region, wherein the drain region has a plurality of regions having different impurity concentrations, and the source region has more regions having different impurity concentrations than the drain region.

The plurality of regions having different impurity concentrations in each of the source and drain regions are characterized in that the closer to the first conductive layer, the lower the impurity concentration.

The semiconductor device further includes a storage element formed on one main surface of the semiconductor substrate, wherein the storage element includes a first conductive layer formed on the main surface of the semiconductor substrate via a first insulating film. A second conductive layer formed on the first conductive layer with a second insulating film interposed therebetween, and formed on the main surface of the semiconductor substrate so as to face below the first conductive layer. A source and drain region, and a pair of sidewalls formed on the source or drain region with the first and second conductive layers interposed therebetween; and a pair of sidewalls formed on the drain region in the pair of sidewalls. The sidewall formed in
It is characterized by having more layers than the sidewalls formed on the source region.

Further, the layers of the pair of sidewalls are all formed of the same type of insulating film.

According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, a first conductive layer formed on one main surface of a semiconductor substrate with a first insulating film interposed therebetween is formed on the first conductive layer. Having a second conductive layer formed with a second insulating film interposed therebetween, and a source and drain region formed on the main surface of the semiconductor substrate so as to face below the first conductive layer. In a method for manufacturing a non-volatile semiconductor memory device including an element and a peripheral transistor formed on a main surface of the semiconductor substrate, a method for manufacturing the non-volatile semiconductor memory device includes: A step of depositing an insulating film to be a part of a side wall, and a step of performing ion implantation using a mask opened above a portion of the semiconductor substrate to be a source region of the storage element. Than it is.

Further, the step of depositing the insulating film and the step of performing ion implantation are repeated a plurality of times.

Further, the step of performing the ion implantation is characterized in that the implantation amount is increased in later steps.

Further, a first conductive layer formed on one main surface of the semiconductor substrate via a first insulating film, and a first conductive layer formed on the first conductive layer via a second insulating film. A second conductive layer;
A non-volatile storage device having a storage element having a source and a drain region formed on a main surface of the semiconductor substrate so as to face below the first conductive layer, and a peripheral transistor formed on the main surface of the semiconductor substrate; Depositing an insulating film that becomes a part of a sidewall of the peripheral transistor on a portion of the semiconductor substrate on which the storage element and the peripheral transistor are formed; Etching a part of the insulating film using a mask opened above a portion to be a source region of the memory element.

Further, the step of depositing the insulating film and the step of etching a part of the insulating film are each repeated a plurality of times.

As the insulating film deposited a plurality of times,
All are characterized by using the same type of insulating film.

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, Embodiment 1 of the present invention will be described with reference to FIGS.

FIG. 1 is a cross-sectional view of a main part showing a structure of a memory cell transistor 30 of a nonvolatile semiconductor memory device according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 1 denotes a semiconductor substrate made of, for example, a P-type silicon substrate. Reference numeral 2 denotes a gate insulating film made of a silicon oxide film formed on one main surface of the semiconductor substrate 1, and reference numeral 3 denotes a conductive film formed on the gate insulating film 2 such as a polycrystalline silicon film or an amorphous silicon film. A floating gate (hereinafter, referred to as “FG”) made of a film, 4 is an interlayer insulating film formed on FG3,
For example, TEOS (Tetraethoxysilan)
e), a three-layer laminated film composed of a silicon nitride film and TEOS, and a control gate (hereinafter, “CG”) composed of, for example, a polycrystalline silicon film formed on the interlayer insulating film 4.
That. ) And form part of a word line.

Reference numerals 6 and 7 denote source and drain regions of the memory cell transistor 30, respectively, which are formed on the main surface of the semiconductor substrate 1 so as to face below the FG3. Of these, the source region 6 has a low-concentration impurity region 6a partially formed under the FG3 and a medium-concentration impurity region formed so as to have an outer edge almost immediately below the side surface of the FG3. 6c and a high-concentration impurity region 6b formed at a position further away from the side surface of the FG 3 than the medium-concentration impurity region 6c.
On the other hand, the drain region 7 has a low-concentration impurity region 7a formed so as to partially penetrate under the FG3, and a high-concentration impurity region 7b formed to have an outer edge almost immediately below the side surface of the FG3. It is composed of

Here, the high, medium and low concentrations are defined as
It is not an absolute impurity concentration, but a relative impurity concentration difference between the impurity regions. This indicates that the absolute value of the concentration of each impurity region is
It is necessary to select an optimum value in consideration of the length of each of the control gate and the floating gate, the type of implanted ions, and other various conditions according to the electrical characteristics of the semiconductor device.

The symbols N−, N +, N ++ in the figure do not indicate the absolute impurity concentration as in the above case.
This is a symbol used to represent the relative difference in impurity concentration between the regions.

8 and 9 are the gate insulating film 2 and the FG
3, a sidewall made of, for example, a silicon oxide film formed on the source and drain regions 6 and 7 with the interlayer insulating film 4 and the CG 5 interposed therebetween. In particular, the sidewall 9 on the drain region is an FG3 And the like, and is constituted by a layer 9a in contact with the side surface and a layer 9b formed outside the layer 9a. Reference numeral 10 denotes an overlying oxide film made of a silicon oxide film such as TEOS formed on the CG 5, and a part on the source side is cut off. Reference numeral 11 denotes a side wall of the overlying oxide film 10, which is formed on the source side on the CG 5.

Next, a method for manufacturing a nonvolatile semiconductor memory device having the memory cell transistor 30 having such a structure will be described with reference to FIGS. FIGS. 2 to 4 show the method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment in the order of steps for each of the memory cell portion having the memory cell transistor 30 and the peripheral circuit portion having the peripheral transistor 40. It is a fragmentary sectional view.

First, as shown in FIG. 2A, a gate oxide film 2 is formed on a semiconductor substrate 1 made of, for example, a P-type silicon substrate by, for example, a thermal oxidation method, and FG is formed thereon.
First, a first conductive film 3a made of, for example, a polycrystalline silicon film or an amorphous silicon film or the like is deposited by a CVD method, and is patterned into a desired shape using a normal photolithography technique. FG3 is formed in the portion. continue,
TEO is formed on the entire surface of the semiconductor substrate 1 as an interlayer insulating film 4.
Three layers of S, a silicon nitride film and TEOS are sequentially deposited. Next, the interlayer insulating film 4 and the first conductive film 3a formed in the peripheral circuit portion are removed.

Next, a gate oxide film 12 for the peripheral transistor 40 is formed by thermal oxidation, and a part of the gate oxide film 12 is formed in both the peripheral circuit part and the memory cell part, and the other part is formed of the CG5 in the peripheral circuit part and the memory cell part. For example, a second conductive film 5a made of a polycrystalline silicon film or a compound film of polycrystalline silicon and a refractory metal is deposited by a CVD method. Further, an oxide film 14 of TEOS or the like and a polycrystalline silicon film 15 are sequentially deposited thereon.

Next, as shown in FIG. 2B, a resist is applied on the polycrystalline silicon film 15 and is patterned into a desired shape to form a resist mask 16.
To form

Next, as shown in FIG. 3A, a polycrystalline silicon film 15 is formed using the formed resist mask 16.
Is processed by anisotropic etching, and then the resist mask 16 is removed.

Next, as shown in FIG. 3B, using the polycrystalline silicon film 15 processed into the desired shape as a mask, the silicon oxide film 14 is processed by anisotropic etching to form an oxide film mask. 14a, and using the oxide film mask 14a, a second conductive film 5a thereunder is formed.
Is processed by anisotropic etching to form the gate electrode 13 of the peripheral transistor and the CG 5.

Here, the polycrystalline silicon film 15 on the oxide film mask 14a is simultaneously removed by the anisotropic etching used for forming the gate electrode 13 and the CG 5. Further, the oxide film mask 14 a in the peripheral circuit portion becomes an overlying oxide film 17 for the gate electrode 13.

Next, as shown in FIG. 3C, the peripheral circuit portion is covered with a resist, and only the memory cell portion is anisotropically etched using the oxide film mask 14a to form an interlayer insulating film 4 and a first insulating film. FG by processing the conductive film 3a of
Form 3 Thereafter, the resist covering the peripheral circuit portion is removed. At this time, when the interlayer insulating film 4 is etched, the oxide film mask 14a in the memory cell portion is also etched, and the film thickness is reduced.

Next, as shown in FIG. 3D, a resist mask 18 is formed to cover the source side and the peripheral circuit portion of the memory cell portion and open to the drain side of the memory cell portion. Is used to implant ions of phosphorus and arsenic into the semiconductor substrate 1 to form the drain region 7 of the memory cell transistor. Here, a small amount of boron may be simultaneously injected. After that, the resist mask 18 is removed.

Next, as shown in FIG. 4A, the oxide film 23 of the same type (for example, TEOS) is thinner than the insulating film for the side wall of the peripheral transistor 40.
Is deposited on the entire surface of the semiconductor substrate 1.

Next, as shown in FIG. 4B, the drain side of the memory cell portion and the peripheral circuit portion are covered, and the word line direction of the semiconductor substrate 1 (in FIGS. Direction), a portion serving as the source region 6 of each memory cell transistor, an isolation oxide film separating the portion serving as the source region 6 of each memory cell transistor, and an oxide mask 14 on the CG 5 of each memory cell transistor.
a resist mask 24 opening to the surface a is formed, and the resist mask 24 is used to
A portion 25 of the source region 6 is ion-implanted at a high concentration, such as arsenic, and finally becomes a high-concentration impurity region 6b.
To form

At this time, the CG on the source side of the memory cell portion
Since the thickness of the oxide film 23 formed on the semiconductor substrate 1 located immediately below the five ends is thicker in the ion incident direction, incident ions (for example, arsenic) do not reach the semiconductor substrate 1. Therefore, a high-concentration impurity region 6b is formed at a position away from immediately below the end of the CG 5. Also, CG
5 does not receive incident ions such as arsenic due to the resist 24 and the oxide film mask 14a.

Next, as shown in FIG. 4C, anisotropic etching using a resist mask 24 is performed to separate and oxidize the memory cell transistors arranged in the word line direction so as to be connected to the source region 6. The film is removed, and the surface of the semiconductor substrate 1 covered with the isolation oxide film is exposed.
Hereinafter, this anisotropic etching is referred to as SAS (self-aligned source) etching. At this time, the oxide film 23 on the CG 5 and the oxide film mask 14a are simultaneously etched to form the overlying oxide film 10 of the memory cell transistor.

Next, ion implantation of phosphorus and arsenic is performed in a self-aligned manner by using the CG 5 and the resist mask 19 from which a part of the overlying oxide film 10 has been removed, as shown in FIG. The implantation is performed at a concentration relatively lower than that of the implantation, and the outer edge thereof is located closer to the vicinity of the end of the CG 5 than the part 25 of the source region, and finally the impurity regions 6a and 6c having the low concentration and the medium concentration are formed. , A part 26 of the source region 6 is formed. Here, a small amount of boron may be simultaneously ion-implanted. At this time, a wiring (a so-called “source line”) having a structure in which the source regions 6 of the respective memory cell transistors connected in the word line direction are connected to the surface of the semiconductor substrate 1 previously exposed by the SAS etching step and the vicinity thereof. It is formed parallel to the line.

Next, after removing the resist mask 19, FIG.
As shown in (d), the gate insulating films 12 and 2 are processed by performing anisotropic etching using the gate electrode 13 and the CG 5 as a mask, and subsequently, for example, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1. By forming an insulating film using the CVD method and performing anisotropic etching, a sidewall 20 is formed on the side surface of the gate electrode 13 and the overlying oxide film 17 of the peripheral transistor, and at the same time, the FG3 is formed.
And the sidewalls 8 and 9 are formed on the source and drain regions 6 and 7 on the side surfaces of the CG 5.

Subsequently, the memory cell portion is covered with a resist,
For example, by implanting phosphorus or arsenic at a high concentration, the source and drain regions 21 of the peripheral transistor,
The peripheral transistor 40 is obtained by forming 22. Here, a small amount of boron may be simultaneously ion-implanted. Thereafter, the resist covering the memory cell portion is removed.

Thereafter, the dopant implanted into the source and drain regions is thermally diffused by performing a heat treatment, so that the low-concentration impurity region 6a, the medium-concentration impurity region 6c, the high-concentration impurity region 6b, and the low-concentration impurity region 6b. The non-volatile semiconductor memory device including the memory cell transistor 30 shown in FIG. 1 is obtained by forming the high concentration impurity region 7a and the high concentration impurity region 7b.

Here, in the step shown in FIG. 4C, since dopants having different diffusion lengths due to thermal diffusion, such as phosphorus and arsenic, are implanted, they are part of the source region in this heat treatment step. 26 are formed separately in the medium concentration and low concentration impurity regions 6c and 6a.

In the first embodiment, since the structure is as described above, even if the CG 5 is miniaturized, the high concentration impurity region 7b is formed in the drain region 7.
Are formed immediately below CG5, while source region 6 is formed.
Only the high-concentration impurity region 6b can be kept away from immediately below the end of the CG 5, and the low-concentration impurity region 6a, 7a which defines the substantial length of the channel region between the source and drain regions 6, 7 Can be maintained at such a distance that current does not easily flow, so that the nonvolatile semiconductor memory device according to the present invention has a predetermined electrical characteristic with respect to variations in the interval between the source region 6 and the drain region 7 during manufacturing. , Ie, an L margin can be secured.

In the drain region 7, a high-concentration impurity region 7b is formed near the end of the CG 5 in order to extract charges. In addition, a low-concentration impurity region 7a is formed. Therefore, there is an effect that a decrease in drain withstand voltage can be prevented.

In the first embodiment, each of source and drain regions 6 and 7 has multi-stage impurity concentration regions 6a, 6c, 6b and 7a, 7b, and
Since they are arranged so that their impurity concentration becomes higher as they go away from CG5, an LDD structure can be formed, threshold voltage fluctuation can be suppressed, and high reliability of the present nonvolatile semiconductor memory device can be realized. It has the effect of being able to.

Further, in the first embodiment, only the oxide film 23 is deposited in the peripheral circuit portion, and after the side wall of the memory cell transistor 30 is once formed as in the above-described conventional example. Since the sidewall 20 of the peripheral transistor is not formed,
The side wall 20 of the peripheral transistor does not vary due to the etching.
When depositing an insulating film for formation, the oxide film 2 previously deposited
3, the insulating film may be deposited.

In the first embodiment, since the above-described manufacturing method is used, compared to the conventional manufacturing method, the number of steps for depositing oxide film 23 is increased by only one step. A nonvolatile semiconductor memory device having a structure having an effect can be obtained.

In Embodiment 1, FIG.
In the step shown in FIG. 5C, since the highly anisotropic SAS etching is performed, even if it takes a long time to remove the oxide film 23, as shown in FIG. There is. In such a case, once the isolation oxide film is removed, the SAS etching is terminated, and the remaining oxide film 23a is subjected to dry etching with relatively weak anisotropy or an etching rate of low concentration hydrofluoric acid or the like. May be removed by wet etching having a small diameter.

Also, in the first embodiment, FIG.
In the step shown in (c), since dopants having different diffusion lengths due to thermal diffusion, such as phosphorus and arsenic, are implanted, the intermediate concentration and low concentration impurity regions 6c and 6a are formed separately by a heat treatment in a later step. Alternatively, implantation using either one of the ions may be performed. In this case, as shown in FIG. 6, the middle of the source region 6 of the memory cell transistor is removed. The impurity region 6c of the concentration is not formed.

However, also in this case, it is possible to keep the high-concentration impurity region 6b only in the source region 6 more than immediately below the end of the CG 5, and to further reduce the substantial length of the channel region between the source and drain regions 6 and 7. The distance between the low-concentration impurity regions 6a and 7a, which define the height, can be kept at such a distance that the current does not easily flow. It has the regions 6a, 6b and 7a, 7b, and is arranged so that the impurity concentration thereof becomes higher as the distance from the CG 5 increases, and the same effect as described above is obtained.

Further, in the above case, the case where the memory cell transistor 30 and the peripheral transistor 40 are of the N-channel type is shown, but FIGS. 3 (d) and 4 (b)
In the step shown in (c), boron or BF ₂ may be ion-implanted instead of phosphorus, arsenic, or the like. In this case, these dopants are unlikely to thermally diffuse,
As in the case described above, it is not possible to separately form the medium concentration and low concentration impurity regions 6c and 6a by thermal diffusion, but the N (and P) type region shown in FIG.
The source and drain regions can be formed in a shape changed to the (and N) type, so that the same effect as described above can be obtained.

Embodiment 2 Embodiment 2 of the present invention
Differs from the first embodiment in that the high-concentration regions 6b of the source and drain regions of the memory cell transistor 30
The only difference is that the second high-concentration regions 6d and 7d have an outer edge at a position further away from the CG 5 than the CG 5 and have a higher impurity concentration than the high-concentration regions 6b and 7b. The other points are the same as in the first embodiment.

FIG. 7 is a cross-sectional view of a main part showing a structure of a nonvolatile semiconductor memory device according to the second embodiment of the present invention. The structure of this device is different from the structure of the nonvolatile semiconductor memory device shown in FIG. 1 of the first embodiment in that the CG5 is higher than the high concentration regions 6b and 7b of the source and drain regions of the memory cell transistor. Second high-concentration regions 6d, 7 having an outer edge at a further distant position and having a higher impurity concentration than high-concentration regions 6b, 7b.
d.

Next, a description will be given of a method of manufacturing the nonvolatile semiconductor memory device thus configured. Although the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment takes different steps from the steps shown in FIG. 4D in the first embodiment, other steps are the same as those shown in FIGS. It includes the same steps as those in the manufacturing method according to the first embodiment shown in FIG.

Specifically, in the second embodiment,
After forming the sidewalls 8, 9, and 20 shown in FIG. 4D, the peripheral transistor is implanted at a high concentration, for example, with phosphorus or arsenic without covering the memory cell portion with a resist. Source and drain regions 2
At the same time as forming the first and second regions 22, the second high-concentration regions 6d and 7d are formed using the side walls 8 and 9 as a mask.

In the second embodiment, the first embodiment
In comparison with the first embodiment, since ion implantation can be performed without forming a resist mask covering a memory cell portion, the number of steps can be reduced, and the same effect as that of the first embodiment can be obtained. Becomes possible.

In addition, in the second embodiment, the second
In the high-concentration regions 6d and 7d, the contact with the drain region 7 can be made, so that the impurity region in the drain region 7 not related to the charge extraction, that is, not related to the memory operation, specifically, For example, it is possible to reduce the impurity concentration in the deep portion immediately below the end of the FG3.

In the second embodiment, when forming the source and drain regions 21 and 22 of the peripheral transistor, the resist does not cover the memory cell portion having the same conductivity type memory cell transistor. By performing high-concentration ion implantation, there is an effect that the possibility of charge-up can be reduced and destruction of an electric element due to charge-up can be prevented.

Embodiment 3 Embodiment 3 of the present invention
In contrast to the first embodiment, as shown in FIG. 4B, instead of performing high-concentration ion implantation of arsenic through the oxide film 23, after exposing the surface of the semiconductor substrate 1, Embodiment 1 is different only in that arsenic is directly implanted into the semiconductor substrate 1 at a high concentration.
Is the same as

The third embodiment will be described below with reference to FIG. FIG. 8 is a fragmentary cross-sectional view showing a method of manufacturing the nonvolatile semiconductor memory device according to Embodiment 3 for each of the memory cell portion and the peripheral circuit portion in the order of steps.

In the third embodiment, the process up to the formation of the resist mask 24 shown in FIG. 4B is the same as the manufacturing method of the first embodiment. Immediately before performing high-concentration implantation, as shown in FIG.
3 and anisotropic etching to such an extent that the residual portion of the gate insulating film 2 is removed. As a result, the surface of the semiconductor substrate 1 on the source side of the memory cell portion is exposed, and the oxide film 2 is exposed.
3 are formed.

Here, if the thickness of the side wall 27 becomes too thin by etching, the high concentration impurity region 25 formed by arsenic implanted at a high concentration will
Since it is too close to the end of G5, the desired effect cannot be obtained. Therefore, in the above-mentioned etching, although the surface of the semiconductor substrate 1 is exposed, it is not preferable to perform more etching than necessary. Therefore, here, the oxide film 23 is used.
In addition, it is necessary to perform appropriate etching to the extent that the residue of the gate insulating film 2 is removed. Here, the anisotropic etching may use the same method as the SAS etching.

Next, as shown in FIG. 8B, arsenic is ion-implanted directly and at a high concentration into the semiconductor substrate 1 exposed by the anisotropic etching to form a part 25 of the source region 6. . . Subsequent steps are the same as those shown in FIG.
(C) The same as the following steps.

In the third embodiment, the first embodiment
Since an etching step for the oxide film 23 on the source side of the memory cell portion is added, the number of steps in the first embodiment is increased by only one in the conventional method. In the third embodiment, the total number of steps is increased by two steps.
An effect similar to that of the first embodiment can be obtained.

In addition, in the third embodiment, since ion implantation is performed through oxide film 23 in the first embodiment,
Although high implantation energy is required, ion implantation can be performed directly on the semiconductor substrate 1, so that there is an effect that an increase in implantation energy is not required.

In the third embodiment, the anisotropic etching and the high-concentration ion implantation are performed only once each on only the source side of the memory cell portion. Instead, FIG. After the step shown in the above, before performing the SAS etching, the resist mask 24 is removed, an oxide film is deposited again, a resist mask is formed, anisotropic etching is performed, and high-concentration ion implantation is performed. Furthermore, by repeating these series of steps a plurality of times, the source and drain regions 6 and 7 obtained in the third embodiment can be obtained.
In addition, a larger number of regions having different impurity concentrations can be formed. That is, the source and drain regions 6, 7
Can be further subdivided.

Here, the thickness of the oxide film to be deposited is:
The thickness should not exceed the thickness of the insulating film deposited for the sidewalls 20 of the peripheral transistor.

In the above case, the case where the memory cell transistor 30 and the peripheral transistor 40 are of the N-channel type has been described, but in the step shown in FIG. 8B, boron or BF is used instead of arsenic. ₂ may be ion-implanted, and in this case, the same effect as described above is obtained.

[0093]

According to the present invention, a nonvolatile semiconductor memory device includes a memory element formed on one main surface of a semiconductor substrate,
The storage element is formed on a first conductive layer formed on a main surface of the semiconductor substrate via a first insulating film, and is formed on the first conductive layer via a second insulating film. A second conductive layer; and a source and drain region formed on the main surface of the semiconductor substrate so as to face below the first conductive layer. The drain region has a plurality of regions having different impurity concentrations. And the source region has a region having a larger impurity concentration than the drain region. Therefore, even when the second conductive layer is miniaturized, only the source region has an impurity concentration lower than that of the drain region. Since the high region can be separated from the second conductive layer, the nonvolatile semiconductor memory device exhibits predetermined electric characteristics with respect to a variation in the interval between the source region and the drain region during manufacturing. It has the effect of ensuring tolerance.

The plurality of regions having different impurity concentrations in each of the source and drain regions is characterized in that the closer the region is to the first conductive layer, the lower the impurity concentration is. With such a structure, it is possible to suppress a change in threshold voltage and the like, and to achieve an effect of realizing high reliability.

Further, the semiconductor device further includes a storage element formed on one main surface of the semiconductor substrate, and the storage element includes a first conductive layer formed on the main surface of the semiconductor substrate via a first insulating film. A second conductive layer formed on the first conductive layer with a second insulating film interposed therebetween, and formed on the main surface of the semiconductor substrate so as to face below the first conductive layer. A source and drain region, and a pair of sidewalls formed on the source or drain region with the first and second conductive layers interposed therebetween; and a pair of sidewalls formed on the drain region in the pair of sidewalls. The sidewall formed in
Since the semiconductor device has more layers than the sidewalls formed on the source region, the ion implantation in the step of forming the source region may be performed by the respective layers of the sidewalls at the time of manufacturing the nonvolatile semiconductor memory device. Is performed each time the second conductive layer is miniaturized, since the source region has a region having a different impurity concentration than the drain region. In addition, it is possible to separate a region having a high impurity concentration only from the source region from the second conductive layer, so that the nonvolatile semiconductor memory device is capable of preventing variations in the interval between the source region and the drain region during manufacturing. This has an effect that a margin for exhibiting predetermined electrical characteristics can be secured.

Further, since the layers of the pair of sidewalls are all formed of the same type of insulating film, the formation of the nonvolatile semiconductor memory device is facilitated and the manufacturing cost is reduced. This has the effect that it can be achieved.

The method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes the steps of: forming a first conductive layer formed on one main surface of a semiconductor substrate via a first insulating film; Having a second conductive layer formed with a second insulating film interposed therebetween, and a source and drain region formed on the main surface of the semiconductor substrate so as to face below the first conductive layer. In a method for manufacturing a non-volatile semiconductor memory device including an element and a peripheral transistor formed on a main surface of the semiconductor substrate, a method for manufacturing the non-volatile semiconductor memory device includes: A step of depositing an insulating film to be a part of a side wall, and a step of performing ion implantation using a mask opened above a portion of the semiconductor substrate to be a source region of the storage element. In the nonvolatile semiconductor memory device manufactured by this method, the number of steps is increased only by increasing the number of steps of depositing the insulating film for the sidewall, and the source region has a higher impurity concentration than the drain region. It is possible to have different regions. for that reason,
Even when the second conductive layer is miniaturized with only a slight increase in manufacturing time and a slight increase in manufacturing cost, a region having a high impurity concentration only in the source region is separated from the second conductive layer. This makes it possible to secure an allowance for the nonvolatile semiconductor memory device to exhibit predetermined electrical characteristics with respect to variations in the interval between the source region and the drain region during manufacturing.

Also, since the step of depositing the insulating film and the step of implanting ions are repeated a plurality of times, the nonvolatile semiconductor memory device manufactured by this method has Since the second conductive layer has more regions having different impurity concentrations than the drain region, even when the second conductive layer is miniaturized, the variation in the interval between the source region and the drain region during manufacturing is reduced. This has the effect that a larger margin for the nonvolatile semiconductor memory device to exhibit predetermined electrical characteristics can be secured.

In the above-described ion implantation step, the amount of implantation increases in later steps. Therefore, in the nonvolatile semiconductor memory device manufactured by this method, the source and drain regions have an LDD structure. This has the effect of suppressing fluctuations in the threshold voltage, etc., and realizing high reliability.

Further, a first conductive layer formed on one main surface of the semiconductor substrate via a first insulating film, and a first conductive layer formed on the first conductive layer via a second insulating film. A second conductive layer;
A non-volatile storage device having a storage element having a source and a drain region formed on a main surface of the semiconductor substrate so as to face below the first conductive layer, and a peripheral transistor formed on the main surface of the semiconductor substrate; Depositing an insulating film that becomes a part of a sidewall of the peripheral transistor on a portion of the semiconductor substrate on which the storage element and the peripheral transistor are formed; Etching a portion of the insulating film using a mask opened above a portion serving as a source region of the storage element. Therefore, the nonvolatile semiconductor memory device manufactured by this method includes: The implantation energy for ion implantation for forming the gate electrode can be suppressed, and the ion implantation By performing the following etching step, as a result, the source region is to have different regions of many impurity concentration than the drain region. Therefore, even when the second conductive layer is miniaturized, a region having a high impurity concentration only in the source region can be separated from the second conductive layer. Has an effect that the nonvolatile semiconductor memory device can secure a margin for exhibiting predetermined electrical characteristics.

Further, since the step of depositing the insulating film and the step of etching a part of the insulating film are repeated a plurality of times, the nonvolatile semiconductor memory device manufactured by this method has the following features. Since the source region has a region with a much higher impurity concentration than the drain region, even when the second conductive layer is miniaturized, the distance between the source region and the drain region may be reduced. This has an effect that the nonvolatile semiconductor memory device can secure a larger margin for exhibiting predetermined electrical characteristics with respect to the variation.

Further, as the insulating film deposited a plurality of times,
Since all are characterized by using the same type of insulating film,
The nonvolatile semiconductor memory device manufactured by this method includes:
This has the effect that the formation of the device is easy and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view showing a structure of a memory cell transistor of a nonvolatile semiconductor memory device according to Embodiment 1 of the present invention;

FIG. 2 is a fragmentary cross-sectional view showing a method of manufacturing the nonvolatile semiconductor memory device according to Embodiment 1 of the present invention for each of the memory cell portion and the peripheral transistor portion in the order of steps;

FIG. 3 is a fragmentary cross-sectional view showing a method of manufacturing the nonvolatile semiconductor memory device according to Embodiment 1 of the present invention for each of the memory cell portion and the peripheral transistor portion in the order of steps;

FIG. 4 is a fragmentary cross-sectional view showing a method of manufacturing the nonvolatile semiconductor memory device according to Embodiment 1 of the present invention for each of the memory cell portion and the peripheral transistor portion in the order of steps;

FIG. 5 is a cross-sectional view of a main part of the nonvolatile semiconductor memory device in which an oxide film remains without being removed by SAS etching;

FIG. 6 is a fragmentary cross-sectional view showing a structure of a memory cell transistor of a nonvolatile semiconductor memory device formed by implanting one type of ions.

FIG. 7 is a fragmentary cross-sectional view showing a structure of a memory cell transistor of the nonvolatile semiconductor memory device according to Embodiment 2 of the present invention;

FIG. 8 is a fragmentary cross-sectional view showing a method of manufacturing the nonvolatile semiconductor memory device according to Embodiment 3 of the present invention for each of the memory cell portion and the peripheral transistor portion in the order of steps;

FIG. 9 is a fragmentary cross-sectional view showing a structure of a memory cell transistor of a conventional nonvolatile semiconductor memory device.

FIG. 10 is a fragmentary cross-sectional view showing a conventional method of manufacturing a nonvolatile semiconductor memory device in the order of steps for each of a memory cell portion and a peripheral transistor portion;

FIG. 11 is a fragmentary cross-sectional view showing a conventional method of manufacturing a nonvolatile semiconductor memory device in the order of steps for each of a memory cell portion and a peripheral transistor portion;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 1st insulating film, 3 1st
Conductive layer, 4 second insulating film, 5 second conductive layer,
6, a source region, 6a, 6b, 6c, 6d, a region forming a source region, 7 a drain region, 7a, 7b,
7d One region forming a drain region, 8 Side wall formed on a source region, 9 Side wall formed on a drain region, 9a, 9b Layer forming a side wall on a drain region, 23 Side of peripheral transistor Insulating film serving as a part of a wall, 24 mask, 25, 26 A portion serving as a source region of a memory element of a semiconductor substrate, 30 memory element, 40 peripheral transistor.

Claims (10)

[Claims] A first conductive layer formed on a main surface of the semiconductor substrate with a first insulating film interposed therebetween; and a storage element formed on one main surface of the semiconductor substrate. A second conductive layer formed on the first conductive layer with a second insulating film interposed therebetween, and formed on the main surface of the semiconductor substrate so as to face below the first conductive layer. A non-volatile semiconductor device having a source and a drain region, wherein the drain region has a plurality of regions having different impurity concentrations, and the source region has a region having a higher impurity concentration than the drain region. Storage device. 2. The non-volatile semiconductor storage device according to claim 1, wherein the plurality of regions having different impurity concentrations in the source and drain regions have lower impurity concentrations as the regions are closer to the first conductive layer. . 3. A semiconductor device comprising: a storage element formed on one main surface of a semiconductor substrate; wherein the storage element has a first conductive layer formed on a main surface of the semiconductor substrate via a first insulating film. A second conductive layer formed on the first conductive layer with a second insulating film interposed therebetween, and formed on the main surface of the semiconductor substrate so as to face below the first conductive layer. A source and drain region, and a pair of sidewalls formed on the source or drain region with the first and second conductive layers interposed therebetween; The non-volatile semiconductor memory device according to claim 1, wherein the side wall formed on the source region has more layers than the side wall formed on the source region. 4. The nonvolatile semiconductor memory device according to claim 3, wherein all the layers included in the pair of sidewalls are formed of the same type of insulating film. 5. A first conductive layer formed on one main surface of a semiconductor substrate via a first insulating film, and a first conductive layer formed on the first conductive layer via a second insulating film. A memory element having a second conductive layer, source and drain regions formed on the main surface of the semiconductor substrate so as to face below the first conductive layer, and formed on the main surface of the semiconductor substrate A method of manufacturing a nonvolatile semiconductor memory device having a peripheral transistor, wherein an insulating film that becomes a part of a sidewall of the peripheral transistor is deposited on a portion of the semiconductor substrate on which the storage element and the peripheral transistor are formed. A method of manufacturing a non-volatile semiconductor memory device, comprising: a step of performing ion implantation using a mask that is opened above a portion of the semiconductor substrate to be a source region of the storage element. 6. The method according to claim 5, wherein the step of depositing the insulating film and the step of performing ion implantation are repeated a plurality of times. 7. The method for manufacturing a nonvolatile semiconductor memory device according to claim 6, wherein in the step of performing ion implantation, the amount of implantation is increased in later steps. 8. A first conductive layer formed on one principal surface of a semiconductor substrate via a first insulating film, and a first conductive layer formed on the first conductive layer via a second insulating film. A memory element having a second conductive layer, source and drain regions formed on the main surface of the semiconductor substrate so as to face below the first conductive layer, and formed on the main surface of the semiconductor substrate A method of manufacturing a nonvolatile semiconductor memory device having a peripheral transistor, wherein an insulating film that becomes a part of a sidewall of the peripheral transistor is deposited on a portion of the semiconductor substrate on which the storage element and the peripheral transistor are formed. A method of manufacturing a nonvolatile semiconductor memory device, comprising: a step of etching a part of the insulating film using a mask that is opened above a part of the semiconductor substrate that is to be a source region of the storage element. 9. The method according to claim 8, wherein the step of depositing the insulating film and the step of etching a part of the insulating film are repeated a plurality of times. 10. The insulating film of the same kind is used as an insulating film deposited a plurality of times.
10. The method for manufacturing a nonvolatile semiconductor memory device according to claim 7.