JP2011210896A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including an NMOS transistor for ESD protection in the shallow trench isolation structure having sufficient ESD protecting function through suppression of an off-leak current to a small value without increase in the manufacturing steps and occupation area.SOLUTION: The semiconductor device includes the NMOS transistor for ESD protection having a shallow trench isolation area 501 for isolation of element. Moreover, in this NMOS transistor for ESD protection, a type P breakdown area 401 formed of a high-concentration type P impurity concentration area is formed, via an offset area 601 isolated by constant distance from a drain area 202 of the NMOS transistor for ESD protection, at the front surface of a channel area formed at the front surface of the type P silicon substrate via a gate insulated film at the lower surface of a gate electrode 301 of the NMOS transistor for ESD protection.

Description

  The present invention provides an ESD protection device having a shallow trench structure for element isolation formed between an external connection terminal and an internal circuit area to protect an internal element formed in the internal circuit area from being destroyed by ESD. The present invention relates to a semiconductor device having an N-type MOS transistor.

  In recent years, with the miniaturization of semiconductor devices, many semiconductor devices having MOS type transistors having shallow trench isolation have been seen. However, particularly in the case of a semiconductor device that uses shallow trench isolation as an element isolation structure, there is a problem in that it has a region where a leakage current such as a crystal defect layer is likely to occur in a region near the shallow trench due to the structure itself or the manufacturing method. In particular, the off-leakage current of an off-transistor having a large transistor width is a further problem. Further, in order to quickly release the ESD current using the bipolar operation, it is necessary to set a breakdown voltage generally called a trigger voltage lower than that of the internal element.

  As an improvement measure for reducing the leakage current of such an off transistor, an example in which a plurality of transistors are arranged so as to be completely turned off between a power supply (Vdd) and a ground (Vss) has been proposed (for example, Patent Document 1).

JP 2002-231886 A

  However, if the W width is reduced in order to keep the off-leakage current of the off transistor small, a sufficient protection function cannot be achieved. Further, in the semiconductor device in which a plurality of transistors are arranged so as to be completely turned off between the power supply (Vdd) and the ground (Vss) as in the improvement example, the occupied area increases because of the plurality of transistors, There were problems such as increased costs.

In order to solve the above problems, the present invention is configured as follows.
In an N-type MOS transistor for ESD protection having a shallow trench isolation region for element isolation, a channel region formed on the surface of a P-type silicon substrate via a gate insulating film on the lower surface of the gate electrode of the N-type MOS transistor for ESD protection A semiconductor device in which a P-type breakdown region composed of a dense P-type impurity concentration region is formed on the surface of the semiconductor device through an offset region spaced apart from the drain region of the ESD protection N-type MOS transistor by a certain distance. .

The P-type breakdown region is a semiconductor device arranged so as to cover the entire width of the channel region of the N-type MOS transistor for ESD protection.
The P-type breakdown region is a semiconductor device disposed only in a part of the channel region of the ESD protection N-type MOS transistor.
The P-type breakdown region is a semiconductor device in contact with the shallow trench isolation region for element isolation arranged around the N-type MOS transistor for ESD protection.

Further, the P-type impurity concentration in the P-type breakdown region and the width of the offset region are determined so that the breakdown voltage of the N-type MOS transistor for ESD protection is the surface of the internal transistor formed in the internal circuit region. The semiconductor device is set to be lower than the breakdown voltage and higher than the power supply voltage of the internal circuit.
The depth of the P-type breakdown region is a semiconductor device deeper than the depth of the drain region of the N-type MOS transistor for ESD protection.

  By the means described above, a semiconductor device having an N-type MOS transistor for ESD protection having a sufficient ESD protection function in which the trigger voltage is set low while suppressing the off-leakage current without increasing the occupied area is obtained. Can do.

1 is a schematic plan view showing a first embodiment of an N-type MOS transistor for ESD protection in a semiconductor device according to the present invention. FIG. 6 is a schematic plan view showing a second embodiment of an N-type MOS transistor for ESD protection of a semiconductor device according to the present invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic plan view showing a first embodiment of an N-type MOS transistor for ESD protection of a semiconductor device according to the present invention.

  A source region 201 and a drain region 202 made of a pair of N-type high-concentration impurity regions are formed, and an appropriate P-type impurity (not shown) is introduced between the source region 201 and the drain region 202 to provide a threshold value. A channel region in which the voltage is adjusted is formed, and a gate insulating film made of a silicon oxide film or the like (not shown) is provided on the channel region, and a gate made of polysilicon or the like whose potential is fixed to the ground potential on its upper surface. An electrode 301 is disposed to form an N-type MOS transistor.

  A shallow trench structure is used for insulation isolation from other elements, and the outer periphery of the transistor is surrounded by a shallow trench isolation region 501.

  Here, the surface of the channel region formed on the surface of the P-type silicon substrate through the gate insulating film on the lower surface of the gate electrode 301 of the N-type MOS transistor is interposed via the offset region 601 spaced from the drain region 202 by a certain distance. Thus, a P-type breakdown region 401 composed of a dense P-type impurity concentration region is formed over the entire channel width of the N-type MOS transistor.

  Here, since the P-type breakdown region 401 is in contact with the shallow trench isolation region 501 for element isolation disposed around the N-type MOS transistor for ESD protection, the vicinity of the shallow trench isolation region 501 peculiar to the shallow trench isolation. It is possible to prevent an increase in leakage current that easily occurs.

  The P-type impurity concentration in the P-type breakdown region 401 and the width of the offset region 601 are such that the surface breakdown voltage of the N-type MOS transistor for ESD protection is the surface breakdown of the internal transistor formed in the internal circuit region. It is set to be lower than the down voltage and higher than the power supply voltage of the internal circuit.

  When a power supply voltage for normal operation is applied to the drain region 202 of the N-type MOS transistor for ESD protection, the depletion layer extends in the offset region 601 so that breakdown does not occur.

  On the other hand, when a large surge due to static electricity is applied to the drain region 202 of the N-type MOS transistor for ESD protection, the depletion layer extending from the drain region 202 to the offset region 601 reaches the P-type breakdown region 401 and P A breakdown is caused by forming a high electric field region near the boundary of the mold breakdown region 401.

  Further, the depth of the P-type breakdown region 401 is formed so as to be deeper than the depth of the drain region 202 of the N-type MOS transistor for ESD protection, and a depletion layer extending from the drain region 202 to the offset region 601. Can be firmly received even in deep areas.

  In this way, when a large surge due to static electricity is applied to the N-type MOS transistor for ESD protection, bipolar operation can be started with a lower trigger voltage than the transistor in the internal element region, and the internal element is destroyed by ESD. Can be protected efficiently.

  FIG. 2 is a schematic plan view showing a second embodiment of the N-type MOS transistor for ESD protection of the semiconductor device according to the present invention.

  The difference from the first embodiment shown in FIG. 1 is that the P-type breakdown region 401 is not formed over the entire channel width of the N-type MOS transistor for ESD protection, and is in a portion in contact with the shallow trench isolation region 501. It is only the point that is formed.

  The P-type breakdown region 401 is only partially formed with respect to the channel width of the N-type MOS transistor for ESD protection.

  However, since it is formed only in the portion in contact with the shallow trench isolation region 501, it is possible to prevent an increase in leakage current that tends to occur in the vicinity of the shallow trench isolation region 501 unique to the shallow trench isolation.

  Further, as described in the first embodiment shown in FIG. 1, the P-type impurity concentration in the P-type breakdown region 401 and the width of the offset region 601 depend on the breakdown of the N-type MOS transistor for ESD protection. The voltage is set to be lower than the surface breakdown voltage of the internal transistor formed in the internal circuit region and higher than the power supply voltage of the internal circuit.

  When a power supply voltage for normal operation is applied to the drain region 202 of the N-type MOS transistor for ESD protection, the depletion layer extends in the offset region 601 so that breakdown does not occur.

  On the other hand, when a large surge due to static electricity is applied to the drain region 202 of the N-type MOS transistor for ESD protection, the depletion layer extending from the drain region 202 to the offset region 601 reaches the P-type breakdown region 401 and P A breakdown is caused by forming a high electric field region near the boundary of the mold breakdown region 401.

At this time, unlike the first embodiment shown in FIG. 1, since the P-type breakdown region 401 is formed only in a part of the channel region, the region to be broken down is not the entire width of the channel region. However, after breakdown, the potential of the P-type semiconductor region under the channel region is increased by the trigger current, so that the entire drain region 202 can contribute to the bipolar operation, and a large current can be released.
Other explanations can be replaced with the same reference numerals as those in FIG.

201 Source region 202 Drain region 301 Gate electrode 401 P-type breakdown region 501 Shallow trench isolation region 601 Offset region

Claims (6)

  In an N-type MOS transistor for ESD protection having a shallow trench isolation region for element isolation, a channel region formed on the surface of a P-type silicon substrate via a gate insulating film on the lower surface of the gate electrode of the N-type MOS transistor for ESD protection A semiconductor device in which a P-type breakdown region composed of a dense P-type impurity concentration region is formed on the surface of the semiconductor device through an offset region spaced apart from the drain region of the ESD protection N-type MOS transistor.   2. The semiconductor device according to claim 1, wherein the P-type breakdown region is arranged so as to cover the entire width of the channel region of the N-type MOS transistor for ESD protection.   2. The semiconductor device according to claim 1, wherein the P-type breakdown region is disposed only in a part of the channel region of the ESD protection N-type MOS transistor.   4. The semiconductor device according to claim 3, wherein the P-type breakdown region is in contact with the shallow trench isolation region for element isolation disposed around the N-type MOS transistor for ESD protection.   The P-type impurity concentration in the P-type breakdown region and the width of the offset region are determined so that the breakdown voltage of the N-type MOS transistor for ESD protection is the surface breakdown of the internal transistor formed in the internal circuit region. 2. The semiconductor device according to claim 1, wherein the semiconductor device is set to be lower than a voltage and higher than a power supply voltage of the internal circuit.   The semiconductor device according to claim 1, wherein a depth of the P-type breakdown region is deeper than a depth of the drain region of the N-type MOS transistor for ESD protection.

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