200915535 九、發明說明 【發明所屬之技術領域】 本發明係有關具有MOS電晶體之半導體裝置，其中 ，N -型Μ Ο S電晶體係使用做爲E S D保護元件。 【先前技術】 在具有MOS電晶體的半導體裝置中，其閘極電位係 固定於接地電位（Vss )以保持在關閉狀態中之Ν-型MOS 電晶體被稱爲截止（〇 f f )電晶體，且被使用做爲E S D保 護元件，用以防止內部電路由於來自供外部連接用之墊塊 (pad)的靜電而崩潰（breakdown)。 如圖6所例舉者，截止電晶體721之閘極電極521係 由和位於內部電路區域中之N -型Μ Ο S電晶體7 0 1和P -型 MOS電晶體71 1相同的Ν-型多晶矽膜所構成的。此外， 甚至在具有CMOS電路之半導體裝置中，而CMOS電路 具有同極（homo-polar)聞極結構，其中，N -型MOS電 晶體70 1之閘極電極係由N-型多晶矽膜所構成的，且P-型MOS電晶體71 1之閘極電極係由P-型多晶矽膜所構成 的，截止電晶體之閘極電極5 2 1係由和用於位在內部電路 區域中之內部元件之N -型MOS電晶體相同的N -型多晶矽 膜所構成的。 與形成諸如邏輯電路之內部電路的MOS電晶體不同 ，截止電晶體必須使由靜電所引起之所有大量的電流突然 流動，且因此，電晶體寬度（W)常常被設定爲和幾百微 -4- 200915535 米一樣大。 雖然截止電晶體之閘極電極係固定於Vss，以使截止 電晶體保持在關閉狀態中，因爲臨界電壓係小於1 V ’所 以類似於內部電路之N-型MOS電晶體的情況’次臨界電 流被產生至某種程度。如上所述，因爲截止電晶體之寬度 W大，所以在待命備用（standby)期間之關閉狀態漏電 流因此也大，因而會有在具有截止電晶體安裝於其上之整 個1C的待命備用期間之電流耗損增加的問題。 做爲其對抗措施，多個電晶體被配置於電源線（Vdd )與接地線（Vss )之間，使得ESD保護元件被帶到完全 的關閉狀態（舉例來說，見日本專利申請公開第 2002-231886 號案）。 然而，如果W被做得小，以便降低截止電晶體之關 閉狀態漏電流，則截止電晶體不能夠令人滿意地實施保護 的功能。此外，如同在日本專利申請公開第2 0 0 2 - 2 3 1 8 8 6 號案中所述，在其中多個電晶體被配置於電源線（Vdd ) 與接地線（Vss )之間，以維持完全的關閉狀態之半導體 裝置中，會有該多個電晶體的佔據面積增加，因而導致半 導體裝置之成本上升的問題。 【發明內容】 爲了解決上述問題，依據本發明之半導體裝置包含下 面的結構。 半導體裝置包含：至少一內部元件用N -型MOS電晶 200915535 體，係設置在內部電路區域中；及一 ESD保護用N-型 MOS電晶體，係設置在外部連接端子與該內部電路區域 之間，該ESD保護用N-型MOS電晶體用來保護該內部元 件用N-型MOS電晶體及其他內部元件免於由於ESD而崩 潰。在該半導體裝置中，該ESD保護用N-型MOS電晶體 之臨界電壓被設定爲高於該內部元件用N-型MOS電晶體 之臨界電壓。 該ESD保護用N-型MOS電晶體之閘極電極係由P-型多晶矽所構成的。 該內部電路區域包含該內部元件用N-型MOS電晶體 及一內部元件用P-型MOS電晶體，該內部元件用N-型 MOS電晶體之閘極電極和該內部元件用P-型MOS電晶體 之閘極電極係由N-型多晶矽所構成的。 該內部電路區域包含該內部元件用N-型MOS電晶體 及一內部元件用P-型MOS電晶體，該內部元件用N-型 MOS電晶體之閘極電極係由N-型多晶矽所構成的，而該 內部元件用P-型MOS電晶體之閘極電極係由P-型多晶矽 所構成的。 該ESD保護用N-型MOS電晶體之通道區域中之P-型雜質的濃度被設定爲高於該內部元件用N-型MOS電晶 體之通道區域中之P-型雜質的濃度。 該ESD保護用N-型MOS電晶體之該通道區域中的該 P -型雜質係由用來調整形成在該內部電路區域中之其他 MOS電晶體之通道濃度的P-型雜質（除了 P-型基板之雜 200915535 質和P -型井區域之雜質以外） N -型MOS電晶體之通道濃度的BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an MOS transistor in which an N-type Μ 电 S electro-optic system is used as an E S D protection element. [Prior Art] In a semiconductor device having an MOS transistor, a Ν-type MOS transistor whose gate potential is fixed to a ground potential (Vss) to be kept in a closed state is referred to as a cutoff (〇ff) transistor, It is also used as an ESD protection element to prevent the internal circuit from being broken due to static electricity from a pad for external connection. As exemplified in Fig. 6, the gate electrode 521 of the cut-off transistor 721 is the same as the N-type Μ 电 S transistor 701 and the P-type MOS transistor 71 1 located in the internal circuit region - A polycrystalline tantalum film. Further, even in a semiconductor device having a CMOS circuit, the CMOS circuit has a homo-polar smear structure in which a gate electrode of the N-type MOS transistor 70 1 is composed of an N-type polysilicon film. And the gate electrode of the P-type MOS transistor 71 1 is composed of a P-type polysilicon film, and the gate electrode of the cut-off transistor is used for the internal components in the internal circuit region. The N-type polycrystalline germanium film of the N-type MOS transistor is composed of the same N-type polycrystalline germanium film. Unlike a MOS transistor that forms an internal circuit such as a logic circuit, the cut-off transistor must cause a sudden flow of all of the large amount of current caused by static electricity, and therefore, the transistor width (W) is often set to and several hundred micro-4. - 200915535 meters as big. Although the gate electrode of the cut-off transistor is fixed to Vss so that the cut-off transistor is kept in the off state, since the threshold voltage is less than 1 V ', the case of the N-type MOS transistor similar to the internal circuit 'subcritical current Was produced to some extent. As described above, since the width W of the cut-off transistor is large, the off-state leakage current during the standby standby period is therefore large, and thus there is a standby standby period of the entire 1C having the cut-off transistor mounted thereon. The problem of increased current consumption. As a countermeasure, a plurality of transistors are disposed between the power supply line (Vdd) and the ground line (Vss), so that the ESD protection element is brought to a completely closed state (for example, see Japanese Patent Application Laid-Open No. 2002) -231886). However, if W is made small in order to lower the off-state leakage current of the cut-off transistor, the cut-off transistor cannot satisfactorily perform the function of protection. Further, as described in Japanese Patent Application Laid-Open No. 2 0 0 2 - 2 3 8 8 6 , in which a plurality of transistors are disposed between a power supply line (Vdd) and a ground line (Vss), In a semiconductor device in which a completely closed state is maintained, there is a problem in that the occupied area of the plurality of transistors increases, which causes an increase in the cost of the semiconductor device. SUMMARY OF THE INVENTION In order to solve the above problems, a semiconductor device according to the present invention includes the following structure. The semiconductor device includes: at least one internal component for the N-type MOS transistor 200915535 body, is disposed in the internal circuit region; and an ESD protection N-type MOS transistor is disposed between the external connection terminal and the internal circuit region The N-type MOS transistor for ESD protection is used to protect the internal component from N-type MOS transistors and other internal components from being broken by ESD. In the semiconductor device, the threshold voltage of the N-type MOS transistor for ESD protection is set to be higher than the threshold voltage of the N-type MOS transistor for the internal device. The gate electrode of the N-type MOS transistor for ESD protection is composed of P-type polysilicon. The internal circuit region includes the N-type MOS transistor for the internal component and the P-type MOS transistor for the internal component, the gate electrode of the N-type MOS transistor for the internal component and the P-type MOS for the internal component The gate electrode of the transistor is composed of N-type polysilicon. The internal circuit region includes an N-type MOS transistor for the internal component and a P-type MOS transistor for the internal component, wherein the gate electrode of the N-type MOS transistor is composed of N-type polysilicon. The gate electrode of the P-type MOS transistor of the internal component is composed of P-type polysilicon. The concentration of the P-type impurity in the channel region of the N-type MOS transistor for ESD protection is set to be higher than the concentration of the P-type impurity in the channel region of the N-type MOS transistor for the internal device. The P-type impurity in the channel region of the N-type MOS transistor for ESD protection is a P-type impurity (in addition to P- for adjusting the channel concentration of other MOS transistors formed in the internal circuit region). Type substrate miscellaneous 200915535 impurity and P-type well region impurities) channel concentration of N-type MOS transistor
電壓，且因此，能夠獲得具有 ESD保護用Ν-型MOS電晶 禾口用來調整該內部元件用 p_型雜質所構成的。 g >1 ·型Μ Ο S電晶體之該閘 體的半導體裝置，其能夠抑制關閉狀態漏電流’而同時能 夠令人滿意地實施E S D保護的功能’但不需增加製程步 驟及佔據面積。 【實施方式】 (第一實施例） 圖1爲例舉依據本發明第一實施例之半導體裝置的 ESD保護用N -型MOS電晶體、內部元件用N -型MOS電 晶體、和內部元件用P -型Μ Ο S電晶體的示意剖面視圖。 首先，敘述ESD保護用Ν-型MOS電晶體721。 一對之ESD保護用Ν -型MOS電晶體的源極區域221 和ESD保護用Ν-型M0S電晶體的汲極區域222 (其係由 Ν-型重度摻雜的雜質區域所構成）係形成於做爲第一導電 類型之半導體基板的Ρ-型矽基板101上，源極區域221 和汲極區域222係藉由透過淺溝槽隔離或LOCOS法而 形成於其間的元件隔離區域3 0 1而和其他元件電氣隔離。 ESD保護用Ν -型MOS電晶體的通道區域621係形成 200915535The voltage, and therefore, can be obtained by using a Ν-type MOS transistor for ESD protection to adjust the p_ type impurity of the internal element. g >1 The semiconductor device of the gate of the S-type transistor can suppress the leakage current in the off state and at the same time satisfactorily perform the function of the E S D protection, but does not require an increase in the number of processing steps and the occupation area. [Embodiment] FIG. 1 is a view showing an N-type MOS transistor for ESD protection, an N-type MOS transistor for internal components, and an internal component for a semiconductor device according to a first embodiment of the present invention. Schematic cross-sectional view of a P-type Μ 电 S transistor. First, a Ν-type MOS transistor 721 for ESD protection will be described. A pair of ESD protection uses a source region 221 of the NMOS-type MOS transistor and a drain region 222 of the Ν-type MOS transistor for ESD protection (which is composed of a Ν-type heavily doped impurity region) On the Ρ-type germanium substrate 101 as the semiconductor substrate of the first conductivity type, the source region 221 and the drain region 222 are formed in the element isolation region 3 0 1 by the shallow trench isolation or the LOCOS method. It is electrically isolated from other components. The channel region 621 of the Ν-type MOS transistor for ESD protection is formed 200915535
在ESD保護用N-型MOS電晶體的源極區域221與ESD 保護用N-型MOS電晶體的汲極區域222之間，ESD保護 用N-型MOS電晶體的P-型閘極電極5 22係經由閘極絕緣 膜421而被形成在通道區域621的上方，P -型閘極電極 5 22係由P-型多晶矽膜來予以形成的，且閘極絕緣膜421 係由矽氧化物膜等等來予以形成的。注意，源極區域22 1 被電連接，以便具有和ESD保護用N-型MOS電晶體的 P-型閘極電極522之接地電位（Vss )(未顯示出）相同 的接地電位（Vss )，其使得ESD保護用N-型MOS電晶 體72 1保持關閉狀態，其係所謂的截止電晶體之關閉狀態 。此外，汲極區域222係連接至外部連接端子。 注意，爲了簡單起見，在圖1的例子中，僅例舉出 ESD保護用N-型MOS電晶體721，其具有一對之ESD保 護用N-型MOS電晶體的源極區域221和ESD保護用N-型MOS電晶體的汲極區域222，它們係由N-型重度摻雜 的雜質區域所構成的。然而，因爲真正的ESD保護用 型MOS電晶體需要大的電晶體寬度，以便使由靜電所引 起之大量的電流流動，所以真正的ESD保護用N-型M〇S 電晶體常常被形成而具有許多個源極區域和汲極區域。 接著，敘述內部元件的N-型MOS電晶體701和內部 元件的P -型Μ 0 S電晶體7 1 1。 首先，有關內部元件的Ν-型MOS電晶體701，一對 之內部元件用Ν-型MOS電晶體的源極區域201和內部元 件用Ν-型MOS電晶體的汲極區域2 02 (其係由Ν-型重度 200915535 摻雜的雜質區域所構成）係形成於做爲第一導電類型之半 導體基板的P -型矽基板1 01上，源極區域2 0 1和汲極區 域202係藉由透過淺溝槽隔離或LOCOS法而被形成於其 間的元件隔離區域3 0 1而和其他元件電氣隔離。 內部元件用N-型M0S電晶體的通道區域601係形成 在內部元件用N-型M0S電晶體的源極區域201與內部元 件用N-型M0S電晶體的汲極區域202之間，內部元件用 N-型MOS電晶體的N-型閘極電極501係經由閘極絕緣膜 401而被形成在通道區域601的上方，N-型閘極電極501 係由N-型多晶矽膜來予以形成的，且閘極絕緣膜40 1係 由矽氧化物膜等等來予以形成的。 接著，有關內部元件的P-型MOS電晶體71 1，一對 之內部元件用P-型M0S電晶體的源極區域21 1和內部元 件用P-型MOS電晶體的汲極區域212 (其係由P-型重度 摻雜的雜質區域所構成）係形成於設置在做爲第一導電類 型之半導體基板之P-型矽基板101的N-井區域1 1 1上， 源極區域2 11和汲極區域2 1 2係藉由透過淺溝槽隔離或 LOCOS法而被形成於其間的元件隔離區域301而和其他 元件電氣隔離。 內部元件用P-型M0S電晶體的通道區域61 1係形成 在內部元件用P-型M0S電晶體的源極區域21 1與內部元 件用P -型Μ 0 S電晶體的汲極區域2 1 2之間，內部元件用 Ρ -型Μ 0 S電晶體的Ν -型閘極電極5 1 1係經由閘極絕緣膜 411而被形成在通道區域611的上方，Ν-型閘極電極51 1 -9- 200915535 係由N-型多晶矽膜來予以形成的，且閘極絕緣膜411係 由矽氧化物膜等等來予以形成的。 接著’比較ESD保護用.型MOS電晶體721、內部 元件的N -型MOS電晶體701和內部元件的P -型MOS電 晶體7 1 1而敘述本發明之特性。 在ESD保護用N-型MOS電晶體721中，ESD保護用 N-型MOS電晶體的P-型閘極電極5 22係由P-型多晶矽所 構成的，且因此，因爲在P-型多晶矽與形成ESD保護用 N-型MOS電晶體的通道區域621之P-型矽基板101間之 功函數上的差異’所以和內部元件的N-型MOS電晶體 701之反相電壓相較下，需要更高的反相電壓。 換言之，ESD保護用N-型MOS電晶體721具有比內 部元件用N-型MOS電晶體701之臨界電壓更高的臨界電 壓，且因此，在閘極電位係固定於〇 V ( Vss )的情況中 之關閉狀態漏電流能夠被抑制到低位準。 ESD保護用N-型MOS電晶體721係與形成諸如邏輯 電路之內部電路的MOS電晶體（包含內部元件用N-型 MOS電晶體701)不同，且必須使由靜電所引起之所有大 量的電流突然流動，因而，電晶體寬度（W )被設定爲和 幾百微米一樣大。因此，ESD保護用N-型MOS電晶體 72 1之關閉狀態漏電流的抑制在減少於整個半導體裝置（ 具有ESD保護用N-型MOS電晶體721安裝於其上）的待 命備用期間之電流耗損方面係高度有效的。 依據本發明，因爲ESD保護用N-型MOS電晶體之 -10- 200915535 P-型閘極電極522係由P-型多晶矽所構成的，所以ESD 保護用N -型Μ 0 S電晶體7 2 1具有比內部元件的N -型 Μ 0 S電晶體（具有由Ν -型多晶矽所構成的閘極電極）之 臨界電壓更高的臨界電壓’且因此，在閘極電位係固定於 0 V ( V s s )的情況中之關閉狀態漏電流能夠被有效地做得 小。這使其可能減少在整個半導體裝置（具有帶有大的W 之ESD保護用N-型MOS電晶體721安裝於其上）的待命 備用期間之電流耗損。 (第二實施例） 圖2爲例舉依據本發明第二實施例之半導體裝置的 ESD保護用N-型MOS電晶體、內部元件用N-型MOS電 晶體、和內部元件用P-型MOS電晶體的示意剖面視圖。 此實施例和圖1所例舉之第一實施例的不同在於內部 元件的P-型MOS電晶體71 1之閘極電極係由P-型多晶矽 膜所構成的。在圖2中，這被例舉爲內部元件用 P-型 MOS電晶體的P -型閘極電極512。 在圖2所例舉之例子中，內部元件的N -型Μ Ο S電晶 體70 1之閘極電極係由Ν-型多晶矽膜所構成的，且內部 元件的Ρ_型MOS電晶體71 1之閘極電極係由Ρ-型多晶砂 膜所構成的，此爲通常被稱爲同極（homopolar)聞極電 晶體。特別是，這常常被使用做爲藉由形成P-型MOS電 晶體的通道於矽基板表面側上且使漏電流小而使半導體裝 置之低電壓操作成爲可能的技術。 -11 - 200915535 依據本發明，內部元件用P -型Μ O S電晶體的P -型閘 極電極512及ESD保護用N-型MOS電晶體的P-型閘極 電極522係由相同之p -型多晶矽膜所構成的。 這使其可能獲得到具有同極閘極的半導體裝置，其使 得在第一實施例中所述之關閉狀態漏電流小，而同時令人 滿意地實施爲ESD保護用N-型MOS電晶體721所需之對 抗靜電的保護功能，且能夠操作於低電壓，但不會增加製 程步驟和佔據面積。 有關其他組件，相同的數字被用來指示圖1中所例舉 之相似或相同的組件，且其說明被省略。 (第三實施例） 圖3爲例舉依據本發明第三實施例之半導體裝置的 ESD保護用N -型MOS電晶體、內部元件用N -型MOS電 晶體、和內部元件用P -型Μ Ο S電晶體的示意剖面視圖。 首先’敘述ESD保護用Ν-型MOS電晶體721。 該對之由Ν-型重度摻雜的雜質區域所構成之源極區 域221和汲極區域222係形成在做爲第一導電類型之半導 體基板的Ρ -型矽基板1 〇 1上，源極區域2 2 1和汲極區域 2 2 2係藉由透過淺溝槽隔離或L Ο C Ο S法而被形成於其間 的元件隔離區域3 0 1而和其他元件電氣隔離。 ESD保護用Ν-型MOS電晶體721之通道區域621係 形成在源極區域2 2 1與汲極區域2 2 2之間，由多晶砂膜等 等所構成的閘極電極5 3 2係經由由矽氧化物膜等等所構成 -12- 200915535 的閘極絕緣膜42 1而被形成於通道區域62 1的上方。注意 ，源極區域2 2 1被電連接，以便具有和閘極電極5 3 2之接 地電位（Vss )(未顯示出）相同的接地電位（Vss )，其 使得E S D保護用N -型Μ Ο S電晶體7 2 1保持關閉狀態，其 係所謂的截止電晶體之關閉狀態。此外，汲極區域222係 連接至外部連接端子。 注意，爲了簡單起見，在圖3的例子中’僅例舉出 ESD保護用Ν-型MOS電晶體，其具有一對之由Ν-型重度 摻雜的雜質區域所構成之源極區域22 1和汲極區域222。 然而，真正的ESD保護用Ν -型MOS電晶體需要大的電晶 體寬度，以便使由靜電所引起之大量的電流流動。因此’ 真正的ESD保護用Ν -型MOS電晶體常常被形成而具有許 多個源極區域和汲極區域。 接著，敘述內部元件的Ν -型Μ Ο S電晶體7 〇 1。 該對之由Ν -型重度摻雜的雜質區域所構成的源極區 域20 1和汲極區域202係形成於做爲第一導電類型之半導 體基板的Ρ -型矽基板1 〇 1上，源極區域2 0 1和汲極區域 2 0 2係藉由透過淺溝槽隔離或L Ο C Ο S法而被形成於其間 的元件隔離區域3 01而和其他元件電氣隔離。 內部元件之Ν -型MOS電晶體701的通道區域601係 形成在源極區域20 1與汲極區域202之間，由多晶矽膜等 等所構成的閘極電極5 3 1係經由由矽氧化物膜等等所構成 的閘極絕緣膜4 0 1而被形成於通道區域6 2 1的上方。注意 ，爲了簡單起見，僅例舉出內部元件之Ν-型MOS電晶體 -13- 200915535 701。然而，在真正的1C中，形成半導體裝置之許多個元 件（諸如，P-型MOS電晶體）被形成。 接著，比較ESD保護用N-型MOS電晶體721和內部 元件的N-型MOS電晶體701而敘述本發明之特性。 ESD保護用N-型MOS電晶體721之通道區域621的 P-型雜質濃度被設定而比內部元件的N-型MOS電晶體 701之通道區域601的P-型雜質濃度更高，藉此，ESD保 護用N-型MOS電晶體721之臨界電壓被設定而比內部元 件的N-型MOS電晶體701之臨界電壓更高。 ESD保護用N-型MOS電晶體721係與形成諸如邏輯 電路之內部電路的Μ Ο S電晶體（包含內部元件之N -型 MOS電晶體701 )不同，且需要使由靜電所引起之大量的 電流同時流動到末端，因而，電晶體寬度（W )被設定爲 和幾百微米一樣大。在此，因爲ESD保護用Ν-型MOS電 晶體721之臨界電壓被設定而比內部元件的Ν-型MOS電 晶體70 1之臨界電壓更高，所以在待命備用期間之關閉狀 態漏電流能夠被做得小，且整個1C之待命備用期間的電 流耗損（具有ESD保護用Ν-型MOS電晶體721安裝於其 上）能夠被減小。 在此，ESD保護用Ν-型MOS電晶體721之通道區域 621的Ρ-型雜質係由Ρ-型矽基板101之Ρ-型雜質所構成 的（或者，當Ρ-型井區域被形成且ESD保護用Ν-型MOS 電晶體721被形成於其中時，Ρ-型井區域之Ρ-型雜質（未 顯示出））、用以調整內部元件之Ν-型MOS電晶體701 -14- 200915535 之通道區域6 0 1之濃度的P -型雜質、及用以調整在內部 電路區域中所形成之其他MOS電晶體之通道濃度的P-型 雜質（舉例來說，P-型MOS電晶體、空乏N-型電晶體、 或具有不同臨界値之N-型或P-型MOS電晶體）。換言之 ，相較於在內部元件之N-型MOS電晶體701的通道區域 601中，較大量的P-型雜質被導入於ESD保護用N-型 MOS電晶體721之通道區域621中。 這使其可能將ESD保護用N-型MOS電晶體721之臨 界電壓設定得比內部元件之N-型MOS電晶體701的臨界 電壓更高，且因此，ESD保護用N-型MOS電晶體721之 次臨界電流被做得小，且漏電流能夠被做得小。 這樣，能夠獲得到具有ESD保護用N-型MOS電晶體 的半導體裝置，其使得關閉狀態漏電流小，而同時令人滿 意地實施E S D保護功能，但不會增加製程步驟和佔據面 積。 依據此實施例，利用MOS電晶體之通道區域濃度的 差異來改變臨界電壓，其可以和第一實施例及第二實施例 結合來加以實施。在下面所述之第四實施例及第五實施例 中，也利用MOS電晶體之通道區域濃度的差異來改變臨 界電壓。 (第四實施例） 圖4爲例舉依據本發明第四實施例之半導體裝置的 ESD保護用N-型MOS電晶體、內部元件用N-型MOS電 -15- 200915535 晶體、和內部元件用P-型MOS電晶體的示意剖面視圖。 ESD保護用N-型MOS電晶體721之通道區域621的 P-型雜質濃度被設定而比內部元件的N-型MOS電晶體 701之通道區域601的P-型雜質濃度更高，藉此，ESD保 護用N-型MOS電晶體721之臨界電壓被設定而比內部元 件的N-型MOS電晶體701之臨界電壓更高。此外，ESD 保護用N-型MOS電晶體721和內部元件的N-型MOS電 晶體70 1之閘極電極係由P-型多晶矽所構成，而同時內 部元件的P-型MOS電晶體71 1之閘極電極係由N-型多晶 矽所構成，這和圖2中所例舉之同極閘極電晶體的情況相 反。這是爲了藉由形成N-型MOS電晶體之通道和P-型 MOS電晶體之通道兩者離開矽基板表面側以改善驅動力 (電流驅動能力）、避免矽表面之結晶性的不便、及形通 道於產生較少缺陷的內部區域中之目的。 依據本發明，內部元件用N-型MOS電晶體之P-型閘 極電極5 02及ESD保護用N-型MOS電晶體之P-型閘極 電極5 22係由P-型多晶矽膜所構成的。 這使其可能獲得具有高電流驅動能力之半導體裝置， 其使得在第三實施例中所述之關閉狀態漏電流小，而同時 令人滿意地實施爲ESD保護用N-型MOS電晶體721所需 之對抗靜電的保護功能，但不會增加製程步驟和佔據面積 〇 有關其他組件，相同的數字被用來指示圖1中所例舉 之相似或相同的組件，且其說明被省略。 -16- 200915535 (第五實施例） 圖5爲例舉依據本發明第五實施例之半導體裝置的 ESD保護用N-型MOS電晶體、內部元件用N-型MOS電 晶體、和內部元件用P-型MOS電晶體的示意剖面視圖。 ESD保護用N-型MOS電晶體721之通道區域621的 P-型雜質濃度被設定而比內部元件的N-型MOS電晶體 701之通道區域601的P-型雜質濃度更高，藉此，ESD保 護用N-型MOS電晶體721之臨界電壓被設定而比內部元 件的N -型Μ Ο S電晶體7 0 1之臨界電壓更高。此外，E S D 保護用Ν-型MOS電晶體721和內部元件的Ν-型MOS電 晶體7 0 1及7 1 1之閘極電極係由Ρ -型多晶矽所構成。這 是爲了藉由形成Ν-型MOS電晶體之通道離開矽基板表面 側以改善驅動力（電流驅動能力）、避免矽表面之結晶性 的不便、及形通道於產生較少缺陷的內部區域中之目的。 除此之外，Ρ-型MOS電晶體之通道係形成於矽基板表面 之側上，且因此，漏電流能夠被做得小。 依據本發明，內部元件用Ν-型MOS電晶體之Ρ-型閘 極電極5 02、內部元件用Ρ-型MOS電晶體之Ρ-型閘極電 極5 12、及ESD保護用Ν-型MOS電晶體之Ρ-型閘極電極 522係由相同之Ρ-型多晶矽膜所構成的。 這使其可能獲得一半導體裝置，其使得在第一實施例 中所述之關閉狀態漏電流小，而同時令人滿意地實施爲 ESD保護用Ν-型MOS電晶體721所需之對抗靜電的保護 -17 - 200915535 功能、給予內部元件的N-型MOS電晶體701高電流驅動 能力，並使得內部元件之P-型MOS電晶體71 1的漏電流 小，但不會增加製程步驟和佔據面積。 有關其他組件，相同的數字被用來指示圖1中所例舉 之相似或相同的組件，且其說明被省略。 【圖式簡單說明】 在附圖中： 圖1係例舉依據本發明第一實施例之半導體裝置的 ESD保護用N-型MOS電晶體、內部元件用N-型MOS電 晶體、和內部元件用P-型MOS電晶體的示意剖面視圖； 圖2係例舉依據本發明第二實施例之半導體裝置的 ESD保護用N-型MOS電晶體、內部元件用N-型MOS電 晶體、和內部元件用P-型MOS電晶體的示意剖面視圖； 圖3係例舉依據本發明第三實施例之半導體裝置的 ESD保護用N-型MOS電晶體、內部元件用N-型MOS電 晶體、和內部元件用P-型MOS電晶體的示意剖面視圖； 圖4係例舉依據本發明第四實施例之半導體裝置的 ESD保護用N-型MOS電晶體、內部元件用N-型MOS電 晶體、和內部元件用P-型MOS電晶體的示意剖面視圖； 圖5係例舉依據本發明第五實施例之半導體裝置的 ESD保護用N-型MOS電晶體、內部元件用N-型MOS電 晶體、和內部元件用P-型MOS電晶體的示意剖面視圖； 以及 -18 - 200915535 ESD保護用N- 電晶體、和內部 圖6係例舉依據習知之半導體裝置的 型MOS電晶體、內部元件用N-型MOS 元件用P-型MOS電晶體的示意剖面視圖。 【主要元件符號說明】 1 0 1 : P -型矽基板 2 2 1 :源極區域 2 2 2 ·汲極區域 3 0 1 :元件隔離區域 4 2 1 :閘極絕緣膜 5 22 : P-型閘極電極 6 2 1 :通道區域 721 : N -型MOS電晶體 701 : N -型MOS電晶體 711 : P -型MOS電晶體 2 0 1 :源極區域 2 0 2 :汲極區域 6 0 1 通道區域 5 0 1 : N -型閘極電極 4 0 1 :閘極絕緣膜 2 1 1 :源極區域 2 1 2 :汲極區域 1 1 1 N -井區域 6 1 1 ·通道區域 -19- 200915535 5 11 · N -型間極電極 4 1 1 :閘極絕緣膜 512 : P-型閘極電極 5 3 2 :閘極電極 5 3 1 :閘極電極 5 0 2 : P -型閘極電極 5 2 1 :閘極電極The P-type gate electrode 5 of the N-type MOS transistor for ESD protection is between the source region 221 of the N-type MOS transistor for ESD protection and the drain region 222 of the N-type MOS transistor for ESD protection. 22 is formed over the channel region 621 via the gate insulating film 421, P-type gate electrode 522 is formed of a P-type polysilicon film, and the gate insulating film 421 is made of a tantalum oxide film. Wait for it to be formed. Note that the source region 22 1 is electrically connected so as to have the same ground potential (Vss ) as the ground potential (Vss ) (not shown) of the P-type gate electrode 522 of the N-type MOS transistor for ESD protection, This keeps the ESD protection N-type MOS transistor 72 1 in a closed state, which is a so-called off state of the off-cell. Further, the drain region 222 is connected to an external connection terminal. Note that, for the sake of simplicity, in the example of FIG. 1, only the N-type MOS transistor 721 for ESD protection having a source region 221 and ESD of a pair of N-type MOS transistors for ESD protection is exemplified. The drain regions 222 of the protective N-type MOS transistors are composed of N-type heavily doped impurity regions. However, since a true ESD protection type MOS transistor requires a large transistor width in order to flow a large amount of current caused by static electricity, a true ESD protection N-type M〇S transistor is often formed to have Many source areas and bungee areas. Next, the N-type MOS transistor 701 of the internal element and the P-type Μ 0 S transistor 7 1 1 of the internal element will be described. First, the Ν-type MOS transistor 701 with respect to the internal components, the source region 201 of the Ν-type MOS transistor for the pair of internal components, and the drain region 02 of the 元件-type MOS transistor for the internal component (the system) The impurity region composed of the Ν-type heavily 200915535 is formed on the P − -type germanium substrate 101 as the semiconductor substrate of the first conductivity type, and the source region 2 0 1 and the drain region 202 are The element isolation region 301 formed therebetween by shallow trench isolation or LOCOS method is electrically isolated from other components. The channel region 601 of the N-type MOS transistor for internal components is formed between the source region 201 of the N-type MOS transistor for internal components and the drain region 202 of the N-type MOS transistor for internal components, internal components The N-type gate electrode 501 of the N-type MOS transistor is formed over the channel region 601 via the gate insulating film 401, and the N-type gate electrode 501 is formed of an N-type polysilicon film. And the gate insulating film 40 1 is formed of a tantalum oxide film or the like. Next, a P-type MOS transistor 71 for internal components, a source region 21 1 for a pair of internal components for a P-type MOS transistor, and a drain region 212 for a P-type MOS transistor for an internal component (which It is formed of a P-type heavily doped impurity region) formed on the N-well region 11 1 of the P-type germanium substrate 101 as the semiconductor substrate of the first conductivity type, and the source region 2 11 The drain region 2 1 2 is electrically isolated from other components by an element isolation region 301 formed therebetween by shallow trench isolation or LOCOS method. The channel region 61 1 of the P-type MOS transistor for internal components is formed in the source region 21 1 of the P-type MOS transistor for internal components and the drain region 2 1 of the P-type Μ 0 S transistor for internal components. Between the two, the internal element is used for the Ρ-type Μ 0 S transistor, and the Ν-type gate electrode 5 1 1 is formed over the channel region 611 via the gate insulating film 411, and the Ν-type gate electrode 51 1 -9-200915535 is formed of an N-type polysilicon film, and the gate insulating film 411 is formed of a tantalum oxide film or the like. Next, the characteristics of the present invention will be described by comparing the ESD protection type MOS transistor 721, the N-type MOS transistor 701 of the internal element, and the P-type MOS transistor 7 1 1 of the internal element. In the N-type MOS transistor 721 for ESD protection, the P-type gate electrode 522 of the N-type MOS transistor for ESD protection is composed of P-type polysilicon, and therefore, because of the P-type polysilicon The difference in work function between the P-type germanium substrate 101 of the channel region 621 forming the N-type MOS transistor for ESD protection is compared with the reverse voltage of the N-type MOS transistor 701 of the internal device. A higher reverse voltage is required. In other words, the N-type MOS transistor 721 for ESD protection has a higher threshold voltage than the threshold voltage of the N-type MOS transistor 701 for internal components, and therefore, the case where the gate potential is fixed to 〇V (Vss) The off-state leakage current can be suppressed to a low level. The N-type MOS transistor 721 for ESD protection is different from the MOS transistor (including the N-type MOS transistor 701 for internal components) which forms an internal circuit such as a logic circuit, and must have a large amount of current caused by static electricity. Sudden flow, and thus, the transistor width (W) is set to be as large as several hundred micrometers. Therefore, the suppression of the off-state leakage current of the N-type MOS transistor 72 for ESD protection is reduced by the current consumption during the standby standby period of the entire semiconductor device (with the N-type MOS transistor 721 for ESD protection mounted thereon). The aspect is highly effective. According to the present invention, since the-10-200915535 P-type gate electrode 522 of the N-type MOS transistor for ESD protection is composed of P-type polysilicon, the N-type NMOS transistor for ESD protection is 7 2 1 has a higher threshold voltage than the threshold voltage of the N-type Μ 0 S transistor (having a gate electrode composed of Ν-type polysilicon) than the internal component, and therefore, the gate potential is fixed at 0 V ( The off-state leakage current in the case of V ss ) can be effectively made small. This makes it possible to reduce the current consumption during the standby period of the entire semiconductor device (on which the N-type MOS transistor 721 for ESD protection with a large W is mounted). (Second Embodiment) Fig. 2 is a view showing an N-type MOS transistor for ESD protection, an N-type MOS transistor for internal components, and a P-type MOS for internal components of a semiconductor device according to a second embodiment of the present invention. A schematic cross-sectional view of a transistor. This embodiment differs from the first embodiment exemplified in Fig. 1 in that the gate electrode of the P-type MOS transistor 71 1 of the internal device is constituted by a P-type polysilicon film. In Fig. 2, this is exemplified as a P-type gate electrode 512 of a P-type MOS transistor for internal components. In the example illustrated in FIG. 2, the gate electrode of the N-type Μ 电 S transistor 70 1 of the internal device is composed of a Ν-type polysilicon film, and the 元件-type MOS transistor 71 1 of the internal device. The gate electrode is composed of a Ρ-type polycrystalline sand film, which is commonly referred to as a homopolar smectic transistor. In particular, this is often used as a technique for making low voltage operation of a semiconductor device possible by forming a channel of a P-type MOS transistor on the surface side of the germanium substrate and making the leakage current small. -11 - 200915535 According to the present invention, the P-type gate electrode 512 of the P-type Μ OS transistor for internal components and the P-type gate electrode 522 of the N-type MOS transistor for ESD protection are the same p - A polycrystalline tantalum film. This makes it possible to obtain a semiconductor device having the same gate, which makes the off-state leakage current described in the first embodiment small, while being satisfactorily implemented as an N-type MOS transistor for ESD protection 721. The anti-static protection required, and can operate at low voltages without increasing process steps and footprint. Regarding other components, the same numerals are used to indicate similar or identical components exemplified in Fig. 1, and the description thereof is omitted. (Third Embodiment) Fig. 3 is a view showing an N-type MOS transistor for ESD protection, an N-type MOS transistor for internal components, and a P-type 内部 for internal components of a semiconductor device according to a third embodiment of the present invention.示意 S schematic cross-sectional view of the transistor. First, the Ν-type MOS transistor 721 for ESD protection will be described. The source region 221 and the drain region 222 composed of the heavily doped impurity regions are formed on the Ρ-type germanium substrate 1 〇1 as the semiconductor substrate of the first conductivity type, the source The region 2 2 1 and the drain region 2 2 2 are electrically isolated from other components by the element isolation region 301 formed therebetween by shallow trench isolation or L Ο C Ο S method. The channel region 621 of the SD-type MOS transistor 721 for ESD protection is formed between the source region 2 2 1 and the drain region 2 2 2, and the gate electrode 5 3 2 composed of a polycrystalline silicon film or the like It is formed above the channel region 62 1 via a gate insulating film 42 1 of -12-200915535 which is composed of a tantalum oxide film or the like. Note that the source region 2 2 1 is electrically connected so as to have the same ground potential (Vss ) as the ground potential (Vss ) (not shown) of the gate electrode 523, which makes the N-type ES for ESD protection. The S transistor 7 2 1 is kept in a closed state, which is a so-called off state of the off-cell. Further, the drain region 222 is connected to the external connection terminal. Note that, for the sake of simplicity, in the example of FIG. 3, only the NMOS-type MOS transistor for ESD protection is exemplified, which has a pair of source regions 22 composed of erbium-type heavily doped impurity regions. 1 and the bungee region 222. However, true ESD protection uses a 电-type MOS transistor that requires a large dielectric width to allow a large amount of current caused by static electricity to flow. Therefore, true ESD protection Ν-type MOS transistors are often formed with many source regions and drain regions. Next, the Ν-type Ο 电 S transistor 7 〇 1 of the internal element will be described. The source region 20 1 and the drain region 202 composed of the Ν-type heavily doped impurity regions are formed on the Ρ-type 矽 substrate 1 〇1 as the semiconductor substrate of the first conductivity type, the source The pole region 2 0 1 and the drain region 2 0 2 are electrically isolated from other components by the element isolation region 310 formed therebetween by shallow trench isolation or L Ο C Ο S method. The channel region 601 of the internal device-type MOS transistor 701 is formed between the source region 20 1 and the drain region 202, and the gate electrode 53 formed by the polysilicon film or the like is via the tantalum oxide. A gate insulating film 401 composed of a film or the like is formed over the channel region 623. Note that, for the sake of simplicity, only the internal-element Ν-type MOS transistor -13-200915535 701 is exemplified. However, in the real 1C, many elements forming a semiconductor device such as a P-type MOS transistor are formed. Next, the characteristics of the present invention will be described by comparing the N-type MOS transistor 721 for ESD protection with the N-type MOS transistor 701 of the internal element. The P-type impurity concentration of the channel region 621 of the N-type MOS transistor 721 for ESD protection is set to be higher than the P-type impurity concentration of the channel region 601 of the N-type MOS transistor 701 of the internal device, whereby The threshold voltage of the N-type MOS transistor 721 for ESD protection is set to be higher than the threshold voltage of the N-type MOS transistor 701 of the internal element. The N-type MOS transistor 721 for ESD protection is different from the Μ S transistor (the N-type MOS transistor 701 including internal components) which forms an internal circuit such as a logic circuit, and requires a large amount of static electricity. The current flows to the end at the same time, and thus, the transistor width (W) is set to be as large as several hundred micrometers. Here, since the threshold voltage of the D-type MOS transistor 721 for ESD protection is set higher than the threshold voltage of the Ν-type MOS transistor 70 1 of the internal element, the off-state leakage current during the standby period can be It is made small, and the current consumption during the standby standby period of 1C (with the ESD protection Ν-type MOS transistor 721 mounted thereon) can be reduced. Here, the Ρ-type impurity of the channel region 621 of the Ν-type MOS transistor 721 for ESD protection is composed of Ρ-type impurities of the Ρ-type 矽 substrate 101 (or when a Ρ-type well region is formed and When a SD-type MOS transistor 721 for ESD protection is formed therein, a Ρ-type impurity (not shown) of a Ρ-type well region, and a Ν-type MOS transistor for adjusting an internal component 701 -14 - 200915535 a P-type impurity having a concentration of the channel region 610, and a P-type impurity for adjusting a channel concentration of other MOS transistors formed in the internal circuit region (for example, a P-type MOS transistor, Depleted N-type transistors, or N-type or P-type MOS transistors with different critical enthalpies). In other words, a larger amount of P-type impurities are introduced into the channel region 621 of the N-type MOS transistor 721 for ESD protection than in the channel region 601 of the N-type MOS transistor 701 of the internal device. This makes it possible to set the threshold voltage of the N-type MOS transistor 721 for ESD protection higher than the threshold voltage of the N-type MOS transistor 701 of the internal element, and therefore, the N-type MOS transistor 721 for ESD protection. The secondary critical current is made small and the leakage current can be made small. Thus, a semiconductor device having an N-type MOS transistor for ESD protection can be obtained which makes the off-state leakage current small while at the same time satisfactorily implementing the E S D protection function without increasing the process steps and the occupied area. According to this embodiment, the threshold voltage is changed by the difference in the channel region concentration of the MOS transistor, which can be implemented in combination with the first embodiment and the second embodiment. In the fourth embodiment and the fifth embodiment described below, the boundary voltage is also changed by the difference in the channel region concentration of the MOS transistor. (Fourth Embodiment) FIG. 4 is a view showing an N-type MOS transistor for ESD protection, an N-type MOS electric -15-200915535 crystal for internal components, and an internal component for a semiconductor device according to a fourth embodiment of the present invention. A schematic cross-sectional view of a P-type MOS transistor. The P-type impurity concentration of the channel region 621 of the N-type MOS transistor 721 for ESD protection is set to be higher than the P-type impurity concentration of the channel region 601 of the N-type MOS transistor 701 of the internal device, whereby The threshold voltage of the N-type MOS transistor 721 for ESD protection is set to be higher than the threshold voltage of the N-type MOS transistor 701 of the internal element. Further, the gate electrode of the N-type MOS transistor 721 for ESD protection and the N-type MOS transistor 70 1 of the internal element is composed of a P-type polysilicon, and the P-type MOS transistor 71 1 of the internal element at the same time. The gate electrode is composed of N-type polysilicon, which is the opposite of the case of the same gate transistor as exemplified in FIG. This is to improve the driving force (current driving capability) by both the channel forming the N-type MOS transistor and the channel of the P-type MOS transistor to improve the driving force (current driving capability), and to avoid the inconvenience of crystallinity of the surface of the crucible, and The purpose of a shaped channel in an interior region that produces fewer defects. According to the present invention, the P-type gate electrode 502 of the N-type MOS transistor for internal components and the P-type gate electrode 522 of the N-type MOS transistor for ESD protection are composed of a P-type polysilicon film. of. This makes it possible to obtain a semiconductor device having a high current driving capability, which makes the off-state leakage current described in the third embodiment small, while being satisfactorily implemented as an N-type protection N-type MOS transistor 721 The anti-static protection function is required, but does not increase the process steps and the occupied area. Other components are used, and the same numerals are used to indicate similar or identical components exemplified in FIG. 1, and the description thereof is omitted. -16-200915535 (Fifth Embodiment) FIG. 5 is a view showing an N-type MOS transistor for ESD protection, an N-type MOS transistor for internal components, and an internal component for a semiconductor device according to a fifth embodiment of the present invention. A schematic cross-sectional view of a P-type MOS transistor. The P-type impurity concentration of the channel region 621 of the N-type MOS transistor 721 for ESD protection is set to be higher than the P-type impurity concentration of the channel region 601 of the N-type MOS transistor 701 of the internal device, whereby The threshold voltage of the N-type MOS transistor 721 for ESD protection is set to be higher than the threshold voltage of the N-type Μ S transistor 70 1 of the internal device. Further, the gate electrode of the S-type MOS transistor 721 for protection of the E S D and the Ν-type MOS transistors 70 1 and 711 of the internal element is composed of Ρ-type polysilicon. This is to improve the driving force (current driving capability) by the channel forming the Ν-type MOS transistor, to improve the driving force (current driving capability), to avoid the inconvenience of crystallinity of the ruthenium surface, and to form a channel in an internal region where fewer defects are generated. The purpose. In addition to this, the channel of the Ρ-type MOS transistor is formed on the side of the surface of the ruthenium substrate, and therefore, the leak current can be made small. According to the present invention, the 元件-type gate electrode 502 of the Ν-type MOS transistor for internal components, the Ρ-type gate electrode 5 12 of the Ρ-type MOS transistor for internal components, and the Ν-type MOS for ESD protection The germanium-type gate electrode 522 of the transistor is composed of the same germanium-type polysilicon film. This makes it possible to obtain a semiconductor device which makes the off-state leakage current described in the first embodiment small, while at the same time satisfactorily implemented as antistatic for the ESD protection Ν-type MOS transistor 721. Protection -17 - 200915535 function, N-type MOS transistor 701 giving internal components high current drive capability, and making the leakage current of the internal component P-type MOS transistor 71 1 small, but does not increase the process steps and occupied area . Regarding other components, the same numerals are used to indicate similar or identical components exemplified in Fig. 1, and the description thereof is omitted. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing an N-type MOS transistor for ESD protection, an N-type MOS transistor for internal components, and an internal component of a semiconductor device according to a first embodiment of the present invention. A schematic cross-sectional view of a P-type MOS transistor; FIG. 2 is an N-type MOS transistor for ESD protection, an N-type MOS transistor for internal components, and an internal portion of a semiconductor device according to a second embodiment of the present invention; FIG. 3 is a schematic cross-sectional view showing a P-type MOS transistor for a device; FIG. 3 is an N-type MOS transistor for ESD protection, an N-type MOS transistor for internal components, and a semiconductor device according to a third embodiment of the present invention; FIG. 4 is a schematic cross-sectional view showing a P-type MOS transistor for an internal component; FIG. 4 is an N-type MOS transistor for ESD protection, an N-type MOS transistor for an internal component, and a semiconductor device according to a fourth embodiment of the present invention; And a schematic cross-sectional view of a P-type MOS transistor for internal components; and FIG. 5 is an N-type MOS transistor for ESD protection of a semiconductor device according to a fifth embodiment of the present invention, and an N-type MOS transistor for internal components. Schematic cross-section of a P-type MOS transistor with internal components And -18 - 200915535 N-protective N-transistor, and internal Figure 6 is a schematic cross-section of a MOS transistor according to a conventional semiconductor device and a P-type MOS transistor for an N-type MOS device for internal components. view. [Description of main component symbols] 1 0 1 : P - type germanium substrate 2 2 1 : source region 2 2 2 · drain region 3 0 1 : element isolation region 4 2 1 : gate insulating film 5 22 : P-type Gate electrode 6 2 1 : channel region 721 : N - type MOS transistor 701 : N - type MOS transistor 711 : P - type MOS transistor 2 0 1 : source region 2 0 2 : drain region 6 0 1 Channel region 5 0 1 : N -type gate electrode 4 0 1 : gate insulating film 2 1 1 : source region 2 1 2 : drain region 1 1 1 N - well region 6 1 1 · channel region -19- 200915535 5 11 · N-type interpole electrode 4 1 1 : Gate insulating film 512 : P-type gate electrode 5 3 2 : Gate electrode 5 3 1 : Gate electrode 5 0 2 : P - type gate electrode 5 2 1 : Gate electrode