200812061 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一·種積體電路（integrated circuit， ic)設計，特別是有關於一種靜電放電（electr〇static discharge，ESD)保護電路的佈局（lay〇ut)設計。 【先前技術】 在積體電路中，容易受到靜電放電的影響而損壞金 氧半導體（ metal oxide semicbnductor，MOS )元件的閘極 氧化物。藉由接觸只有高於積體電路供應電壓些許伏特 的電壓，就可能破壞閘極氧化物。來自一般環境來源的 靜電電壓可輕易達到數千伏特，或是甚至達到數萬伏 特。雖然電荷以及所產生的任何電流是非常地小，靜電 電壓還是具有破壞性。因此，在靜電電荷損壞積體電路 之前’為了釋放任何的靜電電荷，積體電路中靜電放電 保護電路通常與其他核心電路一起被使用。 在低壓、高速應用方面，絕緣物上覆石夕（silicon on insulator, SOI)技術變得越來越普遍。因為絕緣物上覆矽 技術之優點多於傳導矽晶圓（bulk silicon)技術之優點， 例如：具有對閉鎖（latch up )的免疫性以及較小的接面 電容。在絕緣物上覆矽技術的使用上，二極體為傳統的 靜電放電保護元件。由於具有低觸發電壓、低導通電阻 以及焉靜電放電耐受能力（ESD robustness )，在晶.片内 靜電放電保護方面’ 一極體為有效的元件之一。然而， 0503-A32625TWF/NikeyChen 5 200812061 單獨使用傳統的二極體係無法提供足夠的保護來對抗靜 電放電電荷。 另一^種傳統元件’常作為靜電放電保護以對抗靜電 放電電荷'，係為使用絕緣物上覆矽技術所製造的閑桎接 地 N 型金氧半導體（grounded gate NMOS，GGNMOS)馬200812061 IX. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit (IC) design, and more particularly to an electrostatic discharge (ESD) protection circuit Layout (lay〇ut) design. [Prior Art] In an integrated circuit, it is susceptible to damage of a gate oxide of a metal oxide semiconductor (CMOS) device due to electrostatic discharge. The gate oxide can be destroyed by contacting a voltage that is only a few volts above the supply voltage of the integrated circuit. Electrostatic voltages from general environmental sources can easily reach thousands of volts, or even tens of thousands of volts. Although the charge and any current generated is very small, the electrostatic voltage is destructive. Therefore, in order to discharge any electrostatic charge before the electrostatic charge damages the integrated circuit, the electrostatic discharge protection circuit in the integrated circuit is usually used together with other core circuits. In low-voltage, high-speed applications, silicon-on-insulator (SOI) technology is becoming more common. Because the overfill technology of the insulator has advantages over the advantages of the bulk silicon technology, for example, it has immunity to latch up and a small junction capacitance. In the use of the overlying technology of the insulator, the diode is a conventional electrostatic discharge protection element. Due to its low trigger voltage, low on-resistance, and ESD robustness, it is one of the most effective components in the field of electrostatic discharge protection. However, 0503-A32625TWF/NikeyChen 5 200812061 The use of a conventional two-pole system alone does not provide sufficient protection against electrostatic discharge charges. Another conventional element, 'usually used as an electrostatic discharge protection against electrostatic discharge charge', is a grounded gate NMOS (GGNMOS) horse fabricated using an insulator overlying technique.
件。閘極接地N型金氧半導體元件的特徵為具有連接至... 接地端的多晶梦（poly silicon )閘極層。然而，閘極接地 N型金氧半導體无件卻無法提供足夠的靜電放電保護來 對抗負靜電放電電荷V 因此’絕緣物上覆梦技術的靜電放電保護電路需要 可提供足夠保護之靜電放電保護電路的佈局結構’用以 對抗正、負兩靜電放電電荷。 【發明内容】 · 有鑑於此，本發明提供一種靜電放電保護電路的佈 局結構，包括一第一金氧半導體元件區域，具有一第一 摻雜區以及一第二摻雜區，上述第一、第二摻雜區具有 相同的極性，並配置於一第一導電閘極層的兩侧;以及 一第三掺雜區，沿著上述第一摻雜區配置，並位於上述 第一導電閘極層的一侧，其中上述第三摻雜區具有不同 於上述第一、第二摻雜區的極性，使得上述第三摻雜區 以及上述第二掺雜區形成一二極體，在負靜電放電事件 中5上述二極體用以提南靜電放電電流的消除能力。 在本發明另一實施例中，靜電放電保護電路的佈局 0503-A32625TWF/NikeyChen 6 200812061 結，包括一第一 N型金氧半導體元件區域，具有配置於 ’ 一第一導電閘極層之兩側的一 N型源極區以及一 N型汲 厂極區；以及―P型摻職，沿著型源極區配置: .，並位於上述第-導電閘極層的一爾，:使得上述p型推雜 區以及上述N型汲極區形成一二極體.，在負靜電放 件中上述二極體用以提高靜電放電電流的消除能力， 其中上迷第-金氧半導體元件區域以及上述p型接雜區 製造於-半導體層上，上述半導體層藉由—隔離層盘— > 半導體基體分隔。 在本發明又—實施射，靜電放㈣護電路的怖局 結才f包括―第―N型金氧半導體元件區域，具有配置於 一第一導電閘極層之兩側的一第一 N型源極區以及一第 型汲極區；-P型摻雜區，沿著上述第—n型源極 區配置，並位於上述第一導電閘極層的一侧，使得上述p 型推雜！以及上述第一 N型汲極區形成一第一二極體； .^及第一金氧半導體元件區域，具有相鄰於上述第一 N =源極區的第一導電閘極層，以及相鄰於上述第二導 书閘極層亚位於上述第一 N型源極區之相反侧的一第二 N型/及極區，使得上述第二N型汲極區以及上述p型摻 雜區形成一第二二極體。 ^ 【實施方式】 明麵ίΐ本發明之上述和其他目的、特徵、和優點能更 絲、f重’下文特舉出較佳實施例，並配合所附圖式， 〇5〇3-A32625TWF/NikeyChen 7 200812061 作詳細說明如下： - 實施例： v - 第1圖係：顧示使用絕緣物上覆矽技術所製造的傳統 二極體之佈局結構:1Q0。:佈局結構100内的各二極體是由 N+型摻雜區以及P+型掺雜區彼此之間的接面所組成。例 如，二極體102包'括_於^+型摻雜區106以及P+型摻雜 區108上方的多晶矽層104,而另一二極體110包括位於 N+型摻雜區114 '以及P+型摻雜區108上方的多晶矽層 • 112。 由於具有低觸發電壓、低導通電阻以及高靜電放電 耐受能力，傳統上使用這些二極體作為晶片内的靜電放 電保護。然而，在沒有其他元件的情況下，單獨使用這 些傳統二極體作為靜電放電保護’係無法提供足夠的保 護來對抗靜電放電電荷。 第2圖係顯示使用絕緣物上覆矽技術所製造的傳統 T型閘極閘極接地N型金氧半導體元件的佈局結構200。 佈局結構200内的各傳統T型閘極電晶體包括多晶矽層 202，以及形成於多晶石夕層202兩侧的N+型源極（source, S) /汲極（drain，D)區204。多晶矽層202具有1[型結 構。P+型摻雜區208為佈植於N+型源極/汲極區204下 方之井區的井區接觸（well contact)。 單獨使用T型閘極閘極接地N型金氧半導體元件作 為靜電放電保護係無法提供南效率的保護來對抗負靜電 放電電何。因此’需要一種更佳能保護核心電路的靜電 0503-A32625TWF/NikeyChen 8 200812061 放電保護電路以對抗負靜電放電電荷。 一第3圖係頦不根據本發明一實施例之靜電放黨保護 、元件的佈局結構3GG。佈局結構3⑽包括一些N型金氧 半導體:元雜域’各N型金氧半導體元件轉姉導電 閘極層302 ,以及配置於導電閘極層3〇2兩侧的源極/汲 極區304。導電閘:極層3〇2可由金屬、多晶梦以及多晶砍 化孟屬（polycide)等材料所製成。源極/没極區3 係將 N 1_亦隹貝重4亦隹到p型半導.體基體中的導電閑極層逝 下方所製造而成。位於導電閘極層3〇2下方且介於源極/ 及極區304之間的區域係定義為通道區，當通道區導通 ^•’具有& H如热知此技藝者所了解，通道區的推 雜密度低於源極/汲極區304的摻雜密度。 P型摻雜區306沿著源極區綱配置，並與源極區 304同位於各N型半導體之導電閑極層3〇2白勺一侧。？型 摻雜區306、導電閘極層302的邊緣為部分重疊，用以改 #善彼此之間的導電性叶型摻雜區306可延伸超過源極區 304的範圍。雖然第3圖_示p型掺雜區施位於源極 區3〇4的上面，’然而P型捧雜區306亦可配置在源極區 3 04的下面’或是上下兩面。阳址、 既然P型摻雜區306與汲極 區304的極性是不同的，1>型換雜區3〇6與没極區3〇4 可在N型金氧半⑽元件一中形成二極體，而不需要 佔用額外的空間。 如第3圖所顯示，各金氣半導體元件區域具有配置 在佈局結構300内的導電閘植層302以及源極（S ) /没極 0503-A32625TWF/NikeyChen 9 200812061 (D)區304。在本發明一實施例中，？型摻雜區3〇6配 置於兩鄰近的導電閘極層；302之間，並與上述兩鄰近之 導電閘極層302的邊緣重疊。型摻雜區306可往右邊越 過導電閘極層302而與汲極區含0_形成一個二極體，以 及往左邊越過另一導電閘極層'3〇之而與汲極區304形成 另一個二極體。 - 金氧半導體元件區域（包括導電閘極層302以及源 極/汲極區304)以及Ρ型摻雜區.306係製造於半導體層, 上’半導體層藉由隔離層與半導體基體分隔。此稱為絕 緣物上覆石夕結構。Ρ型摻雜區306的摻雜密度高於位在導 電閘極層302下方之通道區的摻雜密度。例如，ρ型推雜 區306的接雜密度可大體上相同於源極/汲極區的摻 雜密度。Ρ型摻雜區306之摻雜密度的範圍大約在le6 cm 3與le24 cm-3之間。可以了解到增加ρ型摻雜區3㈨ 的尺寸以及掺雜密度，將導致流經過由ρ型摻雜區3〇6 與汲極區304所組成之二極體的電流也會跟著增加。 導電閘極層302、源極區304以及ρ型摻雜區3〇6 耦接至接地端，而汲極區3〇4耦接至輸入/輸出接合墊。 上述結構可由第4圖中示意圖400所顯示。N型金氧半 導體電晶體402係表示金氧半導體元件區域的電子符 號，如前文所描述，耦接於接合墊4〇4以及接地端:間 二極體406係表示第3圖中由P型摻雜區3〇6與汲極曰區 3〇4所組成之二極體的電子符號，亦耦接於接合墊以 及接地端之間，以及並聯於N型金氧半導體電晶體4⑽。 0503-A32625TWF/NikeyChen jq 200812061 核心電路408耦接於接合墊4〇4以 、 並聯於N型:金轉導體電Q 端之間’以及 金氧半導體電晶仙二極體權。隨 源極為於昼愈讥』 通兩為不¥通，因為其閘極以及_ 以及接地為之間I因此，在正常操作下，Ν划入"/… 體電晶體402以及二極體傷不會影、、^乳+導，Pieces. The gate grounded N-type MOS device is characterized by having a polysilicon gate layer connected to the ground terminal. However, the gate-grounded N-type MOS has no component but does not provide sufficient ESD protection against the negative ESD charge. Therefore, the ESD protection circuit of the Insulator Overlay Technology requires an ESD protection circuit that provides adequate protection. The layout structure 'is used to combat positive and negative electrostatic discharge charges. SUMMARY OF THE INVENTION In view of the above, the present invention provides a layout structure of an electrostatic discharge protection circuit, including a first MOS device region having a first doped region and a second doped region, the first The second doped regions have the same polarity and are disposed on both sides of a first conductive gate layer; and a third doped region disposed along the first doped region and located at the first conductive gate a side of the layer, wherein the third doped region has a polarity different from that of the first and second doped regions, such that the third doped region and the second doped region form a diode, and the negative static electricity In the discharge event, the above two diodes are used to eliminate the electrostatic discharge current of the South. In another embodiment of the present invention, the layout of the ESD protection circuit is 0503-A32625TWF/NikeyChen 6 200812061, and includes a first N-type MOS device region having two sides disposed on a first conductive gate layer. An N-type source region and an N-type 汲 factory pole region; and a "P-type adjunct, along the source region configuration: . and located in the first-first conductive gate layer, such that the above p The type of the dummy region and the N-type drain region form a diode. In the negative electrostatic discharge device, the diode is used to improve the electrostatic discharge current elimination capability, wherein the first-metal oxide semiconductor device region and the above The p-type junction region is fabricated on a --semiconductor layer separated by a spacer layer - > semiconductor substrate. In the present invention, the implementation of the radiation, electrostatic discharge (four) protection circuit includes a "N-type MOS device region, and has a first N-type disposed on both sides of a first conductive gate layer. a source region and a first type drain region; a P-type doped region disposed along the first n-type source region and located on one side of the first conductive gate layer, such that the p-type dopant is mixed! And the first N-type drain region forms a first diode; and the first MOS device region has a first conductive gate layer adjacent to the first N= source region, and a phase a second N-type/polar region adjacent to the second N-type source region of the second N-type source region, such that the second N-type drain region and the p-type doped region A second diode is formed. [Embodiment] The above and other objects, features, and advantages of the present invention will become more apparent and advantageous. hereinafter, the preferred embodiment will be described with reference to the accompanying drawings, 〇5〇3-A32625TWF/ Nikey Chen 7 200812061 is described in detail as follows: - Example: v - Fig. 1 is a layout structure of a conventional diode manufactured by using an overlying insulator technique: 1Q0. Each of the diodes in the layout structure 100 is composed of a junction between an N+ doped region and a P+ doped region. For example, the diode 102 includes a polysilicon layer 104 over the ^+ doped region 106 and the P+ doped region 108, and the other diode 110 includes an N+ doped region 114' and a P+ type. The polysilicon layer above the doped region 108 • 112. These diodes have traditionally been used as electrostatic discharge protection in wafers due to their low trigger voltage, low on-resistance, and high electrostatic discharge withstand capability. However, in the absence of other components, the use of these conventional diodes alone as an electrostatic discharge protection system does not provide sufficient protection against electrostatic discharge charges. Fig. 2 is a view showing a layout structure 200 of a conventional T-type gate gate grounded N-type MOS device fabricated using an overlying immersion technique. Each of the conventional T-type gate transistors within the layout structure 200 includes a polysilicon layer 202, and an N+ source (drain) region 204 formed on both sides of the polycrystalline layer 202. The polysilicon layer 202 has a 1 [type structure. The P+ doped region 208 is a well contact implanted in a well region below the N+ source/drain region 204. The use of a T-gate gate-grounded N-type MOS device alone as an ESD protection system does not provide protection against south efficiency against negative ESD. Therefore, it is necessary to have a better electrostatic protection 0503-A32625TWF/NikeyChen 8 200812061 discharge protection circuit against the negative electrostatic discharge charge. Fig. 3 is a diagram showing the layout of the electrostatic discharge party and the component 3GG according to an embodiment of the present invention. The layout structure 3 (10) includes some N-type MOS semiconductors: a meta-domain, each N-type MOS device switching conductive gate layer 302, and a source/drain region 304 disposed on both sides of the conductive gate layer 3〇2 . Conductive gate: The pole layer 3〇2 can be made of materials such as metal, polycrystalline dreams, and polycide. The source/no-polar region 3 system is manufactured by the N 1_ also the 重 重 重 4 隹 隹 p p p p p p p p 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The region located below the conductive gate layer 3〇2 and between the source/pole region 304 is defined as a channel region, and when the channel region is turned on, it has a & H, as known to those skilled in the art, the channel The doping density of the regions is lower than the doping density of the source/drain regions 304. The P-type doping region 306 is disposed along the source region and is located on the side of the conductive idle layer 3〇2 of each N-type semiconductor together with the source region 304. ? The edges of the doped region 306 and the conductive gate layer 302 are partially overlapped to improve the extent that the conductive doped regions 306 between each other can extend beyond the source region 304. Although Fig. 3 shows that the p-type doping region is applied over the source region 3〇4, the P-type doping region 306 may be disposed under the source region 308 or on both sides. The anode address, since the polarity of the P-doped region 306 and the drain region 304 are different, the 1>-type impurity-changing region 3〇6 and the non-polar region 3〇4 may form two in the N-type gold-oxygen half (10) element Polar body, without taking up extra space. As shown in Fig. 3, each of the gold gas semiconductor device regions has a conductive gate layer 302 and a source (S) / no pole 0503-A32625TWF/NikeyChen 9 200812061 (D) region 304 disposed in the layout structure 300. In an embodiment of the invention, The doped regions 3〇6 are disposed between two adjacent conductive gate layers; 302 and overlap the edges of the two adjacent conductive gate layers 302. The doped region 306 may pass over the conductive gate layer 302 to the right and form a diode with the drain region 0_, and the other conductive gate layer '3' to the left and the drain region 304 to form another A diode. - a MOS device region (including a conductive gate layer 302 and a source/drain region 304) and a erbium-doped region 306 are fabricated on the semiconductor layer, and the upper semiconductor layer is separated from the semiconductor substrate by an isolation layer. This is called the overlying stone structure of the insulator. The doping density of the doped region 306 is higher than the doping density of the channel region below the conductive gate layer 302. For example, the p-type doping region 306 may have a bulk density that is substantially the same as the doped density of the source/drain regions. The doping density of the doped region 306 ranges between approximately le6 cm3 and le24 cm-3. It can be appreciated that increasing the size and doping density of the p-doped region 3(9) will result in an increase in the current flowing through the diode composed of the p-doped region 3〇6 and the drain region 304. The conductive gate layer 302, the source region 304, and the p-type doping region 3〇6 are coupled to the ground terminal, and the drain region 3〇4 is coupled to the input/output pad. The above structure can be shown by the schematic diagram 400 in FIG. The N-type MOS transistor 402 represents an electronic symbol of a region of the MOS device, as described above, coupled to the bonding pad 4〇4 and the ground terminal: the inter-diode 406 represents the P-type in FIG. The electronic symbol of the diode composed of the doped region 3〇6 and the drain region 3〇4 is also coupled between the bonding pad and the ground terminal, and is connected in parallel to the N-type MOS transistor 4 (10). 0503-A32625TWF/NikeyChen jq 200812061 The core circuit 408 is coupled to the bonding pad 4〇4, in parallel between the N-type: the gold-to-conductor electrical Q-end, and the MOS semiconductor transistor. With the source is extremely 昼 讥 通 通 通 通 通 通 通 通 通 通 通 通 通 通 通 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Will not shadow, ^ milk + guide,
操作。然而，在靜電放電事件中，N型金&= 408的· 體搬和/或二極體傷可被觸發以消除^放c U圖_示有關靜電放電保護能力 ^P 曲線圖_係顯示第3圖中根據本發明之靜^ =果， 兀件以及第2圖中傳統靜電放電保護元件之电讀護 軸係表示電流的絕對值。兩個元件被設且:’其中γ 寬度:曲線502係表示第2圖中傳統靜電放電工：同的 之正靜電放電的性能，而另—曲線5〇4係表兀件 傳統靜電放電保護元件之負靜電放電的性圖中 中根據本發明之靜電放電保護元件而令，^就罘3圖 示正靜電放電的性能，而另 ° 4 5。6係表 電的性能。 忒5〇8係表示負靜電放 在正靜電放電的能力方面，兩個元件 之1.75安培的保護。在負靜電放電的性能方面目似程度 的傳統靜電放電保護元件只能提供到達’弟2圖 的靜電放電保護元件能提供有效:::保 達到-2·27安培的保護。 々改导而 如前文所描述’根據本發明所描述之靜電放電保護 0503-A32625TWF/NikeyChe] 11 200812061 元件的佈局結構可增加二極體的尺寸，而不需要使用額 :外的空間。在負靜電放電事件中，其可幫助.靜電放電保 … 護元件消除靜電放電的電流。 . . : 本發明:雖以較佳實施例揭露如上'，\然其並非用g限 定本發明的範圍，任何熟習此項技藝者’，在不脫離本發 明之精神和範圍内，當可做些許的更動與潤飾，因此本： 發明之保護範圍當視後附之申請專利範圍所界定者為 準。 0503-A32625TWF/NikeyChen 12 200812061 【圖式簡單說明】 第1圖係顯示傳統二極體的佈局結構； 第2圖係顯示傳統T型:閘極閘極接地N型金氧半導 體元件的佈局結構，;:;: 第3圖係顯示根據本發明一實施例之靜電放電保護 電路的佈局結構， 第4圖係顯示根據本發明一實施例之靜電放電保護 電路的示意圖；以及 第5圖係顯示在負靜電放電事件中根據本發明一實 施例之靜電放電保護電路的性能改善。 【主要元件符號說明】 100、200、300〜佈局結構； 102、110〜二極體； 104、112、202〜多晶矽層； 106、114〜N+型摻雜區； 108、208〜P+型摻雜區； 204、304〜源極/汲極區； 302〜導電閘極層； 306〜P型摻雜區； 400〜示意圖； 402〜N型金氧半導體電晶體； 404〜接合墊； 406〜二極體； 408〜核心電路； 500〜曲線圖； 502_508〜曲線。 0503-A32625TWF/NikeyChen 13operating. However, in the event of an electrostatic discharge, the N-type gold &= 408 body transfer and / or diode damage can be triggered to eliminate the ^ u u _ shows the electrostatic discharge protection ability ^ P curve _ system display The electrostatic readout shaft of the conventional electrostatic discharge protection element according to the present invention in Fig. 3 represents the absolute value of the current according to the present invention. Two components are set and: 'where γ width: curve 502 is the traditional electrostatic discharge worker in Figure 2: the same positive electrostatic discharge performance, and the other curve 5〇4 is the traditional electrostatic discharge protection component In the negative electrostatic discharge diagram, the electrostatic discharge protection element according to the present invention is used to illustrate the performance of the positive electrostatic discharge, and the performance of the electric discharge. The 忒5〇8 series indicates that the negative static discharge is 1.75 amps of protection of the two components in terms of the ability of positive electrostatic discharge. Conventional ESD protection components with a degree of negative electrostatic discharge performance can only provide an ESD protection component that can provide effective protection to: -2 to 2.7 amps. Modifications as described above' Electrostatic discharge protection according to the present invention 0503-A32625TWF/NikeyChe] 11 200812061 The layout structure of the components can increase the size of the diode without the use of an external space. In a negative electrostatic discharge event, it can help the electrostatic discharge protection component to eliminate the current of the electrostatic discharge. The present invention is not limited to the scope of the present invention by the following description, and is not intended to limit the scope of the present invention, and anyone skilled in the art can do it without departing from the spirit and scope of the invention. A few changes and refinements, therefore: The scope of protection of the invention is subject to the definition of the scope of the patent application. 0503-A32625TWF/NikeyChen 12 200812061 [Simple diagram of the diagram] The first diagram shows the layout structure of the conventional diode; the second diagram shows the layout structure of the conventional T-type: gate gate-grounded N-type MOS device. FIG. 3 is a view showing a layout structure of an electrostatic discharge protection circuit according to an embodiment of the present invention, and FIG. 4 is a view showing an electrostatic discharge protection circuit according to an embodiment of the present invention; and FIG. 5 is a view showing The performance of the electrostatic discharge protection circuit according to an embodiment of the present invention is improved in a negative electrostatic discharge event. [Main component symbol description] 100, 200, 300~ layout structure; 102, 110~ diode; 104, 112, 202~ polysilicon layer; 106, 114~N+ doped region; 108, 208~P+ doping 204; 304~ source/drain region; 302~ conductive gate layer; 306~P-type doped region; 400~ schematic; 402~N-type MOS transistor; 404~bond pad; 406~2 Polar body; 408 ~ core circuit; 500 ~ curve; 502_508 ~ curve. 0503-A32625TWF/NikeyChen 13