1335661 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種積體電路（integrated也响 ic)設計，特別是有關於一種靜電放電⑺⑽觸心 diScharge，ESD)保護電路的佈局⑷酬）設計。 【先前技術] =體電路中，容易受到靜電放電的影響而損壞金 metal oxide semiconductor, MOS ) it ^ ^ ^ 氧化物藉由接觸只有高於積體電路供應電壓些許伏特 的電壓’就可能破壞閘極氧化物。來自—般環境來源的 靜電電壓可輕易達到數千伏特，或是甚至達到數萬伏 特二雖然電荷以及所產生的任何電流是非常地小，靜電 電f還疋具有破壞性。因此’在靜電電荷損壞積體電路 之前，為了釋放任何的靜電電荷，積體電路中靜電放電 保護電路通常與其他核心電路一起被使用。 在低壓、高速應用方面，絕緣物上覆矽（siHc〇n⑽ insulator，S01)技術變得越來越普遍。因為絕緣物上覆矽 技術之優點多於傳導石夕晶圓（buik silicon )技術之優點， 例如：具有對閉鎖（latch up)的免疫性以及較小的接面 電容。在絕緣物上覆矽技術的使用上，二極體為傳統的 靜電放電保護元件。由於具有低觸發電壓、低導通電阻 以及兩靜電放電财受能力（ESD robustness )，在晶片内 靜電放電保護方面’二極體為有效的元件之一。然而， 0503-A32625TWF/NikeyChen 5 L335661 單獨使用傳統的二極體係無法提供足夠的保護來對抗靜 電放電電何。 另一種傳統元件，常作為靜電放電保護以對抗靜電 放電電荷，係為使用絕緣物上覆矽技術所製造的閘極接 地 N 型金氧半導體（grounded gate NMOS, GGNMOS )元 件。閘極接地N型金氧半導體元件的特徵為具有連接至 接地端的多晶石夕（poly silicon)閘極層。然而，閘極接地 N型金氧半導體元件卻無法提供足夠的靜電放電保護來 對抗負靜電放電電荷。 因此，絕緣物上覆矽技術的靜電放電保護電路需要 可提供足夠保護之靜電放電保護電路的佈局結構，用以 對抗正、負兩靜電放電電荷。 【發明内容】 有鑑於此，本發明提供一種靜電放電保護電路的佈 局結構，包括一第一金氧半導體元件區域，具有一第一 摻雜區以及一第二摻雜區，上述第一、第二摻雜區具有 相同的極性，並配置於一第一導電閘極層的兩側；以及 一第三掺雜區，沿著上述第一摻雜區配置，並位於上述 第一導電閘極層的一側，其中上述第三捧雜區具有不同 於上述第一、第二摻雜區的極性，使得上述第三摻雜區 以及上述第二摻雜區形成一二極體，在負靜電放電事件 中，上述二極體用以提高靜電放電電流的消除能力。 在本發明另一實施例中，靜電放電保護電路的佈局 0503-A32625TWF/NikeyChen 6 1335661 結構包括一第一 N型金氧半導體元件區域，具有配置於 一第一導電閘極層之兩侧的一 N型源極區以及—N型汲 極區；以及一 ？型摻雜區，沿著上述N型源極區配置/， 並位於上述第一導電閘極層的一側，使得上述p型摻雜 區以及上述N型汲極區形成一二極體，在負靜電放電事 件中，上述一極體用以提咼靜電放電電流的消除能力， 其中上述第一金氧半導體元件區域以及上述p型摻雜區 製造於一半導體層上，上述半導體層藉由一隔離層盥一 半導體基體分隔。 、 在本發明又一實施例中，靜電放電保護電路的佈局 結構包括一第一 N型金氧半導體元件區域，具有配置於 一第一導電閘極層之兩側的一第一 N型源極區以及一第 型没極區；—p型摻雜區，沿著上述第型源極 區配置，並位於上述第一導電閘極層的一側，使得上述p 型摻雜區以及上述第一 N型汲極區形成一第一二極體；1335661 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to an integrated circuit (integrated also ic) design, in particular to an electrostatic discharge (7) (10) contact center diScharge (ESD) protection circuit layout (4) Remuneration) design. [Prior Art] = In the body circuit, it is susceptible to electrostatic discharge and damage to gold metal oxide semiconductor, MOS ) it ^ ^ ^ Oxide can damage the gate by contacting a voltage that is only a few volts higher than the supply voltage of the integrated circuit. Extreme oxide. The electrostatic voltage from a general environmental source can easily reach thousands of volts, or even tens of thousands of volts. Although the charge and any current generated is very small, the electrostatic charge f is also destructive. Therefore, in order to discharge any electrostatic charge before the electrostatic charge damages the integrated circuit, the electrostatic discharge protection circuit in the integrated circuit is usually used together with other core circuits. In low-voltage, high-speed applications, silicon-on-insulator (SiHc〇n(10) insulator, S01) technology is becoming more common. This is because the advantages of the overlying insulator technology are more than the advantages of conducting buik silicon technology, such as: immunity to latch up and small junction capacitance. In the use of the overlying technology of the insulator, the diode is a conventional electrostatic discharge protection element. Due to its low trigger voltage, low on-resistance, and two electrostatic discharge capabilities (ESD robustness), the diode is one of the effective components in the protection of electrostatic discharge in a wafer. However, the use of a conventional two-pole system with 0503-A32625TWF/NikeyChen 5 L335661 alone does not provide sufficient protection against static discharge. Another conventional component, often used as an electrostatic discharge protection against electrostatic discharge charges, is a gated grounded gate NMOS (GGNMOS) component fabricated using an insulator overlying germanium technique. The gate-grounded N-type MOS device is characterized by having a polysilicon gate layer connected to the ground. However, the gate-grounded N-type MOS device does not provide sufficient ESD protection against negative ESD charges. Therefore, the electrostatic discharge protection circuit of the overlying insulator technology requires a layout structure of an electrostatic discharge protection circuit that provides sufficient protection against both positive and negative electrostatic discharge charges. SUMMARY OF THE INVENTION In view of the above, the present invention provides a layout structure of an electrostatic discharge protection circuit, including a first MOS device region having a first doped region and a second doped region, the first and the first The two doped regions have the same polarity and are disposed on both sides of a first conductive gate layer; and a third doped region disposed along the first doped region and located in the first conductive gate layer a side of the third doping region having a polarity different from that of the first and second doping regions, such that the third doping region and the second doping region form a diode, in a negative electrostatic discharge In the event, the above-mentioned diodes are used to improve the elimination capability of the electrostatic discharge current. In another embodiment of the present invention, the layout of the ESD protection circuit 0503-A32625TWF/NikeyChen 6 1335661 includes a first N-type MOS device region having one disposed on both sides of a first conductive gate layer. N-type source region and -N-type bungee region; and one? a doped region disposed along the N-type source region and located on a side of the first conductive gate layer, such that the p-type doped region and the N-type drain region form a diode. In the negative electrostatic discharge event, the one-pole body is used for improving the elimination capability of the electrostatic discharge current, wherein the first MOS device region and the p-type doping region are fabricated on a semiconductor layer, and the semiconductor layer is The isolation layer is separated from the semiconductor substrate. In another embodiment of the present invention, the layout structure of the ESD protection circuit includes a first N-type MOS device region having a first N-type source disposed on both sides of a first conductive gate layer. And a first type of non-polar region; a p-type doped region disposed along the first type of source region and located on one side of the first conductive gate layer, such that the p-type doped region and the first The N-type drain region forms a first diode;
以及第—金氧半導體元件區域，具有相鄰於上述第一 N 3L源極區的-第—導電閘極層，以及相鄰於上述第二導 電閘極層並位於上述第—N型源極區之相反側的一第二 N型汲極區，使得上述第二N型汲極區以及上述p型摻 雜區形成一第二二極體。 【實施方式】 為讓本發明之上述和其他目的、特徵、和優點能更 明顯易丨重’下文特舉出較佳實施例，並配合所附圖式， 0503-A32625TWF/NikeyChen 7 1335661 作詳細說明如下： 實施例： 第1圖係顯示使用絕緣物上覆矽技術所製造的傳統 二極體之佈局結構100。佈局結構100内的各二極體是由 N+型摻雜區以及P+型摻雜區彼此之間的接面所組成。例 如，二極體102包括位於N+型摻雜區106以及P+型摻雜 區108上方的多晶矽層104,而另一二極體110包括位於 N+型摻雜區114以及P+型摻雜區108上方的多晶矽層 112。 由於具有低觸發電壓、低導通電阻以及高靜電放電 耐受能力，傳統上使用這些二極體作為晶片内的靜電放 電保護。然而，在沒有其他元件的情況下，單獨使用這 些傳統二極體作為靜電放電保護，係無法提供足夠的保 護來對抗靜電放電電荷。 第2圖係顯示使用絕緣物上覆矽技術所製造的傳統 T型閘極閘極接地N型金氧半導體元件的佈局結構200。 佈局結構200内的各傳統T型閘極電晶體包括多晶矽層 202,以及形成於多晶矽層202兩側的N+型源極（source, S) /汲極（drain，D)區204。多晶矽層202具有T型結 構。P+型摻雜區208為佈植於N+型源極/汲極區204下 方之井區的井區接觸（well contact)。 單獨使用T型閘極閘極接地N型金氧半導體元件作 為靜電放電保護係無法提供高效率的保護來對抗負靜電 放電電荷。因此，需要一種更佳能保護核心電路的靜電 0503-A32625TWF/NikeyChen 8 661 敌電保護電路以對抗負靜電玫電電7 —第3圖係顯示根據本發明〜實：例之靜電放電保護 =件的佈局結構30G。饰=構3%包括―些n型金氧 二導體元件區域，各㈣金氣半導體元件區域包括導電 ，極層逝，以及配置於導電間極層3〇2兩侧的源極級 極區3〇4。導電閘極層302可由金屬、多Μ以及多晶石夕 ，金屬（⑽ycide)等材料所製成。源極/没極區3〇4係將 N型雜質重摻雜到Μ半導體基體中的導電閘極層3〇2 下方所製造而成。位於導電閑核層3〇2下方且介於源極/ =極區304之間的區域係定義為通道區，當通道區導通 。如熟知此技藝者所了解，通道區的摻 雜松度低於源極/汲㈣撕的摻雜。 Ρ型摻雜區306沿著源極 又 3〇4同位於型半 °° 〇4配置，並與源極區 摻雜區306、導電閘極；電：極層302的-側。？型 善彼此之間的導電性:型部分重疊，用以改 304的範圍。雖然第3麵起306可延伸超過源極區 ^ 304 6^7 I- * ^ 固係.，、員不P型摻雜區306位於源極 k 304的上面，然而p 304的下面，以上下^通亦可配置在源極區 F λΠ4 - 面。既然Ρ型摻雜區306與汲極 :二：Γ同的，？型摻雜區306與囊· & 以導體元件區域巾形成二極體，而不需要 佔用額外的空間。 如第3圖所顯示’各金氧半導體元件區域具有配置 在佈局結構3 0 0内的導電閑極層3 Q 2以及源極⑻/及極 0503-A32625TWF/NikeyChen 9 1335661 (D )區304在本發明—實施例中，p型掺雜區306配 置於兩鄰近的導電閘極層3〇2之間，並與上述兩鄰近之 導電閘極層302的邊緣重疊。p型摻雜區3〇6可往右邊越 過導電閘極層302而與没極區3G4形成一個二極體，以 及往左邊越過另一導電閘極層302而與汲極區3〇4形成 另一個二極體。 金氧半導體元件區域（包括導電閘極層302以及源 _ 極/汲極區304)以及P型摻雜區3〇6係製造於半導體層 上，半導體層藉由隔離層與半導體基體分隔。此稱為/邑 緣物上覆矽結構。P型摻雜區3〇6的摻雜密度高於位在導 電閘極層302下方之通道區的摻雜密度。例如，p型推雜 區306的才參雜密度可大體上相同於源極/汲才㈣304的摻 雜，度。^ S摻雜H 306之捧雜密度的範圍大約在y cm 3與le24 cm·3之間。可以了解到增加p型摻雜區3㈨ 的尺寸以及摻雜密度，將導致流經過由p型摻雜區3㈨ φ 與汲極區304所組成之二極體的電流也會跟著增加。 導電閘極層302、源極區304以及p型換雜區3〇6 耦接至接地端，而汲極區304耦接至輸入/輸出接合墊。 上述結構可由第4圖中示意圖400所顯示。n型金氧半 導體電晶體402係表示金氧半導體元件區域的電子符 號，如剷文所描述，執接於接合墊404以及接地端之間。 二極體406係表示第3圖中由p型摻雜區3〇6與汲極區 304所組成之二極體的電子符號，亦耦接於接合墊以 及接地端之間，以及並聯於N型金氧半導體電晶體4〇2。 0503-A32625TWF/NikeyChen 1335661 核心電路408耦接於接合墊404以及接地端之間，以及 並聯於N型金氧半導體電晶體402 .與二極體406。N型 金氧半導體電晶體402通常為不導通，因為其閘極以及 源極耦接至接地端。二極體406係反相.耦接於接合墊404 以及接地端之間。因此，在正常操作下，N型金氧半導 體電晶體402以及二極體406不會影響核心電路408的 操作。然而，在靜電放電事件中，N型金氧半導體電晶 體402和/或二極體406可被觸發以消除靜電放電電荷。 第5圖係顯示有關靜電放電保護能力的測試結果， 曲線圖500係顯示第3圖中根據本發明之靜電放電保護 元件以及第2圖中傳統靜電放電保護元件之比較，其中Y 轴係表示電流的絕對值。兩個元件被設計成具有相同的 寬度。曲線502係表示第2圖中傳統靜電放電保護元件 之正靜電放電的性能，而另一曲線504係表示第2圖中 傳統靜電放電保護元件之負靜電放電的性能。就弟3圖 中根據本發明之靜電放電保護元件而言’曲線5 0 6係表 示正靜電放電的性能，而另一曲線5 0 8係表示負靜電放 電的性能。 在正靜電放電的能力方面，兩個元件提供相似程度 之1.75安培的保護。在負靜電放電的性能方面，第2圖 的傳統靜電放電保護元件只能提供到達-0.86安培的保 護，而第3圖的靜電放電保護元件能提供有效的改善而 達到-2.27安培的保護。 如前文所描述，根據本發明所描述之靜電放電保護 0503-A32625TWF/NikeyChen 11 1335661 元件的佈局結構可增加二極體的尺寸，而不需要使用額 外的空間。在負靜電放電事件中，其可幫助靜電放電保 護元件消除靜電放電的電流。 本發明雖以較佳實施例揭露如上，然其並非用以限 定本發明的範圍，任何熟習此項技藝者，在不脫離本發 明之精神和範圍内，當可做些許的更動與潤飾，因此本 發明之保護範圍當視後附之申請專利範圍所界定者為 準°And a first-type MOS device region having a first-first conductive gate layer adjacent to the first N 3L source region and adjacent to the second conductive gate layer and located at the first-N-type source A second N-type drain region on the opposite side of the region causes the second N-type drain region and the p-type doped region to form a second diode. The above and other objects, features, and advantages of the present invention will become more apparent and <RTIgt; The description is as follows: Embodiment: Fig. 1 shows a layout structure 100 of a conventional diode manufactured by using an overcoating technique of an insulator. Each of the diodes in the layout structure 100 is composed of a junction between an N+ doped region and a P+ doped region. For example, the diode 102 includes a polysilicon layer 104 over the N+ doped region 106 and the P+ doped region 108, and the other diode 110 includes a N+ doped region 114 and a P+ doped region 108. The polysilicon layer 112. These diodes have traditionally been used as electrostatic discharge protection in wafers due to their low trigger voltage, low on-resistance, and high electrostatic discharge withstand capability. However, in the absence of other components, the use of these conventional diodes alone as electrostatic discharge protection does not provide sufficient protection against electrostatic discharge charges. Fig. 2 is a view showing a layout structure 200 of a conventional T-type gate gate grounded N-type MOS device fabricated using an overlying immersion technique. Each of the conventional T-type gate transistors within the layout structure 200 includes a polysilicon layer 202, and an N+ source (drain) region 204 formed on both sides of the polysilicon layer 202. The polysilicon layer 202 has a T-type structure. The P+ doped region 208 is a well contact implanted in a well region below the N+ source/drain region 204. The use of a T-gate gate-grounded N-type MOS device alone as an ESD protection system does not provide high efficiency protection against negative electrostatic discharge charges. Therefore, there is a need for a more excellent protection of the core circuit of the electrostatic 0503-A32625TWF/NikeyChen 8 661 enemy protection circuit against the negative static electricity 7 - Figure 3 shows the layout of the electrostatic discharge protection according to the present invention Structure 30G. The decoration constituting 3% includes some n-type gold-oxygen two-conductor element regions, and each of the (four) gold-gas semiconductor device regions includes a conductive layer, a drain layer, and a source-level polar region 3 disposed on both sides of the conductive interpole layer 3〇2. 〇 4. The conductive gate layer 302 can be made of a metal, a polysilicon, and a polycrystalline stone, a metal (10) ycide or the like. The source/drain region 3〇4 is made by heavily doping N-type impurities under the conductive gate layer 3〇2 in the germanium semiconductor substrate. The region located below the conductive free-standing core layer 3〇2 and between the source/=polar region 304 is defined as a channel region when the channel region is turned on. As is well known to those skilled in the art, the doping of the channel region is lower than that of the source/deuterium (tetra) tear. The erbium-doped region 306 is disposed along the source and further 型4, and is disposed with the source region doped region 306, the conductive gate, and the side of the electrode layer 302. ? Types of conductivity between each other: the type overlaps to change the range of 304. Although the third face 306 can extend beyond the source region ^304 6^7 I-* ^ solid system, the non-P-doped region 306 is located above the source k 304, but below the p 304, above and below ^ can also be configured in the source region F λ Π 4 - face. Since the Ρ-type doped region 306 and the bungee: two: the same,? The doped regions 306 and the capsules form a diode with a conductor element region towel without taking up extra space. As shown in FIG. 3, each of the MOS device regions has a conductive idle layer 3 Q 2 and a source (8)/and a pole 0503-A32625TWF/NikeyChen 9 1335661 (D) region 304 disposed in the layout structure 300. In the present invention, the p-doped region 306 is disposed between two adjacent conductive gate layers 3〇2 and overlaps the edges of the two adjacent conductive gate layers 302. The p-type doped region 3〇6 can pass over the conductive gate layer 302 to the right and form a diode with the gate region 3G4, and cross the other conductive gate layer 302 to the left to form a drain with the drain region 3〇4. A diode. The MOS device region (including the conductive gate layer 302 and the source/drain region 304) and the P-type doping region 3〇6 are fabricated on the semiconductor layer, and the semiconductor layer is separated from the semiconductor substrate by the isolation layer. This is called the /邑 edge of the structure. The doping density of the P-type doped region 3〇6 is higher than the doping density of the channel region below the conductive gate layer 302. For example, the p-type doping region 306 can be substantially the same as the doping density of the source/deuterium (four) 304. ^ The range of the density of the doped H 306 is approximately between y cm 3 and le24 cm·3. It can be appreciated that increasing the size of the p-doped region 3 (9) and the doping density will result in an increase in the current flowing through the diode composed of the p-type doping region 3 (9) φ and the drain region 304. The conductive gate layer 302, the source region 304, and the p-type replacement region 3〇6 are coupled to the ground terminal, and the drain region 304 is coupled to the input/output pad. The above structure can be shown by the schematic diagram 400 in FIG. The n-type MOS transistor 402 is an electronic symbol representing the region of the MOS device, as described in the shovel, and is bonded between the bond pad 404 and the ground. The diode 406 is an electronic symbol of the diode composed of the p-type doping region 3〇6 and the drain region 304 in FIG. 3, and is also coupled between the bonding pad and the ground, and is connected in parallel to the N. Type MOS transistor 4〇2. 0503-A32625TWF/NikeyChen 1335661 The core circuit 408 is coupled between the bonding pad 404 and the ground, and is connected in parallel to the N-type MOS transistor 402 and the diode 406. The N-type MOS transistor 402 is typically non-conducting because its gate and source are coupled to ground. The diode 406 is inverted. It is coupled between the bonding pad 404 and the ground. Therefore, under normal operation, the N-type MOS transistor 402 and the diode 406 do not affect the operation of the core circuit 408. However, in the event of an electrostatic discharge, the N-type MOS transistor 402 and/or the diode 406 can be triggered to eliminate the electrostatic discharge charge. Fig. 5 shows the test results relating to the electrostatic discharge protection capability, and the graph 500 shows a comparison of the electrostatic discharge protection element according to the present invention in Fig. 3 and the conventional electrostatic discharge protection element in Fig. 2, wherein the y-axis represents current The absolute value. Both components are designed to have the same width. Curve 502 represents the performance of the positive electrostatic discharge of the conventional electrostatic discharge protection element of Fig. 2, and another curve 504 represents the performance of the negative electrostatic discharge of the conventional electrostatic discharge protection element of Fig. 2. In the figure 3 of the electrostatic discharge protection element according to the present invention, the curve 506 represents the performance of positive electrostatic discharge, and the other curve 508 represents the performance of negative electrostatic discharge. In terms of the ability of positive electrostatic discharge, the two components provide a similar degree of protection of 1.75 amps. In terms of the performance of negative electrostatic discharge, the conventional ESD protection component of Figure 2 can only provide protection to -0.86 amps, while the ESD protection component of Figure 3 provides an effective improvement to -2.27 amps of protection. As previously described, the layout of the ESD protection 0503-A32625TWF/NikeyChen 11 1335661 component described in accordance with the present invention can increase the size of the diode without the need for additional space. In a negative electrostatic discharge event, it helps the ESD protection component to eliminate the current from electrostatic discharge. The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended claims.
0503-A32625TWF/NikeyChen 12 1335661 【圖式簡單說明】 第1圖係顯示傳統二極體的佈局結構； 第2圖係顯示傳統T型閘極閘極接地N型金氧半導 體元件的佈局結構； 第3圖係顯示根據本發明一實施例之靜電放電保護 電路的佈局結構； 第4圖係顯示根據本發明一實施例之靜電放電保護 電路的不意圖，以及 第5圖係顯示在負靜電放電事件中根據本發明一實 施例之靜電放電保護電路的性能改善。 【主要元件符號說明】 100、200、300〜佈局結構； 102、110〜二極體； 104、112、202〜多晶矽層； 106、114〜N+型摻雜區； 108、208〜P+型摻雜區； 204、304〜源極/汲極區； 302〜導電閘極層； 306〜P型摻雜區； 400〜示意圖； 402〜N型金氧半導體電晶體； 404〜接合塾； 406〜二極體； 408〜核心電路； 500〜曲線圖； 502-508〜曲線。 0503-A32625TWF/NikeyChen0503-A32625TWF/NikeyChen 12 1335661 [Simple diagram of the diagram] Figure 1 shows the layout structure of the conventional diode; Figure 2 shows the layout structure of the traditional T-type gate gate grounded N-type MOS device; 3 is a view showing a layout structure of an electrostatic discharge protection circuit according to an embodiment of the present invention; FIG. 4 is a view showing an electrostatic discharge protection circuit according to an embodiment of the present invention, and FIG. 5 is a view showing a negative electrostatic discharge event. The performance of the electrostatic discharge protection circuit according to an embodiment of the present invention is improved. [Main component symbol description] 100, 200, 300~ layout structure; 102, 110~ diode; 104, 112, 202~ polysilicon layer; 106, 114~N+ doped region; 108, 208~P+ doping 204; 304 ~ source / drain region; 302 ~ conductive gate layer; 306 ~ P type doped region; 400 ~ schematic; 402 ~ N type MOS transistor; 404 ~ junction 塾; 406 ~ two Polar body; 408 ~ core circuit; 500 ~ curve; 502-508 ~ curve. 0503-A32625TWF/NikeyChen