TW200919703A - Semiconductor devices for improving the ESD protection - Google Patents

Abstract

A semiconductor device. A substrate has a first conductive type. A first drain region having a second conductive type is connected to a first node. A second drain region having the second conductive type is separated from the first drain region. A source region having the second conductive type is connected to a second node. A first channel region is formed on the substrate and located between the source region and the first drain region. A second channel region is formed above the substrate and located between the source region and the second drain region. The second channel region can be connected to the first channel region. A well region having the second conductive type is formed on the substrate. A first doped region having the first conductive type is formed on the well region and coupled to the first node. A second doped region having the second conductive type is formed on the well region and connected to the second drain region.

Description

200919703 IX. Description of the invention: [Technical field to which the invention belongs]

The present invention relates to an electrostatic discharge (ESD) device for an integrated circuit, and more particularly to an improved ESD protection device that is triggered by a silicon controlled rectifier (SCR). [Prior Art] Among various electronic products, 'ESD has become one of the factors that must be overcome for product stability. For the integrated circuit, the gate grounded NM〇s transistor (grounded-gate NM0S, GGNM0S transistor), field-oxide metal oxide semiconductor field effect transistor (metal oxide semiconductor field effect transistor) , MOSFET), output buffer transistors, and bipolar transistor isoelectrics are often considered the primary ESD protection components. The 1A and 1B drawings respectively show a circuit diagram and a layout diagram of a conventional use of a finger-finger structure (finger_t^e) NMOS transistor as an ESD. The NMOS transistor of the yoke structure has a plurality of gate fingers 14, a plurality of source electrodes 16 and a plurality of gate regions 12. In FIGS. 1A and 1B, a plurality of drain regions & are coupled to pad pads of the integrated circuit, and a plurality of source regions 16 are coupled to the power supply line VSS. If the plurality of gate fingers 14 and the plurality of source regions 16 are electrically connected to the ground at the same time, the interdigitated structure is formed as a gate-connected NMOS transistor. Figures 2A and 2B show the traditional use of 矽-controlled rectifiers.

Client's Docket N〇.:95-028 ' ' TT's Docket No: 〇 492-A40983twf.doc/NikeyChen 200919703 ESD § 电路 的 device circuit diagram and cross-section. When scr is turned on, there is

Low resistance and low holding voltage characteristics. In Fig. 2A, NW and Psub represent the N-type well region and the P-type substrate, respectively, and Rnw and Rpsub represent the resistance of the N-type well region and the resistance of the p-type substrate, respectively. In Figure 2B, a simple pilot rectifier is coupled between anode 22 and cathode 24 and ESD current

The path of Iesd is shown by the direction of the arrow. When the anode 22 is coupled to the pad of the pin and the cathode 24 is coupled to ground, the pin forms an ESD protection circuit. In addition, the anode 22 can also be coupled to the power line VDD to protect the internal power line of the integrated circuit from damage to the internal circuitry of the integrated circuit. Fig. 3 is a layout view showing a hybrid SCR-MOS transistor including an I/O cell 39 and a pad 38 on a P-type substrate. The interdigitated structure NM0S transistor includes a plurality of gate fingers 3A, a plurality of source regions 34, and a plurality of drain regions 32. The source region 34 and the non-polar region 32 are N-type conductivity types. The source region 34 is coupled to the P+ pole ring 36, and the p+ pole ring 36 is drained to the power line VSS. The drain region 32 is coupled to the pad 38 via a metal segment. Each of the gate fingers 30 is disposed in a channel region between one of the source regions 34 and one of the drain regions 32. Each of the gate fingers 30 is kept parallel to each other. The N-well region (N_well, NW) 3 1 is disposed between the pad 38 and the interdigitated structure NMOS transistor. The n-type well region 31 includes a P+ doped region 33 and an N+ doped region 35. The p+ doped region 33 is closer to the interdigitated NMOS transistor than the N+ doped region 35. The n-type well region 31 is orthogonal to the complex gate fingers 30. Therefore, the N-type well area 31 is extended

Client's Docket No. : 95-028 TT's Docket No: 0492-A40983twf.doc/NikeyChen 6 200919703 can be substantially perpendicular to the channel width direction of a channel, which is covered by one of the gate fingers 30. The metal segment 37 is located on the N-type well region 31 and is electrically connected to the non-polar region 32, the P+ change region 33, the N+ change region 35, and the pad 38. When a positive ESD pulse occurs, if at least one parasitic Scr is triggered, then the feedback bias of the P+ doping region 33 will inject a large number of holes into the P-type matrix via the N-type well region 31 to form a local portion. A substrate potential to sense the feedback bias of the source region of each NMOS transistor. Therefore, when ESD occurs, all gate fingers of the NMOS transistor and all parasitic SCRs will be turned on. It can be seen that the hybrid SCR-MOS structure can be completely turned on to conduct a large amount of esd transient current. The hybrid SCR-MOS structure in the figure 3 can effectively conduct a large amount of ESD current, thereby increasing the integrated circuit ESD. Protection ability. However, in practical applications, some I/O cells or other ESD protection components may cause the NMOS transistor not to enter a snapback state, causing the SCR to fail. In particular, if the gate potential of the NMOS transistor is such that the NMOS transistor can be directly turned on as the ESD voltage rises during ESD generation, for example, a conventional RC-Inverter driving NMOS, the source of the NMOS transistor is not forward biased. It is generated so that no electron current can flow through the P-type substrate to the n-type well region to trigger the parasitic SCR.

Clienfs Docket No.: 95-028 TT^ Docket No: 0492-A40983twf.doc/NikeyChen 7 200919703 SUMMARY OF THE INVENTION In view of the above, the present invention provides a semiconductor device for improving the ESD of a static discharge, even if The transistor is directly turned on during the ESQ event and can also trigger the Shi Xi-controlled rectifier. The semiconductor device includes: a -th node and a second node; a semiconductor substrate having a -first conductivity type, and - a structural element formed on the semiconductor substrate - a plurality of -dipole regions having a second conductivity type connected to the first node; a plurality of second drain regions having the second conductivity type separated from the first-th region; the plurality of source regions having the second conductivity And coupled to the second node; and the plurality of first channel regions are formed on the semiconductor substrate and are divided between the source region and the first-nothotropic region; and the plurality of second channel regions Formed on the +conductor substrate' and located between the source region and the second non-polar region, respectively, the well region has the second conductivity type formed on the body substrate, and the well region extends in the m direction. And the first direction may form an intersection angle with at least the channel width direction of the second channel region, the well region is adjacent to the finger structure component; and the first nutrient region ' has the first conductivity type , Formed in the well region and lightly connected to the first node; and a second doped region 'having the above-described first form, formed in the well region, and intimately connected to the first _, and the pole & The above and other objects and features of the present invention will become more apparent.

Client's Docket N〇.: 95-028 TT's Docket No: 〇 492-A40983 twf.doc/NikeyChen 200919703 It is to be understood that the preferred embodiments are described below, and the accompanying drawings are described in detail below. : Figure 4 is a layout diagram showing an embodiment of the present invention. In one embodiment, 'an I/O cell 40 and a solder bump (not shown) are included. As shown in FIG. 4, the I/O cell 40 includes an interdigital NMOS transistor transistor, and the NMOS transistor includes a rectifying gate interpole 42, a plurality of drain regions 44, and a plurality of sources. District 46. The complex blue-pole finger 42 includes a plurality of first gate fingers 421 and a plurality of second gate fingers 422. The drain region 44 is opened by the polycrystalline spine (p〇iy) of the gate finger 42 to form the first drain region 441 and the second drain region 442. The structure WMOS electro-crystal system is formed in the active region, wherein the drain region 44 and the source region 46 are N-type conductivity types. The source region 46 can be lightly connected to the electric line VSS' via a metal line and the first > and the polar region 441 can be connected to the pad via a metal line. The first gate finger 421 and the second gate 422 can be connected to the power line VSS, the signal line, and the like, respectively. The first channel region is formed between the source region 46 and the first drain region 441, and the second channel region is formed between the source region 46 and the second drain region 442. The gate finger 42 is simultaneously located in the first channel. The region β and the second channel region 'where the first end of the first channel region is connected to the second end of the second channel region. The 井-type well region 48 can be formed between the pad and the yoke structure of the interdigitated structure. The 井-type well region 48 includes a ν+ doped region 481, a Ρ+ doped region 482, and a Ν+ doped region 483. Wherein, the Ρ+ doped region 482 is located between the N+# hetero region 481 and the Ν+ doped region 483, and the Ν+ doped region 481 can be close to the finger structure.

Client's Docket No.: 95-028 TT5s Docket No: 0492-A40983twf.doc/NikeyChen 9 200919703 NM0S transistor, * N+ doped region 483 can be close to the pad. The N-type well area 8 ^ can be boldly placed on the gate of the gate 42. The metal segment 4 is located above the N-well region 48 and is coupled to the first drain region 44i, the p+ doped region 482, the N+ doped region 483, and the pads. The metal segment 43 is located above the N-well region 48 and the 曰-structure NMOS transistor and is coupled to the second drain region 442 and the N+ doped region 481. The metal segments 41 and the metal segments c may be the same metal layer or different metal layers in the process. The p+ collector ring is generally provided with a NM〇S transistor and can be located on three sides of the NMOS transistor of the interdigitated structure, and the interdigitated structure is not surrounded by one side of the transistor. Pair of solder pads. The P+ collector ring 45 is coupled to the power line vss. Figs. 5A to 5C are cross-sectional views respectively taken along the tangent lines AA, BB, and CC in Fig. 4. In FIG. 5A, the first drain region 44 j , the second drain region 442 , the N+ doping region 481 , the p + doping region 482 , and the N + doping region 483 are sequentially disposed on the p-type substrate 52 and the N-type well. On the area 48, the above five areas are separated by shallow trench isolation (STI). The first drain region 44 and the P+ doping region 482 and the N+ doping region 483 are coupled to the pad 54 ′. The second drain region 442 is coupled to the N+ doping region 481, and the P+ collector ring 45 is coupled to the power source. Line VSS. Figure 5B shows the first gate finger 421 located in the first channel region 541 and the second channel region 542. Figure 5C shows the source region 46 coupled to the power line VSS. Further, in Fig. 5C, it is to be noted that a parasitic SCR is formed between the pad 54 and the power source line VSS. Figure 6 is a circuit diagram showing a parasitic SCR consisting of a P+ doped region 482, an N-type well region 48, a P-type substrate 52, and a source region 46.

Client's Docket N〇.:95-028 TT's Docket No: 0492-A40983twf.doc/NikeyChei 10 200919703 When ^positive ESD pulse balance hair soldering iron 54 and the power line Na is raised by the voltage on the soldering bumper 54 The region 44i ? your potential is also rising, and the electrons in the source region 46 can be directly turned on by the NMOS transistor or into the sudden transition transistor due to the extremely high potential of the 〇u, == no-pole region 44. However, there is no such thing as "4 is divided into the first bungee of £44 and the sixth"-there is no secret zone, so some electrons flow to the pad 54' via the first no-pole zone 441 and some electrons from the second are not. The polar region 442 enters the N-well region 48 via the N+ doped region 481. - However, the electron flow from the second non-polar region 442 muscle through the N-type well region 48 is sufficiently large, then the N-type well under the p+ substitution region 482 The voltage level of the region 48 will be low to trigger the parasitic SCR and conduct the ESD current. Therefore, the present invention can trigger the electron flow in the X direction to trigger the SCR and not only trigger the SCR by the electron flow in the gamma direction. ^ - A better way is that when the current of the ESD is as high as 亳安, the parasitic SCR starts to operate. From the formula (1), ^NW ~ PnW X - Γ 1>

W, J where d and w are as shown in Figure 4. Assume that the resistance RNW of the N-type well region 48 in Fig. 4 is 35 ohms. The condition for the SCR to operate is {ix+iY)»Rm >〇jv (2) where Ιχ is entered by the X-direction via the second drain region 442; the current of the n-well region 48, and Ιγ is The current in the Y direction enters the n-type well region 48. It is assumed that only a very small portion of the electrons enter the 井-type well region 48 from the Υ direction, so that the SCR can be triggered when the Ιχ is equal to or less than 20 mA.

Client's Docket N〇.:95-028 TT's Docket No: 0492-A40983twf.doc/NikeyChen 11 200919703 . In traditional circuit applications, when esd occurs, 500 ancient 6 蛵 蛵,, 杌 杌 P, * 土 ^ f 500 pens of current = flow from and to ^ 44. In the above example, it is known that the current that triggers the SCR and enters the N-type well region 48 is about 2〇442 and is lightly connected to the N-type well region 48^ female because of the 2 mA in the milliampere current of the dipole region. From [, and: "Zone 4481", it is expected that the Tongyu brothers one / and the polar zone 442 will enter the N-scratch SCR. In addition, the other electric current will pass through the first no = 4 丄? 21 mA current system all ESD current 5 (8) f five knives 'If the NM0S electro-crystal system is directly turned on due to the gate d d high in the ESD event, the coffee current is roughly distributed according to the gate width and the uniform sentence can be designed as the first The width of the second secret zone 442 is about one-fifth of the height of the 44th, that is, the width of the second bungee zone 442 is about one-fifth of the width of all the gate fingers. The second non-polar region may be distributed on each of the bungee regions 44 or part of the bungee regions 44, as long as the width of all the second bungee regions is approximately one-fifth of the width of the entire bungee region 44. Therefore, by adjusting the ratio of the second drain region 442 to the first 汲 (the width of the polar region 441, and adjusting the resistance of the well region resistance Rnw, it can be based on actual needs The amount of current required to trigger the parasitic SCR is provided. If the NMOS transistor is suddenly turned on during the ESD event, the above estimation can be a reference for the design of the approximate ESD component because the ESD current is not uniformly distributed according to the gate width. In addition, in FIG. 4, a first channel region (not shown) is formed between the source region 46 and the first gate region 441, and a second channel region is formed between the source region 46 and the second drain region 442. (Not shown) Therefore, the width ratio of the first channel region and the second channel region can also be adjusted by adjusting the ratio of the width of the second drain region 442 to the width of the first drain region 441.

Client's Docket No. : 95-028 TT's Docket No: 0492-A40983twf.doc/NikeyChen 200919703 Figure 7 shows a layout diagram using field effect oxides to separate the non-polar regions. In the fourth figure, the use of the gate finger 42 twin 11 to separate the non-polar region 44 limits the number of the first gate finger 421 and the second gate finger Μ to an even number. As shown in Fig. 7, the drain region 74 is separated by the field oxide 72 into a first drain region 741 and a second drain region. The advantage of using the field effect oxide is that the number of the first gate finger 721 and the second gate finger 722 can be arbitrarily specified, which can be an even number or an odd number. The first gate finger 72 and the second gate finger 722 can be coupled to the power line VSS, the signal line, and the like, respectively. Figure 8 shows another layout diagram using field effect oxides to separate the drain regions. Although the bungee oxide zone 82 is present in the bungee zone 801 to the bungee zone 8〇5. However, the two portions of the drain region 802 to the drain region 8〇4 separated by the field oxide 82 are respectively coupled by the metal layer 85. Therefore, the drain region 802 to the drain region 804 are not separated by the field oxide 82 into the first drain region and the second drain region. Only the drain region 8〇1 and the drain region 8〇5 are separated by the field oxide 82 into the first drain region 841 and the second drain region 842. As shown in Fig. 8, the second drain region may be distributed over a portion of the drain region without being evenly distributed over the respective drain regions to avoid the range of the second drain region being too small (eg, less than the junction ( C〇ntact)) is not easy to implement on the layout. Figure 9 shows a further layout of the use of field oxides to separate the drain regions. In Fig. 9, only the surface of the drain that really needs to form the second drain region 942 (for example, the bungee region 901 and the bungee region 905) has field effect oxides, and the remaining bungee regions are completely absent. (Example: bungee area

Client's Docket N〇.:95-028 TT's Docket No: 0492-A40983twf.doc/NikeyChe: 13 200919703 902-904) 〇The first diagram shows the layout of the voltage tolerant I/O cell. The signal voltage from the input of the rhetoric is greater than

The pin of the operating voltage. As with the point, the operating voltage of the I/O unit cell may be •, and the signal voltage input from the pad may be 5 volts. Between the zone and the source zone, there are two _ fingers that exist again, and the _ ^ s transistor is connected in series: the 汲 electrode of the transistor M1 is reduced to the solder 塾 _, and f 卩The two-gate finger fork 106) is coupled to the resistor and the source terminal is coupled to the Thunder/Γ3AAj Spear-%' door to the extremes of the lean limb. The transistor M3's idle knowledge (that is, the first gate finger is 1〇2) can be connected to the power supply line and the source terminal is coupled to the power line VSS. Similarly...: M2 is not extremely lightly connected to fresh 塾1〇-曰曰脰叉1〇6) Lightly connected to the resistor # 即三三极极指芏 The first end of the resistor R, and the source of the extreme body Extremely extreme. The idle terminal of the transistor M4 (ie, the connection = the fork 10 (four) is connected to the power line vss or the signal line, and to the power line Vs s. The second end of the resistor R _ to the electricity _ v DD :, and - The 汲's 汲's 汲 extreme is transferred to the material 1〇〇, and = to the power supply line VDD. The voltage of the power supply line VDD is connected and the signal voltage input from the pad 100 is at most 5 volts. According to another embodiment of the present invention, the buckling oxide 110 separates the drain into the first drain region Ui / Θ: the field drain region 112. The metal segment 113 is located in the 井-well region 114 and the second and the second Above the two NMOS transistors, and coupled to the structure and structure 匕U1, Ν+ doping

Client's Docket No.: 95-028 TT's Docket No: 0492-A40983twf.doc/NikeyChen 14 200919703 Region 115 and P+ doped region 116. The difference from FIG. 4 is that the outer metal segment (for example, the metal segment 43 of FIG. 4) is not lightly connected to the second non-polar region 112 and the N+ doped region 117, but the direct extension region is directly used. The second drain region 112 and the N+ doped region 117 are directly connected (as indicated by reference numeral A) such that they are elastic in the layout of the metal layer. ,

The present invention has been described with respect to the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and it is possible to make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims. [Simple description of the diagram] The first and second diagrams show the circuit diagram and layout of the traditional interdigitated transistor. Figures 2A and 2B show circuit diagrams and cross-sectional views of a conventional SCR, respectively. Fig. 3 is a layout view showing a hybrid type sCr_m〇S transistor. Figure 4 is a layout view showing an embodiment of the present invention. Figures 5A to 5C show cross-sectional views of the tangent lines AA, BB, and CC in Fig. 4. Figure 6 is a circuit diagram showing a parasitic SCR. Figure 7 shows a layout diagram using field effect oxides to separate the drain regions. Figure 8 shows another cloth that uses field effect oxides to separate the bungee regions.

Client's Docket No. :95-028 TT^s Docket No: 〇492-A40983twf.doc/NikeyChen 15 200919703 Board map. Figure 9 shows a further layout of the drain region using field effect oxides. Figures 10A and 10B show a layout diagram and a circuit diagram of a voltage tolerated 1/0 unit cell. Figure 11 is a layout diagram showing another embodiment of the present invention. [Description of main component symbols] 12, 32, 44, 74, 801, 802, 803, 804, 805, 901, 902, 903, 904, 905~汲 pole zone; 14, 30, 42~ gate finger again; 16 , 34, 46 ~ source region; 106 ~ third gate finger fork; 22 ~ anode; 24 ~ cathode; 31, 48, 114 ~ N type well area; 33, 482, 116 ~ P + doped area; 481, 483, 115, 117~N+ doped regions; 36, 45~P+ pole rings; 37, 41, 43, 85, 113~ metal segments; 38, 54, 100~ pads; 39, 40~I/ O unit cell; 421, 72 Bu 102~ first gate finger fork; 422, 722, 104~ second gate finger fork; 441, 741, 841, 111~ first non-polar region;

Client's Docket N〇.:95-028 TT's Docket No: 0492-A40983twf.doc/NikeyChen 16 200919703 弟二> and polar regions, 442, 742, 842, 942, 112~52~P-type base; 72, 82, 110~ field effect oxide; Ml, M2, M3, M4~ transistor R~ resistance.

Clienfs Docket No.:95-028 TT's Docket No: 0492-A40983twf.doc/NikeyChen 17

Claims (1)

200919703 X. Patent application scope: 1. A semiconductor device for improving electrostatic discharge protection, comprising: a first node and a second node; a semiconductor substrate having a first conductivity type; an electrostatic protection component forming On the semiconductor substrate, comprising: a first drain region having a second conductivity type coupled to the first node; a second drain region having the second conductivity type, and the a drain region is separated; a source region having the second conductive type and coupled to the second node; a first channel region formed on the semiconductor substrate and located in the source region and the first And a second channel region formed on the semiconductor substrate and located between the source region and the second drain region, wherein the first end of the first channel region is connected to the above a second end of the second channel region; a well region having the second conductivity type formed on the semiconductor substrate and extending in a first direction; a first doped region The first conductivity type is formed in the well region and coupled to the first node; and a second doped region has the second conductivity type formed in the well region and connected to the brother Two > and polar regions. 2. The semiconductor device according to claim 1, wherein the width of the second channel region is less than the width of the first channel region: Client's Docket No, 95-028 TT's Docket No: 0492-A40983twf. 3. The semiconductor device of claim 1, wherein the width of the second channel region is less than one-twentieth of the width of the first channel region. 4. The semiconductor device according to claim 1, wherein the first direction is formed at an angle to a channel width direction of one of the second channel regions. 5. The semiconductor device of claim 1, wherein the well region is adjacent to the electrostatic protection device. 6. The semiconductor device of claim 4, wherein the above-mentioned angle of intersection is approximately 90°. 7. The semiconductor device of claim 1, wherein the well region further comprises a contact region having the second conductivity type for coupling to the first node. 8. The semiconductor device of claim 5, wherein the second drain region is formed between the well region and the first drain region. 9. The semiconductor device of claim 1, further comprising a collector ring having the first conductivity type formed on the semiconductor substrate, coupled to the second node, and extended to the above Three sides of the ESD protection component. 10. The semiconductor device of claim 1, further comprising a third doped region having the second conductivity type formed on the semiconductor substrate and the well region and contacting the second doping District and the above second > and polar regions. Client's Docket No.: 95-028 TT's Docket No: 0492-A40983 twf.doc/NikeyChen 19 200919703 U. The semiconductor device of claim 1, further comprising 5 zones for separating the first non-polar region and The second non-polar zone mentioned above. U. The semiconductor device of claim 11, wherein the isolation region is formed of polysilicon. 13. The above-mentioned isolation zone is formed by a field effect oxide as claimed in the scope of patent application. The semiconductor device of claim 1, wherein the first node is a pad and the second node is a power line. The semiconductor device according to claim 14, wherein the well region is formed between the electrostatic protection element and the pad. The semiconductor device of claim 1, wherein the electrostatic protection element further comprises a plurality of gate fingers, and wherein the pole fingers overlap the first channel region. The semiconductor device of claim 16, wherein at least one of the above-mentioned gate fingers overlaps with the second channel region. 18. The semiconductor device of claim 16, wherein at least one of the gate fingers is coupled to the second node. 19. The semiconductor device of claim 16, wherein at least one of the gate fingers is coupled to a signal line. The semiconductor device of claim 19, wherein the signal line is coupled to the second node via a resistor. , ^21. For example, the scope of patent application! The semiconductor device of the above, wherein the first doped region, the well region, the semiconductor substrate, and the source region form a thyristor. Client's Docket N〇.:95-028 TT^s Docket No: 〇492-A40983twf.doc/NikeyChen 20 200919703 22. The semiconductor device as described in the second bungee region and the above two The doping extension region direct = miscellaneous region ^ has the above second derivative 23. The semiconductor device uses a -th junction and a first. Electrostatic enemy protection, package ~ contact; stone. A substrate, with a wide brother ~ conductivity type; - well area 'with - second conduction - first - doped area ... wide electric Μ ' formed on the above substrate The second-doped region of the fish-笙's upper-different type is formed in the second preparation region and has a separation from the third doping region; on the soil, the second doping region-the first a channel region formed between the hetero regions; a 6-pitched region and the second detecting first channel region formed between the upper inter-cell regions; the doping region and the third-fourth doping region, having the above Forming on the first well region, and extending in a first direction, in a second doped (four)' upper (four) two well region, electrically abhorrent, formed in the above-mentioned fourth doped region and the above a first contact, the first doped region is lightly connected to the upper=missing region, and the three doped regions are coupled to the fifth doped region, the upper=second contact, the first narrow type, and the above The first direction is the general ^ brother 1 heterogeneous zone is a Client's Docket No.: 95-028 ^ Stay vertical # 嗤 TT, sD〇cketNo: 0 492_A408983twfd〇c/NikeyChen Once - the second party 21 200919703 To the extension. 24. The semiconductor device of claim 23, wherein the first channel region comprises a first contact connected to a second contact of the second channel region. 25. The semiconductor device of claim 23, wherein the third doped region has a width smaller than a width of the second doped region. 26. The semiconductor device of claim 23, wherein the width of the second channel region is less than the width of the first channel region. 27. The semiconductor device according to claim 26, wherein the width of the second channel region is less than a width of the width of the first channel region - 〇 28. The semiconductor device according to claim 26 The width of the second channel region is less than one-twentieth of the width of the first channel region. 29. The semiconductor device of claim 23, wherein the well region further comprises a contact region having the second conductivity type for coupling to the first contact. 30. The semiconductor device of claim 23, wherein the third doped region is formed between the well region and the second doped region. 31. The semiconductor device of claim 23, further comprising a sixth doped region having the second conductivity type formed on the substrate and the well region and contacting the fifth doped region And the above third Client's Docket No.: 95-028 TT's Docket No: 0492-A40983twf.doc/NikeyChen 22 200919703. 32. The semiconductor device of claim 23, further comprising an isolation region for separating the second doped region and the third doped region. 33. The semiconductor device of claim 32, wherein the isolation region is formed by polycrystalline chopping. 34. The semiconductor device of claim 32, wherein the isolation region is formed by a field effect oxide. The semiconductor device of claim 23, wherein the first contact is a solder fillet and the second contact is a power line. The semiconductor device according to claim 23, wherein the first contact is a first power line, and the second contact is a second power line. 37. The semiconductor device of claim 35, wherein the well region is formed between the third doped region and the first junction. 38. The semiconductor device of claim 23, wherein the fourth doped region, the well region, the substrate, and the first doped region form a controlled rectifier. The semiconductor device according to claim 23, wherein the third doped region and the fifth doped region are connected to each other by one of the second conductive type doping extension regions. Client’s Docket No.:95-028 TT’s Docket No: 0492-A40983twf.doc/NikeyChen