US20150333052A1 - Semiconductor structure and electrostatic discharge protection circuit - Google Patents
Semiconductor structure and electrostatic discharge protection circuit Download PDFInfo
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- US20150333052A1 US20150333052A1 US14/275,995 US201414275995A US2015333052A1 US 20150333052 A1 US20150333052 A1 US 20150333052A1 US 201414275995 A US201414275995 A US 201414275995A US 2015333052 A1 US2015333052 A1 US 2015333052A1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
- H01L27/0277—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base of said parasitic bipolar transistor
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
- H01L29/7818—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
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- H01L29/0886—Shape
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Definitions
- the invention relates to and more specifically to a semiconductor structure and more specifically to an electrostatic discharge protection circuit.
- Semiconductor devices are used in elements for many products such as MP3 players, digital cameras, computer, etc. As the application increases, the demand for the semiconductor device focuses on small size and large circuit density. In the semiconductor technology, the feature size has been reduced. In the meantime, the rate, the efficiency, the density and the cost per integrated circuit unit have been improved.
- the power-saving IC usually uses a LDMOS or an EDMOS as a switch.
- a method for increasing a breakdown voltage (BVdss) of a semiconductor device such as a LDMOS or an EDMOS is decreasing a dopant concentration of a drain region or increasing a drift length.
- Electrostatic discharge is a phenomenon of electrostatic charge transfer between different objects with the accumulation of the electrostatic charges.
- the ESD occurs for an extremely short period of time, which is only within the level of several nano-seconds (ns).
- ns nano-seconds
- a very high current is generated in the ESD event, and the value of the current is usually several amperes. Consequently, once the current generated by the ESD flows through a semiconductor device, the semiconductor device is usually damaged due to high power density.
- the ESD protection device has to provide a discharge path to prevent the semiconductor device from being damaged when the electrostatic charges are generated in the semiconductor device by machine or human body.
- a semiconductor structure comprising a device structure comprising a first well region, a second well region, a source, a drain, an extending doped region, and a gate structure.
- the second well region has conductivity type opposite to a conductivity type of the first well region.
- the drain has a conductivity type same as a conductivity type of the source.
- the source and the drain are formed in the first well region and the second well region respectively.
- the extending doped region is adjoined with the drain and extended under the drain.
- the extending doped region has a conductivity type same as the conductivity type of the drain.
- the gate structure is on the first well region.
- an electrostatic discharge protection circuit comprising a first MOS device and the second MOS device.
- Each of the first MOS device and the second MOS device comprises, a source, a drain, an active body, and a gate structure.
- the gate structure is on the active body between the source and the drain.
- a higher voltage terminal is coupled to the drains of the first MOS device and the second MOS device.
- a lower voltage terminal is coupled to the source and the gate structure of the first MOS device.
- the active body of the first MOS device is coupled to the source of the second MOS device.
- a semiconductor structure comprising a first device structure and a second device structure, each of the first device structure and the second device structure comprising a first well region and/or a second well region, a source, a drain, and a gate structure.
- the source and the drain have a conductivity type same as a conductivity type of the second well region, and opposite to a conductivity type of the first well region.
- the gate structure is on the first well region between the source and the drain.
- the source of the first device structure, and the source and the drain of the second device structure are disposed in the common first well region.
- FIG. 1 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment.
- FIG. 2 illustrates a top view of the semiconductor structure according to an embodiment.
- FIG. 3 illustrates an electrostatic discharge protection circuit according to an embodiment.
- FIG. 4 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment.
- FIG. 5 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment.
- FIG. 6 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment.
- FIG. 7 illustrates an electrostatic discharge protection circuit according to an embodiment.
- FIG. 8 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment.
- FIG. 1 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment.
- FIG. 2 illustrates a top view of the semiconductor structure according to an embodiment.
- a first device structure 102 may comprise a first well region 104 , a second well region 106 , a source 108 , a drain 110 , a gate structure 112 , an extending doped region 114 and a doped contact 116 .
- the second well region 106 may be formed on a semiconductor substrate 118 having a conductivity type opposite to a conductivity type of the second well region 106 .
- the first well region 104 may be formed in the second well region 106 having a conductivity type opposite to a conductivity type of the first well region 104 by a doping process.
- the source 108 and the drain 110 having the same conductivity type are formed in the first well region 104 and the second well region 106 respectively.
- the gate structure 112 is formed on the first well region 104 and the second well region 106 between the source 108 and the second.
- the gate structure 112 comprises a gate dielectric 120 and a gate electrode 122 on the gate dielectric 120 .
- the gate dielectric 120 comprises a thinner dielectric portion 124 adjacent to the source 108 , and a thicker dielectric portion 126 adjacent to the drain 110 .
- the thinner dielectric portion 124 may be formed by a method comprising a deposition, a thermal growth, or other suitable methods.
- the thicker dielectric portion 126 is not limited to a FOX structure, and can be a STI structure, or formed by other suitable techniques. In other embodiments, thin, thick, or partial thick dielectric materials such as an oxide, etc., may be selected for the gate dielectric 120 .
- the extending doped region 114 having a conductivity type same as the conductivity type of the drain 110 may be formed to be adjoined with and extended under the drain 110 by a doping method. In one embodiment, a lower surface of the extending doped region 114 is below a lower surface of the thicker dielectric portion 126 of the gate dielectric 120 .
- the doped contact 116 is formed in the first well region 104 , and has a conductivity type same as the conductivity type of the first well region 104 .
- a second device structure 128 may comprise the first well region 104 , a source 130 , a drain 132 , a gate structure 134 and a doped contact 136 .
- the source 130 and the drain 132 formed in the first well region 104 have a conductivity type opposite to the conductivity type of the first well region 104 .
- the gate structure 134 is formed on the first well region 104 between the source 130 and the drain 132 .
- the gate structure 134 comprises a gate dielectric 138 and a gate electrode 140 formed on the gate dielectric 138 .
- the gate dielectric 138 is not limited to a thin dielectric material, and may use a thick dielectric material, such as an oxide, etc.
- the doped contact 136 is formed in the first well region 104 and has a conductivity type same as the conductivity type of the first well region 104 .
- the doped contact 136 and the source 130 may have a commonly used conductive contact 142 on which.
- the source 108 of the first device structure 102 , and the source 130 and the drain 132 of the second device structure 128 are formed in the commonly used first well region 104 .
- An isolation structure 144 may be used for separating the first device structure 102 and the second device structure 128 .
- the isolation structure 144 is not limited to a FOX structure, and may use a STI structure, or formed by other methods.
- the semiconductor structure further comprises a resistor 146 and a capacitor 148 .
- the resistor 146 may comprise polysilicon or other suitable materials, and may be formed on a dielectric layer 150 .
- the capacitor 148 may be a structure formed by a dielectric layer 156 sandwiched between conductive films 152 and 154 , such as a polysilicon-insulator-polysilicon capacitor (PIP capacitor).
- PIP capacitor polysilicon-insulator-polysilicon capacitor
- the capacitor 148 is coupled to the resistor 146 and the gate structure 134 of the second device structure 128 .
- the source 130 of the second device structure 128 is coupled to the doped contact 116 and the doped contact 136 .
- the first device structure 102 is an EDMOS device.
- the second device structure 128 is a low voltage (LV) MOS device, functioned as an electrostatic discharge protection device.
- LV low voltage
- a higher voltage terminal (high pin) 158 is coupled to the capacitor 148 and the drain 110 of the first device structure 102 and the drain 132 of the second device structure 128
- a lower voltage terminal (low pin) 160 is coupled to the resistor 146 and the source 108 and the gate structure 112 of the first device structure 102 .
- the first well region 104 (for example having a P type conductivity type) arranged at side of the source 108 of the first device structure 102 , having the conductivity type opposite the conductivity type of the source 108 , can functioned as a pick-up structure, improving an electrostatic discharge protection efficiency of the semiconductor structure.
- the extending doped region 114 extended down from the lower surface of the drain 110 and having the conductivity type same as the conductivity type of the drain 110 , can force an electrostatic discharge to flow toward a sub-surface, so as to improve electrostatic discharge protection efficiency of the semiconductor structure.
- a breakdown voltage and a trigger voltage of the first device structure 102 can be decreased by reducing a width of (or a channel length in) the (second well region 106 between the drain 110 and the first well region 104 .
- the second device structure 128 is used to adjust a trigger voltage of the electrostatic discharge protection device, to make the electrostatic discharge protection device easily triggered during an electrostatic discharge issue. For example, a width an a length of the second device structure 128 can be adjusted to control the trigger voltage of the device.
- FIG. 3 illustrates an electrostatic discharge protection circuit according to an embodiment, which may indicate the semiconductor structure as shown in FIG. 1 or FIG. 2 .
- the higher voltage terminal 158 is coupled to the drain 110 of the first device structure 102 (first MOS device) and the drain 132 of the second device structure 128 (second MOS device).
- the lower voltage terminal 160 is coupled to the source 108 and the gate structure 112 of the first device structure 102 .
- An active body 162 (comprising the first well region 104 and the second well region 106 as shown in FIG. 1 ) of the first device structure 102 is coupled to the source 130 of the second device structure 128 .
- Opposing electrodes 164 and 166 of the capacitor 148 are coupled to the drain 132 and the gate structure 134 of the second device structure 128 respectively.
- Two opposing sides of the resistor 146 are coupled to the source 108 of the first device structure 102 and the gate structure 134 of the second device structure 128 .
- the capacitor 148 and the resistor 146 are coupled (electrically connected) in series between the higher voltage terminal 158 and the lower voltage terminal 160 .
- a node (common voltage) 168 between the capacitor 148 and the resistor 146 is coupled to the gate structure 134 of the second device structure 128 .
- An active body 170 (comprising the first well region 104 as shown in FIG. 1 ) and the source 130 of the second device structure 128 are coupled to a node (common voltage) 172 .
- FIG. 4 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment. Differences between the semiconductor structures of FIG. 1 and FIG. 4 are disclosed as following.
- the first well region 104 of the second device structure 128 may be functioned as a resistor by omitting a conductive element 174 as shown in FIG. 1 .
- FIG. 5 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment. Differences between the semiconductor structures of FIG. 5 and FIG. 4 are disclosed as following. The doped contact 136 as shown in FIG. 4 is omitted.
- FIG. 6 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment. Differences between the semiconductor structures of FIG. 6 and FIG. 1 are disclosed as following.
- the resistor 146 shown in FIG. 1 is replaced by a diode 676 .
- the diode 676 comprises a doped well 678 and doped contacts 680 , 682 formed in the doped well 678 .
- the doped well 678 may be formed in the first well region 104 by an implantation process.
- the doped well 678 has a conductivity type same as the conductivity type of the first well region 104 , and is separated from the first well region 104 by the second well region 106 .
- the doped contact 680 has a conductivity type (such as P type conductivity) same as the conductivity type of the doped well 678 .
- the doped contact 682 has a conductivity type (such as N type conductivity) opposing to the conductivity type of the doped well 678 .
- FIG. 7 illustrates an electrostatic discharge protection circuit according to an embodiment, which may indicate the semiconductor structure as shown in FIG. 6 . Differences between the semiconductor structures of FIG. 7 and FIG. 3 are disclosed as following.
- the resistor 146 as shown in FIG. 3 is replaced by the diode 676 .
- Opposing electrodes 784 and 788 of the diode 676 are coupled to the source 108 of the first device structure 102 (first MOS device) and the gate structure 134 of the second device structure 128 (second MOS device).
- the capacitor 148 and the diode 676 are electrically connected in series between the higher voltage terminal 158 and the lower voltage terminal 160 .
- a node 768 between the capacitor 148 and the diode 676 is coupled to the gate structure 134 of the second device structure 128 .
- FIG. 8 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment. Differences between the semiconductor structures of FIG. 8 and FIG. 1 are disclosed as following.
- the second well region 106 comprises a buried doped layer 890 having the same conductivity type (such as N type conductivity type).
- the buried doped layer 890 is formed on the semiconductor substrate 118 having the conductivity type opposite to the conductivity type of the buried doped layer 890 .
- the second well region 106 comprising the buried doped layer 890 can provide isolation effect to the first well region 104 .
- the buried doped layer 890 may be formed by an epitaxial process, but not limited thereto. The concepts for the buried doped layer 890 may be applied to the other embodiments.
- the extending doped region 114 is omitted.
- the semiconductor structure (electrostatic discharge protection circuit) according to embodiments can provide electrostatic discharge protection to HV devices efficiently.
- the semiconductor structure may be manufactured by a standard process, without additional mask.
- the various doped elements may be formed by an implantation process or an epitaxial process properly.
- the doped contacts are heavily doped regions, or other structures having good conductivity.
- the conductive contact may be any kind of structure having good conductivity, such as a metal silicide, a metal, etc.
- the polysilicon material may be formed by a single poly process, or a double poly process. For example, a MOS capacitor structure formed by the single poly process may be used to replace the PIP capacitor. Electrical connections between the elements disclosed above can be achieved through conductive elements such as conductive wires, conductive plugs, conductive layers (such as M 1 , M 2 ), etc.
- the disclosed dielectric, insulating, isolating materials may comprise an oxide such as silicon oxide, a nitride such as silicon nitride, or other materials suitable to provide electrical isolation.
- the extending doped region can be used optionally.
- the first well region of the first device structure may be replaced by a body doped region having a conductivity type opposite to the conductivity type of the second well region, so as to make the first device structure be electrostatic discharge protection device having characteristics of a lateral diffusion MOS (LDMOS).
- LDMOS lateral diffusion MOS
- the said higher voltage terminal and the said lower voltage terminal are reversed to be a lower voltage terminal and a higher voltage terminal.
Abstract
Description
- 1. Technical Field
- The invention relates to and more specifically to a semiconductor structure and more specifically to an electrostatic discharge protection circuit.
- 2. Description of the Related Art
- Semiconductor devices are used in elements for many products such as MP3 players, digital cameras, computer, etc. As the application increases, the demand for the semiconductor device focuses on small size and large circuit density. In the semiconductor technology, the feature size has been reduced. In the meantime, the rate, the efficiency, the density and the cost per integrated circuit unit have been improved.
- Recently, a power-saving IC is a trend for development for a semiconductor device. The power-saving IC usually uses a LDMOS or an EDMOS as a switch. For example, a method for increasing a breakdown voltage (BVdss) of a semiconductor device such as a LDMOS or an EDMOS is decreasing a dopant concentration of a drain region or increasing a drift length.
- Electrostatic discharge (ESD) is a phenomenon of electrostatic charge transfer between different objects with the accumulation of the electrostatic charges. The ESD occurs for an extremely short period of time, which is only within the level of several nano-seconds (ns). A very high current is generated in the ESD event, and the value of the current is usually several amperes. Consequently, once the current generated by the ESD flows through a semiconductor device, the semiconductor device is usually damaged due to high power density. Thus, the ESD protection device has to provide a discharge path to prevent the semiconductor device from being damaged when the electrostatic charges are generated in the semiconductor device by machine or human body.
- According to one embodiment, a semiconductor structure is disclosed, comprising a device structure comprising a first well region, a second well region, a source, a drain, an extending doped region, and a gate structure. The second well region has conductivity type opposite to a conductivity type of the first well region. The drain has a conductivity type same as a conductivity type of the source. The source and the drain are formed in the first well region and the second well region respectively. The extending doped region is adjoined with the drain and extended under the drain. The extending doped region has a conductivity type same as the conductivity type of the drain. The gate structure is on the first well region.
- According to another embodiment, an electrostatic discharge protection circuit is provided, comprising a first MOS device and the second MOS device. Each of the first MOS device and the second MOS device comprises, a source, a drain, an active body, and a gate structure. The gate structure is on the active body between the source and the drain. A higher voltage terminal is coupled to the drains of the first MOS device and the second MOS device. A lower voltage terminal is coupled to the source and the gate structure of the first MOS device. The active body of the first MOS device is coupled to the source of the second MOS device.
- According to yet another embodiment, a semiconductor structure is disclosed, comprising a first device structure and a second device structure, each of the first device structure and the second device structure comprising a first well region and/or a second well region, a source, a drain, and a gate structure. The source and the drain have a conductivity type same as a conductivity type of the second well region, and opposite to a conductivity type of the first well region. The gate structure is on the first well region between the source and the drain. The source of the first device structure, and the source and the drain of the second device structure are disposed in the common first well region.
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FIG. 1 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment. -
FIG. 2 illustrates a top view of the semiconductor structure according to an embodiment. -
FIG. 3 illustrates an electrostatic discharge protection circuit according to an embodiment. -
FIG. 4 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment. -
FIG. 5 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment. -
FIG. 6 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment. -
FIG. 7 illustrates an electrostatic discharge protection circuit according to an embodiment. -
FIG. 8 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment. -
FIG. 1 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment.FIG. 2 illustrates a top view of the semiconductor structure according to an embodiment. - Referring to
FIG. 1 andFIG. 2 , afirst device structure 102 may comprise afirst well region 104, asecond well region 106, asource 108, adrain 110, agate structure 112, an extendingdoped region 114 and a dopedcontact 116. The secondwell region 106 may be formed on asemiconductor substrate 118 having a conductivity type opposite to a conductivity type of thesecond well region 106. The firstwell region 104 may be formed in thesecond well region 106 having a conductivity type opposite to a conductivity type of thefirst well region 104 by a doping process. Thesource 108 and thedrain 110 having the same conductivity type are formed in thefirst well region 104 and thesecond well region 106 respectively. - The
gate structure 112 is formed on thefirst well region 104 and thesecond well region 106 between thesource 108 and the second. In one embodiment, thegate structure 112 comprises a gate dielectric 120 and agate electrode 122 on the gate dielectric 120. The gate dielectric 120 comprises a thinnerdielectric portion 124 adjacent to thesource 108, and a thickerdielectric portion 126 adjacent to thedrain 110. For example, the thinnerdielectric portion 124 may be formed by a method comprising a deposition, a thermal growth, or other suitable methods. The thickerdielectric portion 126 is not limited to a FOX structure, and can be a STI structure, or formed by other suitable techniques. In other embodiments, thin, thick, or partial thick dielectric materials such as an oxide, etc., may be selected for the gate dielectric 120. - The extending
doped region 114 having a conductivity type same as the conductivity type of thedrain 110 may be formed to be adjoined with and extended under thedrain 110 by a doping method. In one embodiment, a lower surface of the extendingdoped region 114 is below a lower surface of the thickerdielectric portion 126 of the gate dielectric 120. The dopedcontact 116 is formed in thefirst well region 104, and has a conductivity type same as the conductivity type of thefirst well region 104. - A
second device structure 128 may comprise thefirst well region 104, asource 130, adrain 132, agate structure 134 and a dopedcontact 136. Thesource 130 and thedrain 132 formed in thefirst well region 104 have a conductivity type opposite to the conductivity type of thefirst well region 104. Thegate structure 134 is formed on thefirst well region 104 between thesource 130 and thedrain 132. Thegate structure 134 comprises a gate dielectric 138 and agate electrode 140 formed on the gate dielectric 138. The gate dielectric 138 is not limited to a thin dielectric material, and may use a thick dielectric material, such as an oxide, etc. Thedoped contact 136 is formed in thefirst well region 104 and has a conductivity type same as the conductivity type of thefirst well region 104. Thedoped contact 136 and thesource 130 may have a commonly usedconductive contact 142 on which. - As shown in
FIG. 1 andFIG. 2 , thesource 108 of thefirst device structure 102, and thesource 130 and thedrain 132 of thesecond device structure 128 are formed in the commonly used firstwell region 104. Anisolation structure 144 may be used for separating thefirst device structure 102 and thesecond device structure 128. Theisolation structure 144 is not limited to a FOX structure, and may use a STI structure, or formed by other methods. The semiconductor structure further comprises aresistor 146 and acapacitor 148. For example, theresistor 146 may comprise polysilicon or other suitable materials, and may be formed on adielectric layer 150. Thecapacitor 148 may be a structure formed by adielectric layer 156 sandwiched betweenconductive films capacitor 148 is coupled to theresistor 146 and thegate structure 134 of thesecond device structure 128. Thesource 130 of thesecond device structure 128 is coupled to thedoped contact 116 and thedoped contact 136. - In one embodiment, the
first device structure 102 is an EDMOS device. Thesecond device structure 128 is a low voltage (LV) MOS device, functioned as an electrostatic discharge protection device. For example, in cases of thefirst device structure 102 and thesecond device structure 128 both being N type devices, a higher voltage terminal (high pin) 158 is coupled to thecapacitor 148 and thedrain 110 of thefirst device structure 102 and thedrain 132 of thesecond device structure 128, and a lower voltage terminal (low pin) 160 is coupled to theresistor 146 and thesource 108 and thegate structure 112 of thefirst device structure 102. - The first well region 104 (for example having a P type conductivity type) arranged at side of the
source 108 of thefirst device structure 102, having the conductivity type opposite the conductivity type of thesource 108, can functioned as a pick-up structure, improving an electrostatic discharge protection efficiency of the semiconductor structure. The extending dopedregion 114, extended down from the lower surface of thedrain 110 and having the conductivity type same as the conductivity type of thedrain 110, can force an electrostatic discharge to flow toward a sub-surface, so as to improve electrostatic discharge protection efficiency of the semiconductor structure. A breakdown voltage and a trigger voltage of thefirst device structure 102 can be decreased by reducing a width of (or a channel length in) the (second well region 106 between thedrain 110 and thefirst well region 104. In embodiments, thesecond device structure 128 is used to adjust a trigger voltage of the electrostatic discharge protection device, to make the electrostatic discharge protection device easily triggered during an electrostatic discharge issue. For example, a width an a length of thesecond device structure 128 can be adjusted to control the trigger voltage of the device. -
FIG. 3 illustrates an electrostatic discharge protection circuit according to an embodiment, which may indicate the semiconductor structure as shown inFIG. 1 orFIG. 2 . Thehigher voltage terminal 158 is coupled to thedrain 110 of the first device structure 102 (first MOS device) and thedrain 132 of the second device structure 128 (second MOS device). Thelower voltage terminal 160 is coupled to thesource 108 and thegate structure 112 of thefirst device structure 102. An active body 162 (comprising thefirst well region 104 and thesecond well region 106 as shown inFIG. 1 ) of thefirst device structure 102 is coupled to thesource 130 of thesecond device structure 128. Opposingelectrodes capacitor 148 are coupled to thedrain 132 and thegate structure 134 of thesecond device structure 128 respectively. Two opposing sides of theresistor 146 are coupled to thesource 108 of thefirst device structure 102 and thegate structure 134 of thesecond device structure 128. Thecapacitor 148 and theresistor 146 are coupled (electrically connected) in series between thehigher voltage terminal 158 and thelower voltage terminal 160. A node (common voltage) 168 between thecapacitor 148 and theresistor 146 is coupled to thegate structure 134 of thesecond device structure 128. An active body 170 (comprising thefirst well region 104 as shown inFIG. 1 ) and thesource 130 of thesecond device structure 128 are coupled to a node (common voltage) 172. -
FIG. 4 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment. Differences between the semiconductor structures ofFIG. 1 andFIG. 4 are disclosed as following. Thefirst well region 104 of thesecond device structure 128 may be functioned as a resistor by omitting aconductive element 174 as shown inFIG. 1 . -
FIG. 5 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment. Differences between the semiconductor structures ofFIG. 5 andFIG. 4 are disclosed as following. Thedoped contact 136 as shown inFIG. 4 is omitted. -
FIG. 6 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment. Differences between the semiconductor structures ofFIG. 6 andFIG. 1 are disclosed as following. Theresistor 146 shown inFIG. 1 is replaced by adiode 676. Thediode 676 comprises a doped well 678 and dopedcontacts first well region 104 by an implantation process. The doped well 678 has a conductivity type same as the conductivity type of thefirst well region 104, and is separated from thefirst well region 104 by thesecond well region 106. In one embodiment, thedoped contact 680 has a conductivity type (such as P type conductivity) same as the conductivity type of the doped well 678. Thedoped contact 682 has a conductivity type (such as N type conductivity) opposing to the conductivity type of the doped well 678. -
FIG. 7 illustrates an electrostatic discharge protection circuit according to an embodiment, which may indicate the semiconductor structure as shown inFIG. 6 . Differences between the semiconductor structures ofFIG. 7 andFIG. 3 are disclosed as following. Theresistor 146 as shown inFIG. 3 is replaced by thediode 676. Opposingelectrodes diode 676 are coupled to thesource 108 of the first device structure 102 (first MOS device) and thegate structure 134 of the second device structure 128 (second MOS device). Thecapacitor 148 and thediode 676 are electrically connected in series between thehigher voltage terminal 158 and thelower voltage terminal 160. Anode 768 between thecapacitor 148 and thediode 676 is coupled to thegate structure 134 of thesecond device structure 128. -
FIG. 8 illustrates a schematic cross-section diagram of a semiconductor structure according to an embodiment. Differences between the semiconductor structures ofFIG. 8 andFIG. 1 are disclosed as following. Thesecond well region 106 comprises a burieddoped layer 890 having the same conductivity type (such as N type conductivity type). The burieddoped layer 890 is formed on thesemiconductor substrate 118 having the conductivity type opposite to the conductivity type of the burieddoped layer 890. Thesecond well region 106 comprising the burieddoped layer 890 can provide isolation effect to thefirst well region 104. The burieddoped layer 890 may be formed by an epitaxial process, but not limited thereto. The concepts for the burieddoped layer 890 may be applied to the other embodiments. The extending dopedregion 114 is omitted. - The semiconductor structure (electrostatic discharge protection circuit) according to embodiments can provide electrostatic discharge protection to HV devices efficiently.
- In embodiments, the semiconductor structure may be manufactured by a standard process, without additional mask. The various doped elements may be formed by an implantation process or an epitaxial process properly. The doped contacts are heavily doped regions, or other structures having good conductivity. The conductive contact may be any kind of structure having good conductivity, such as a metal silicide, a metal, etc. The polysilicon material may be formed by a single poly process, or a double poly process. For example, a MOS capacitor structure formed by the single poly process may be used to replace the PIP capacitor. Electrical connections between the elements disclosed above can be achieved through conductive elements such as conductive wires, conductive plugs, conductive layers (such as M1, M2), etc. The disclosed dielectric, insulating, isolating materials may comprise an oxide such as silicon oxide, a nitride such as silicon nitride, or other materials suitable to provide electrical isolation. The extending doped region can be used optionally. The first well region of the first device structure may be replaced by a body doped region having a conductivity type opposite to the conductivity type of the second well region, so as to make the first device structure be electrostatic discharge protection device having characteristics of a lateral diffusion MOS (LDMOS). In some embodiments, as the first device structure and the second device structure are both P type MOS devices, the said higher voltage terminal and the said lower voltage terminal are reversed to be a lower voltage terminal and a higher voltage terminal.
- While the invention has been described by way of example and in terms of the exemplary embodiment(s), it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
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US20180190815A1 (en) * | 2015-01-05 | 2018-07-05 | Csmc Technologies Fab1 Co., Ltd. | High voltage p-type lateral double-diffused metal oxide semiconductor field effect transistor |
CN111446245A (en) * | 2019-01-17 | 2020-07-24 | 世界先进积体电路股份有限公司 | Semiconductor structure |
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US6444511B1 (en) * | 2001-05-31 | 2002-09-03 | Taiwan Semiconductor Manufacturing Company | CMOS output circuit with enhanced ESD protection using drain side implantation |
US7838940B2 (en) * | 2007-12-04 | 2010-11-23 | Infineon Technologies Ag | Drain-extended field effect transistor |
US8804290B2 (en) * | 2012-01-17 | 2014-08-12 | Texas Instruments Incorporated | Electrostatic discharge protection circuit having buffer stage FET with thicker gate oxide than common-source FET |
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US20180190815A1 (en) * | 2015-01-05 | 2018-07-05 | Csmc Technologies Fab1 Co., Ltd. | High voltage p-type lateral double-diffused metal oxide semiconductor field effect transistor |
CN111446245A (en) * | 2019-01-17 | 2020-07-24 | 世界先进积体电路股份有限公司 | Semiconductor structure |
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