JPH02216847A - High breakdown strength semiconductor device - Google Patents
High breakdown strength semiconductor deviceInfo
- Publication number
- JPH02216847A JPH02216847A JP3750789A JP3750789A JPH02216847A JP H02216847 A JPH02216847 A JP H02216847A JP 3750789 A JP3750789 A JP 3750789A JP 3750789 A JP3750789 A JP 3750789A JP H02216847 A JPH02216847 A JP H02216847A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- epitaxial layer
- potential
- inversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 230000015556 catabolic process Effects 0.000 title abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052782 aluminium Inorganic materials 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
Landscapes
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は高耐圧半導体装置に関し、特に埋込み拡散層に
よって分離された高耐圧ＭＯ３）ランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high voltage semiconductor device, and more particularly to a high voltage MO3) transistor separated by a buried diffusion layer.
〔従来の技術］
従来、ＰＮ接合分離により素子間分離が行われる高耐圧
ＭＯ３，）ランジスタでは、素子を形成するエピタキシ
ャル層を逆導電型の埋込層で包囲して分離し、この分離
されたエピタキシャル層に高耐圧ＭＯＳトランジスタを
形成している。そして、このＭＯＳ）ランジスタを他の
素子や外部配線と接続する際には、配線をこの素子分離
用の埋込層上を通して接続を行っている。[Prior Art] Conventionally, in high-voltage MO3) transistors in which element isolation is performed by PN junction isolation, the epitaxial layer forming the element is surrounded and isolated by a buried layer of the opposite conductivity type, and this separated A high voltage MOS transistor is formed in the epitaxial layer. When this MOS transistor is connected to other elements or external wiring, the wiring is passed over this buried layer for element isolation.
上述した従来の高耐圧ＭＯ３）ランジスタでは、埋込層
上を通された配線に埋込層と同電位の高電圧が印加され
たとき、換言すればエピタキシャル層と逆電位の高電圧
が印加されたときに、配線下のエピタキシャル層が反転
される。そして、この反転層がソース・ドレイン領域或
いはコンタクト領域等の高濃度の拡散層に衝突した所で
ブレークダウンを起こし、耐圧を低下させるという問題
が生じている。In the above-mentioned conventional high-voltage MO3) transistor, when a high voltage having the same potential as the buried layer is applied to the wiring passed over the buried layer, in other words, a high voltage having the opposite potential to the epitaxial layer is applied. At this time, the epitaxial layer under the wiring is inverted. A problem arises in that this inversion layer causes breakdown where it collides with a highly doped diffusion layer such as a source/drain region or a contact region, resulting in a reduction in breakdown voltage.
本発明はこのようなエピタキシャル層の反転による耐圧
の低下を防止した高耐圧半導体装置を提供することを目
的とする。An object of the present invention is to provide a high breakdown voltage semiconductor device that prevents a decrease in breakdown voltage due to such inversion of the epitaxial layer.
本発明の高耐圧半導体装置は、一導電型の半導体基板に
逆導電型のエピタキシャル層を形成し、このエピタキシ
ャル層を一導電型の埋込層で形成した素子分Ｍ ｆｉｌ
域により素子分離する半導体装置において、半導体基板
上には素子分離領域上を通して延設される素子分離領域
と同極性電位の配線と交差するポリシリコン配線を設け
ており、しかもこのポリシリコン配線を前記素子分離領
域と逆極性電位に保持した構成としている。The high-voltage semiconductor device of the present invention has an epitaxial layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type, and an element portion M fil in which this epitaxial layer is formed with a buried layer of one conductivity type.
In a semiconductor device in which elements are isolated by a region, a polysilicon wiring is provided on a semiconductor substrate and intersects with a wiring having the same polarity potential as the element isolation region, which extends over the element isolation region, and this polysilicon wiring is The structure is such that it is held at a potential of opposite polarity to that of the element isolation region.
上述した構成では、素子分１ｇ領域上を通して延設され
る配線が原因とされる反転層の発生をポリシリコン配線
によって抑制し、この反転層により生じるブレークダウ
ンを抑制して高耐圧化を可能とする。In the above-mentioned configuration, the polysilicon wiring suppresses the generation of an inversion layer caused by the wiring extending over the 1g region of the element, and suppresses the breakdown caused by this inversion layer, making it possible to increase the breakdown voltage. do.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
Ｐ−型シリコン基板１の素子分離領域に高濃度のＰ型不
純物を選、次的に導入しておき、この基板１上にＮ−型
エピタキシャル層２を成長する。このとき、前記Ｐ型不
純物が上方に拡散し、Ｐ゛゛込層３が形成される。更に
、エピタキシャル層２０表面から高濃度のＰ型不純物を
選択的に拡散させてＰ“層４を形成し、前記Ｐ°埋込層
３に到達させることで、これらＰ゛゛込層３とＰ゛層４
で素子分離領域５を形成する。A highly concentrated P type impurity is selected and introduced into the element isolation region of a P- type silicon substrate 1, and an N- type epitaxial layer 2 is grown on this substrate 1. At this time, the P-type impurity diffuses upward, and a P-type impurity layer 3 is formed. Furthermore, by selectively diffusing high-concentration P-type impurities from the surface of the epitaxial layer 20 to form a P'' layer 4 and allowing it to reach the P° buried layer 3, these P'' buried layers 3 and P'' layer 4
Then, element isolation regions 5 are formed.
この素子分離領域で分離されたエピタキシャル層２には
、ＭｏＳトランジスタを形成しており、図では例えばエ
ピタキシャルコンタクト領域としてのＮ“拡散層１０を
示している。A MoS transistor is formed in the epitaxial layer 2 separated by this element isolation region, and the figure shows, for example, an N'' diffusion layer 10 as an epitaxial contact region.
マタ、前記シリコン基板１上には、シリコン酸化膜から
なる厚い絶縁膜６を形成し、更にこの上にリンガラス（
ＰＳＧ）膜７を形成し、この上にアルミニウム配、９８
を形成している。このアルミニウム配線８はエピタキシ
ャル層２に形成されたＭｏ３）ランジスタを他のＭｏ３
）ランジスタ或いは電源、接地等の外部配線に接続する
ためのものである。First, a thick insulating film 6 made of a silicon oxide film is formed on the silicon substrate 1, and a phosphor glass (
PSG) film 7 is formed, and an aluminum layer 98 is formed on this film.
is formed. This aluminum wiring 8 connects the Mo3) transistor formed in the epitaxial layer 2 to another Mo3 transistor.
) This is for connecting to a transistor or external wiring such as power supply and grounding.
そして、前記絶縁膜６の上には、前記Ｎ゛型型数散層０
と素子分Ｎ領域５との間において、前記アルミニウム配
線８と交差するようにパターン形成したポリシリコン配
線９を形成している。このポリシリコン配線９は前記エ
ピタキシャル層２に電気接続しており、常にエピタキシ
ャル層２と同電位に保持されるように構成している。Then, on the insulating film 6, the N-type scattering layer 0
A polysilicon wiring 9 is formed in a pattern so as to intersect with the aluminum wiring 8 between the element N region 5 and the aluminum wiring 8 . This polysilicon wiring 9 is electrically connected to the epitaxial layer 2 and is configured to be always held at the same potential as the epitaxial layer 2.
ここで、前記エピタキシャル層２は高圧Ｖ０電位とされ
、前記素子分離領域５はＶＳＳ電位とされているため、
これらの接合面には空乏層１１が広がり、耐圧を保って
いる。Here, since the epitaxial layer 2 is at a high voltage V0 potential and the element isolation region 5 is at a VSS potential,
A depletion layer 11 spreads across these junction surfaces to maintain breakdown voltage.
ここで、アルミニウム配線８にＶＳＳ電位が加えられる
と、エピタキシャル層２の表面はこのＶ。Here, when a VSS potential is applied to the aluminum wiring 8, the surface of the epitaxial layer 2 reaches this V.
電位に引かれてホールが集まりＰ−型に反転する。Attracted by the potential, holes gather and invert into a P-type.
こうして形成されたＰ−反転１ｉ１１２はＮ゛゛散層１
０に到達し、Ｐ−Ｎ’″接合の耐圧以上の電界がかかる
と、素子分Ｍ ’ｐＴＪ域５とエピタキシャル層２の耐
圧の実力以下でもブレークダウンを起こすおそれがある
。The P-inversion 1i112 thus formed is the N-diffused layer 1
0, and if an electric field higher than the breakdown voltage of the PN''' junction is applied, breakdown may occur even if the voltage is lower than the actual breakdown voltage of the element M'pTJ region 5 and the epitaxial layer 2.
しかしながら、この構成ではポリシリコン配線９はＰＳ
Ｇｉ７＠介さずシリコン酸化膜６の上に直接形成されて
いるため、ポリシリコン配線９の高電位の影響でアルミ
ニウム配線８の下に生じる反転層１２は反転し難くなり
、上述した反転層によるブレークダウンの発生を防止す
る。However, in this configuration, the polysilicon wiring 9 is
Since Gi7@ is formed directly on the silicon oxide film 6 without intervening, the inversion layer 12 formed under the aluminum interconnection 8 due to the high potential of the polysilicon interconnection 9 becomes difficult to invert, and the above-mentioned break due to the inversion layer occurs. Prevent the occurrence of down.
なお、本発明はＮ型シリコン基板にＰ−エピタキシャル
層を形成しかつこのエピタキシャル層をＮ゛゛込層によ
り素子分離する構成においても同様に適用することがで
きる。Note that the present invention can be similarly applied to a structure in which a P-epitaxial layer is formed on an N-type silicon substrate and the elements of this epitaxial layer are separated by an N-type layer.
以上説明したように本発明は、素子分離領域と同極性電
位の配線と交差するポリシリコン配線を設け、かつこの
ポリシリコン配線を前記素子分離領域と逆極性電位に保
持しているので、素子分離領域上を通して延設された配
線が原因とされる反転層の発生をポリシリコン配線によ
って抑制し、素子分離領域とエピタキシャル層との本来
の耐圧を保って半導体装置の高耐圧化を実現できる効果
がある。As explained above, in the present invention, a polysilicon wiring is provided which intersects with a wiring having the same polarity potential as the element isolation region, and this polysilicon wiring is held at the opposite polarity potential to the element isolation region. Polysilicon wiring suppresses the occurrence of an inversion layer caused by wiring extending over the area, maintains the original withstand voltage between the element isolation region and the epitaxial layer, and has the effect of increasing the withstand voltage of semiconductor devices. be.
第１図は本発明の一実施例の縦断面図である。
１・・・Ｐ型シリコン基板、２・・・Ｎ−エピタキシャ
ル層、３・・・Ｐ゛埋込層、４・・・Ｐ゛層、５・・・
素子分離領域、６・・・シリコン酸化膜、７・・・ＰＳ
Ｇ、８・・・アルミニウム配線、９・・・ポリシリコン
配線、１０・・・Ｎ゛拡散層、１１・・・空乏層、１２
・・・Ｐ−型反転層。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... P type silicon substrate, 2... N- epitaxial layer, 3... P' buried layer, 4... P' layer, 5...
Element isolation region, 6... silicon oxide film, 7... PS
G, 8... Aluminum wiring, 9... Polysilicon wiring, 10... N' diffusion layer, 11... Depletion layer, 12
...P-type inversion layer.
Claims (1)
層を形成し、このエピタキシャル層を一導電型の埋込層
で形成した素子分離領域により素子分離した半導体装置
において、前記半導体基板上には前記素子分離領域上を
通して延設される素子分離領域と同極性電位の配線と交
差するポリシリコン配線を設け、かつこのポリシリコン
配線を前記素子分離領域と逆極性電位に保持したことを
特徴とする高耐圧半導体装置。1. In a semiconductor device in which an epitaxial layer of an opposite conductivity type is formed on a semiconductor substrate of one conductivity type, and elements of this epitaxial layer are isolated by an element isolation region formed of a buried layer of one conductivity type, on the semiconductor substrate: A polysilicon wiring is provided that extends over the element isolation region and intersects with a wiring having the same polarity potential as the element isolation region, and the polysilicon wiring is maintained at a potential of opposite polarity to the element isolation region. High voltage semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3750789A JPH02216847A (en) | 1989-02-17 | 1989-02-17 | High breakdown strength semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3750789A JPH02216847A (en) | 1989-02-17 | 1989-02-17 | High breakdown strength semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02216847A true JPH02216847A (en) | 1990-08-29 |
Family
ID=12499445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3750789A Pending JPH02216847A (en) | 1989-02-17 | 1989-02-17 | High breakdown strength semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02216847A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4985984A (en) * | 1972-12-20 | 1974-08-17 | ||
| JPS6156431A (en) * | 1984-08-28 | 1986-03-22 | Nec Corp | High-voltage semiconductor integrated circuit |
-
1989
- 1989-02-17 JP JP3750789A patent/JPH02216847A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4985984A (en) * | 1972-12-20 | 1974-08-17 | ||
| JPS6156431A (en) * | 1984-08-28 | 1986-03-22 | Nec Corp | High-voltage semiconductor integrated circuit |
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