JPS6156431A - High-voltage semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable the high-voltage action by inhibiting the generation of parasitic MOSFET effect by a method wherein a conductor layer with a fixed potential impressed by isolation from the semiconductor substrate is formed between the substrate and a wiring conductor. CONSTITUTION:An N<-> epitaxial layer 3 is assumed to be impressed with a high voltage through an electrode 7 and an N<+> diffused layer 5. A wiring 8 extends over isolated P-layers 2 to the top of a P-layer 4: when the potential of the wiring 8 is low enough to generate an inversion layer, inversion layers 9 generate in the layer 3. Current flows from the P-layer 4 through these inver sion layers 9 to the substrate 1 having the lowest potential, and then a parasitic MOSFET generates. The potential of a conductor layer 10 of aluminum or poly Si is fixed at the maximum potential by forming this layer 10 at the region where an inversion layer 6 is desired to cut. A voltage of reverse polarity to that of a voltage generating inversion layers is impressed under the conductor layer 10, and the inversion layer is cut. Since the conductor layer 10 is formed by isolation from the layer 3, the withstand voltage does not deteriorate or the area does not increase.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor integrated circuit that handles high voltage.
f, related to what is done by pn junction separation.

(Traditional technique #) Generally when forming high voltage elements into integrated circuits.

A thick N- epitaxial layer with low resistivity is formed on a P-type substrate, and a P-type wave dispersion layer reaches the P-type substrate from one surface.
Several regions were formed surrounding the epitaxial layer, and the device metals were placed in the regions to separate the devices.

In this case, it is relatively easy to make the elements themselves withstand voltage, but if you try to provide a certain function by connecting the elements with wiring, the epitaxial layer has a high resistivity, so the wiring and wiring The underlying silicon oxide film forms an MO8 structure, and a P-type inversion layer is formed due to the potential relationship between this wiring and the N-epitaxial layer below this wiring. If this P-type inversion layer is formed between two P layers with a potential difference, a parasitic MO8PET with these P layers as a source and drain will operate, causing unnecessary current to flow, and normal operation cannot be expected.

(Problems to be Solved by the Invention) One object of the present invention is to suppress the occurrence of the parasitic MO8PET effect and to obtain a semiconductor integrated circuit capable of high voltage operation.

(Means for Solving the Problems) According to the present invention, a semiconductor integrated circuit is obtained in which a fixed potential is applied between a semiconductor substrate and a wiring conductor, separated from the semiconductor substrate, and an FC conductor layer is entirely formed.

·(Example) Next, the present invention will be explained in detail with reference to one drawing.

FIG. 3 shows how a parasitic MO8F'ET is generated, and assumes that a high voltage is applied to the N- epitaxial layer 3 through the electrode 7 and the 1-diffusion layer 5. At this time, the wiring 8 passes over the isolation layer 2 and extends over the layer 2 4, and if the potential of this wiring 8 is low enough to create an inversion layer, an inversion layer is formed in the N-epitaxial layer 3. 9 occurs. Through this inversion layer 9, current flows from the second layer 4 to the substrate 1, which has the lowest potential.

Conventionally, to prevent such a situation, <N”
/i5't''N- is formed in the epitaxial layer 3.

Since this N+ layer 5' has a high concentration, an inversion layer is difficult to form. Therefore, the inversion layer 9 is divided at this part. However, it is necessary to carefully consider the position of this high concentration layer 5. In other words, when the depletion layer reaches this high concentration layer 5', the container caused an avalanche breakdown,
For example, in Fig. 4, separation 2
If the distance from layer 2 is not sufficient, the original withstand voltage will be lost. Separating them sufficiently will lead to an increase in area, which is undesirable.

According to the present invention, the channel can be tightened without causing such an increase in area. Specifically, FIG. 1 shows one embodiment of the present invention. According to the present invention, a conductor layer 10t of aluminum or polysilicon is formed in the region where the inversion layer 9 is to be divided, and the potential of the conductor layer 10 is fixed at the highest potential. In this way, a voltage having a polarity opposite to the voltage that produces an inversion layer is applied below the conductor layer 10, thereby dividing one inversion layer. Further, since the conductor layer 10 is formed separately from the N 2 epitaxial layer 3 in this portion, there is no deterioration in breakdown voltage or increase in area as in the conventional case.

'l''R'''tJJ'l'l-j'', bmfHl, -a
6"6116"" (Figure 2 shows a typical example. This is a case where the collector of a high voltage NPN transistor is connected to the power supply v0° with an emitter, and the region 5"' is connected to the ground GN DiC. A conductor layer 10 fixed at the highest potential is formed below the wiring 7'' from the region 5''.

Although not mentioned above, it is also possible to form a conductor layer with a fixed potential under the wiring 7'' from the second layer 4 as a space area.Also, although it is not common, the above explanation It is also possible to form the semiconductor regions with opposite polarities, and in this case, it is better to set the potential of the wiring of the present invention to GND.

(Effects of the Invention) As described above, according to the present invention, a semiconductor integrated circuit capable of high voltage operation can be realized in a small area.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing one embodiment of the present invention, and FIG. 2 is a cross-sectional view showing an application example of the present invention. Figure 3 shows parasitic Pch
FIG. 4 is a cross-sectional view of a conventional semiconductor device showing how a MOS FET is formed, and FIG. 4 is a cross-sectional view of a conventional semiconductor device in which generation of a parasitic MO8FET is prevented by an N+ channel stopper. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... P-type layer, 3... N-type layer, 4... P-type layer, 5...
...N-type layer, 5'...N-type layer, 6...
...Insulating film, 6'...Insulating film, 7...
・Vcc (high voltage electrode), 8...low voltage wiring,
9...P cedar bark inversion layer, 10...vcC (
High voltage wiring), 5''... N-type layer (NPN transistor collector). 5'''... N-type layer (NPN transistor emitter, ri), 7'... ...VCO (high voltage) wiring, 7"
...Base wiring, 7'''...GND wiring.

Claims (1)

[Claims] A high-voltage semiconductor integrated circuit characterized in that a conductor having a voltage opposite to that of inverting the conductivity type of the semiconductor layer is formed under a surface wiring on a semiconductor layer in which a semiconductor element is formed, via an insulating film. .