JP3264030B2 - Vertical MOSFET - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical MOSFET, and more particularly, to a structure in which a body-to-body distance in a peripheral portion is formed shorter than a body-to-body distance in an element region, thereby improving avalanche withstand capability. Vertical MOSFET.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional vertical power MOSFET.
FIG. 4 is a cross-sectional view showing an internal structure near an outer peripheral portion of a semiconductor chip constituting the semiconductor device.

[0003] As shown in FIG.
The semiconductor chip 11 constituting the FET is composed of an N ⁺ type silicon substrate 12 and an N ⁻ type epitaxial layer 13 formed by performing epitaxial growth on the N ⁺ type silicon substrate 12 as a base.

Above the N ⁻ -type epitaxial layer 13, P-type semiconductor regions 14 ^# , 14, 14 serving as the body of the vertical MOSFET are formed by diffusion. Except for the P-type semiconductor region 14 ^# , which is the body of the peripheral portion, each of the P-type semiconductor regions 14, 14 which is the body of the element region has each of the channel regions 14 ^* , 14 ^* , 14 ^* , 14 ^* , In the upper layer, N ^{+ type} semiconductor regions 15, 15, 15, 15 serving as source regions are formed by diffusion.

Further, the N ⁻ in which the semiconductor region is formed is described.
On the upper portion of the p-type semiconductor layer 14, the P-type semiconductor region 14 ^# in the peripheral portion, the N ⁺ -type semiconductor region 15 on the P-type semiconductor region 14 in the device region adjacent thereto, and the P-type semiconductor region adjacent to the device region Silicon oxide films (SiO ₂ films) 16, 16, 16 are selectively formed over the adjacent N ⁺ -type semiconductor regions 15, 15 on the upper portions 14, 14. After the silicon oxide films 16, 16, 16 are formed, the gate electrodes 17, 1 are formed on the silicon oxide films 16, 16, 16 using, for example, Poly-Si.
7, 17 are installed.

Further, the gate electrodes 17, 17, 17 are covered with interlayer insulating films 18, 18, using, for example, PSG.
18 are formed, the source electrode 1 is formed using, for example, Al.
The source electrode 19 short-circuits each of the P-type semiconductor regions 14 and the N ⁺ -type semiconductor regions 15 and 15 formed thereon. Although not shown, a drain electrode is provided on the back surface of the N ⁺ type silicon substrate 12.

As is clear from FIG. 2, a conventional vertical M
In the OSFET, the P-type semiconductor region 14 of the element region
Although the channel region 14 ^* and the source region 15 are respectively formed on, because they are not formed in the P-type semiconductor region 14 ^# peripheral portion, the body of the peripheral portion - Body distance L ₁ is the body of the element region - between the body It has been formed longer than the distance L _2. Further, although not shown, the body of the element region - Body distance L ₂ is all equally formed.

The above-mentioned conventional vertical MOSFET has been used as a switching element by connecting an inductive load. FIG. 3A is a schematic circuit diagram in such a case, and FIG. 3B is a current-voltage waveform at that time.

As shown in FIG. 3A, an inductive load L (hereinafter referred to as an L load) is connected to the drain of a MOSFET whose source is grounded, and the L load is a power supply V whose one side is grounded. Connected to _DD .

Then, the gate electrode 17 of the MOSFET
When applying a positive gate voltage V _G (see FIG. 2), the MOSFET is turned on, N ⁺ -type source region 15 (FIG inversion layer is generated in the channel region 14 of P-type semiconductor region 14 ^* (see FIG. 2) 2) (see dotted arrows in FIG. 2).

In this case, as shown in FIG.
When the power supply voltage V _DD is applied to the FET and the switch is turned on, the drain voltage V _D remains very constant at a very small value, but the drain current I _D gradually increases.

When the switch is turned off, the load is reversed to the L load.
An electromotive force is generated, and the back electromotive force causes the drain voltage V_D
Rises sharply. And the drain voltage V_DBreak
Shutdown voltage V_BRIs reached, the MOSFET
Avalanche current (indicated by solid arrows in Fig. 2)
The energy stored in the L load is half of the internal MOSFET.
It will be absorbed in the conductor region. Therefore, the switch
Immediately after turning off the drain current I_DBegins to decrease and the drain
Current I_DBecomes zero when the drain voltage V _DIs power
Voltage V_DDDecreases to In the above, avalanche
Energy that can be absorbed by the semiconductor region inside the MOSFET
Expressed in energy.

[0013]

[SUMMARY OF THE INVENTION Incidentally, as shown in FIG. 2, in the conventional vertical MOSFET, the body of the periphery - Body distance L ₁ is the body of the device region - than the body between the distance L ₂ Long formed (L ₁ >
L _2). The withstand voltage of the MOSFET is determined by the withstand voltage of the region facing the peripheral portion where the distance between the bodies is long. Since the withstand voltage is lower in the region facing the peripheral portion where the distance between the body and the body is longer than in the element region where the distance between the body and the body is shorter, the avalanche current faces the peripheral portion. The flow was easier in the area than in the other element areas.

Therefore, when the switch is turned off, the avalanche current based on the energy of the back electromotive force flowing from the L load causes the N ⁻ type epitaxial layer 13, the P type semiconductor region 14, and the N ⁺ type semiconductor region 15 to form. Sex NP
The N-transistor _TP is easily turned on, and a particularly large current flows in this portion (indicated by a thick arrow in FIG. 2). This portion is easily broken locally due to current concentration, and the energy absorbing ability is reduced. I was

That is, in the L load switching of the vertical MOSFET, there is a problem that an element is destroyed in a peripheral portion thereof and the avalanche withstand capability is reduced. In this case, as shown in FIG. 4, a flywheel diode _DF is connected in parallel to both ends of the L load so that the energy generated by the back electromotive force generated in the L load when the switch is turned off flows through the flywheel diode _DF. And MO
Although it has been considered to compensate for the reduction in the avalanche withstand capability of the SFET, this method requires an extra circuit element, and has a problem that it is against the recent demand for miniaturization of a semiconductor device.

The present invention has been made in view of such circumstances, and an object of the present invention is to improve avalanche withstand capability by preventing local current concentration from occurring in a vertical MOSFET.

[0017]

SUMMARY OF THE INVENTION The present invention provides a vertical MOSF.
In the ET, the body in the peripheral portion and the body in the element region have the same depth, and the body-body distance in the peripheral portion is shorter than the body-body distance in the element region. The avalanche current is configured to flow substantially evenly in an element region other than the element region described above.

[0018]

According to the present invention, in the vertical MOSFET, the breakdown voltage is improved in the region where the distance between the bodies facing the peripheral portion is short.

Therefore, when the switch is turned off when an inductive load is connected and used as a switching element, an avalanche current is less likely to flow in the area facing the peripheral part than in other element areas. In addition, since the avalanche current flows in the other element regions substantially uniformly, local element destruction caused by current concentration due to turning on of the parasitic NPN transistor is less likely to occur, and the avalanche withstand capability is improved.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing an internal structure near an outer peripheral portion of a semiconductor chip constituting a vertical power MOSFET according to one embodiment of the present invention.

As shown in FIG.
The semiconductor chip 1 constituting the OSFET is different from the conventional semiconductor chip 11 shown in FIG.
Body distance L ₁ is, the body of the element region - are shorter than the body between the distance _{L 2 (L 1 <L 2} ). Since other configurations are the same, the same members are denoted by the same reference numerals, and redundant description will be omitted.

Since the present embodiment is configured as described above, when the inductive load is connected and used as a switching element, the withstand voltage is reduced in the region where the body-to-body distance facing the peripheral portion is short. Be improved. Therefore, an avalanche current is less likely to flow in this portion than in other element regions.

Further, since the avalanche current flows substantially evenly in the other element regions, local element destruction caused by current concentration due to turning on of the parasitic NPN transistor is less likely to occur, and the avalanche resistance is improved. Become.

When the avalanche withstand capability is improved, it is no longer necessary to provide a flywheel diode as shown in FIG. 4, so that an extra circuit element is not required and the entire device can be downsized.

In the above embodiment, an N-channel vertical MOSFET has been described as an example. However, the present invention is naturally applicable to a P-channel vertical MOSFET having an opposite conductivity type.

[0026]

As described above, according to the present invention, the body in the peripheral portion and the body in the element region have the same depth, and the distance between the body and the body in the peripheral portion is smaller than that in the element region. Since it is formed shorter than the body-to-body distance,
Since the avalanche current hardly flows in the region facing the peripheral portion and the avalanche current flows evenly in the element region, local element destruction is less likely to occur, so that the avalanche resistance can be improved.

Further, since no extra circuit elements are required, the size of the entire apparatus can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an internal structure near an outer peripheral portion of a semiconductor chip constituting a vertical MOSFET according to one embodiment of the present invention.

FIG. 2 is a cross-sectional view showing an internal structure near an outer peripheral portion of a semiconductor chip constituting a conventional vertical MOSFET.

3A and 3B are diagrams illustrating a case where an inductive load is connected and used as a switching element. FIG. 3A is a schematic circuit diagram in that case, and FIG. 3B is a current-voltage wave type at that time. is there.

FIG. 4 is a schematic circuit diagram when a flywheel diode is connected in parallel to an inductive load.

[Explanation of symbols]

1,11 semiconductor chip 14 ^# periphery of the P-type semiconductor region (body) 14, 14 an element region of the P-type semiconductor region (body) L ₁ periphery of the body - the body distance L ₂ element region of the body - the distance between the body

Claims (1)

(57) [Claims] 1. A to a body of the body and the element region of the peripheral portion to <br/> equal depth one another, and the body of the peripheral portion - the body of the distance element region between the body - shorter than the distance between the body To the element area other than the element area facing the peripheral part.
A vertical MOSFET characterized in that a valanche current flows substantially uniformly .