JPH10321857A - Mos semiconductor device having high breakdown strength - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS semiconductor device which can be operated surely, can be manufactured easily, and is improved in avalanche resistance by providing a plurality of Zener diodes reversely connected in series with each other between the source electrodes and gate electrodes of second and first MOS semiconductor elements. SOLUTION: An auxiliary IGBT section which is a second MOS semiconductor element 2 and Zener diodes 3 which are reversely connected in series with each other are connected in series between the drain and gate of a main IGBT section which is a first MOS semiconductor element 1. In addition, the drain and gate of the auxiliary IGBT section are shortcircuited. In the Zener diodes row 3, reversely connected Zener diodes are connected in multiple stages. Therefore, when an overvoltage is applied across the gate electrodes of the second MOS semiconductor element 2, the element 2 is turned on and a current is supplied to the gate electrode of the first MOS semiconductor element 1 through the Zener diodes 3, turns on the element 1, and increases the avalanche resistance of the element 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS field effect transistor (hereinafter referred to as a MOSFET) in which a plurality of source regions having a gate of a metal-oxide-semiconductor (MOS) structure are provided dispersed in a surface layer of a semiconductor substrate. And a MOS type semiconductor device such as an insulated gate bipolar transistor (hereinafter referred to as IGBT).

[0002]

2. Description of the Related Art For example, one MO of a MOS type semiconductor device is used.
The SFET has a structure in which a pn junction is exposed on the surface of the substrate by selective diffusion of impurities in a surface layer of the n-type semiconductor substrate.
A base region is formed, and a similar n-source region is formed in the surface layer. An insulating film is formed on the surface of the channel region which is the surface layer of the p-base region sandwiched between the n-source region and the n-type semiconductor substrate. In this case, a gate electrode is provided, a source electrode is provided in common contact with the p base region and the n source region, and a drain electrode is provided on the n-type semiconductor substrate. By applying an appropriate voltage to the gate electrode, an inversion layer is formed in the channel region, and through the inversion layer, the drain electrode
The resistance between the source electrodes is reduced, and a current flows.

An example of an IGBT can be said to be a conductivity-modulated type by adding a p-type region to the drain electrode side of a MOSFET and utilizing the injection of minority carriers. In switching circuits, MOS transistors are used because of their low on-resistance, high switching speed, and easy control by voltage.
Semiconductor devices are frequently used.

[0004]

In recent years, in a switching circuit, a MOS type semiconductor device as a switching element has a simplified circuit such as omitting a snubber circuit.
Due to miniaturization of the device and the like, it has become easier to receive the generated surge voltage. For example, when an attempt is made to cut off the current of an inductive load (so-called L load), the voltage applied to the MOS semiconductor device increases due to the energy stored in the inductance, and sometimes even exceeds the power supply voltage. This overvoltage stress leads to the cause of destruction of the MOS type semiconductor device, and there is a demand for an improvement in the destruction resistance (avalanche resistance).

As one method for improving the avalanche withstand capability of such a MOS type semiconductor device, the diffusion depth of a part of the p base region is increased. However, when the diffusion depth is increased, other characteristics such as on-resistance are affected. For example, in a MOSFET,
By increasing the depth from 5 μm to 7 μm, the avalanche resistance is increased by 25%, but at the same time, the on-resistance is reduced by 15%.
% Increase. Therefore, this method is not universal.

FIG. 11 shows a MOSF in which another measure is taken.
FIG. 2 is a cross-sectional view of USP. 5,365,099].
The left part of the figure is a normal MOSFET. That is, the n drift layer 1 stacked on the n ⁺ drain layer 11
3 has a plurality of p base regions 14 and p
⁺ Contact region 15 is formed, and n source region 16 is formed in the surface layer. A gate electrode layer 18 made of, for example, polycrystalline silicon is provided via a gate oxide film 17 on a portion between the n source region 16 of the p base region 14 and the exposed surface of the n drift layer 13. I have. p base region 14 and n source region 16
, A source electrode 19 made of an Al alloy is provided, insulated by an interlayer insulating film made of borophosphosilicate glass (BPSG), and extended over the gate electrode layer 18. On the back side of the n ⁺ drain layer 11,
A drain electrode 20 made of an Al-Si alloy is provided. A unit structure having an n source region 16, a source electrode 19, and the like above and below a p base region 14 as shown in the figure is called a cell structure. The cell structure is often polygonal or rectangular, and many such cell structures are juxtaposed in an actual MOSFET.

On the right side of FIG. 11, means for increasing the avalanche resistance is shown. That is, n
An n ⁺ contact region 7 is formed in the surface layer of drift layer 13, and auxiliary electrode 8 is in contact with n ⁺ contact region 7. A reverse series Zener diode 10 connected in reverse to the thick oxide film 9 on the surface of the n drift layer 13
Is provided, the auxiliary electrode 8 is connected to one end of the reverse series Zener diode 10, and the electrode taken out from the other end of the reverse series Zener diode 10 is a MOS.
It is connected to the gate electrode layer 18 of the FET.

In this structure, since the auxiliary electrode 8 is at the same potential as the drain electrode 20, when the high voltage applied to the drain electrode 20 exceeds the clamp voltage of the reverse series Zener diode 10, the high voltage and the clamp voltage Is applied to the MOSFET gate electrode layer 18 and the
Turn on the SFET to protect the device. However, in order to obtain the structure of FIG. 11, a window must be opened in the thick oxide film 9 to form the n ⁺ contact region 7.
In addition, in order to ensure the operation, the area of n ⁺ contact region 7 must be made large.

In view of the above problems, it is an object of the present invention to provide a MOS type semiconductor device which is reliable in operation and easy to manufacture and has improved avalanche withstand capability.

[0010]

In order to solve the above problems, a high breakdown voltage MOS type semiconductor device according to the present invention has a first MOS type semiconductor element through which a main current flows and the same structure as the first MOS type semiconductor element. The second MO that passes a current smaller than the main current at
The S-type semiconductor element is provided on the same semiconductor substrate, the drain electrode of the first MOS type semiconductor element and the drain electrode of the second MOS type semiconductor element are common, and the gate electrode of the second MOS type semiconductor element has its drain Connected to the second MOS
A plurality of zener diodes connected in reverse series are provided between the source electrode of the semiconductor element and the gate electrode of the first MOS semiconductor element.

With this configuration, when an overvoltage is applied between the drain electrode and the gate electrode of the first MOS type semiconductor element, the second MOS type semiconductor element is turned on, and the current flows through the reverse series Zener. It is supplied to the gate electrode of the first MOS type semiconductor element through a diode (at least one set is only required to be in the opposite direction), turns on the first MOS type semiconductor element, protects the MOS type semiconductor device from overvoltage,
Increases breakdown strength.

In particular, it is preferable that a reverse-connected series Zener diode is provided between the gate electrode and the source electrode of the first MOS type semiconductor element (at least one set of the zener diode is required to be in the reverse direction). By doing so, when an overvoltage is applied between the gate electrode and the source electrode, the overvoltage can be bypassed through the Zener diode, and the thin gate insulating film and the like of the MOS semiconductor device can be protected from the overvoltage. .

Further, if a resistance is provided between the gate electrode and the source electrode of the first MOS type semiconductor device, when the gate electrode of the first MOS type semiconductor device floats due to disconnection or the like, The gate electrode can be protected from noise voltage. Furthermore, if both the first and second MOS semiconductor elements are IGBTs, since they are conductivity modulation elements, the area of the first MOS semiconductor element can be reduced.

Further, the first and second MOS type semiconductor elements are formed by opposing first and second main surfaces, a first conductivity type drift layer, and a first main surface of the first conductivity type drift layer. A second conductivity type base region formed on the side surface layer, a first conductivity type source region separated from the first conductivity type drift layer by the second conductivity type base region, On the surface of the second conductivity type base region sandwiched between the one conductivity type drift layer, the gate electrode layer provided via the gate insulating film, and the first conductivity type source region and the second conductivity type base region. A source electrode provided in common contact, a drain layer provided on the other side of the first conductivity type drift layer,
If it has a drain electrode provided on the second main surface in contact with the surface of the drain layer and a gate electrode provided in contact with the gate electrode layer, a vertical and planar type It becomes a MOS type semiconductor device, the utilization efficiency of the semiconductor substrate is high, and the application is wide as a power semiconductor device.

A first and a second MOS type semiconductor element have opposing first and second main surfaces, a first conductivity type drift layer having a high specific resistance, and a first main type drift layer of the first conductivity type drift layer. A second conductivity type base region formed in the surface layer on the side of the surface, a first conductivity type source region separated from the first conductivity type drift layer by the second conductivity type base region, and a first conductivity type source region A trench dug deeper than the second conductivity type base region so that the first conductivity type base region is exposed to the inner wall, a gate electrode layer formed in the trench via a gate insulating film, a first conductivity type source region and a second conductivity type base. A source electrode provided in common with the region, a drain layer provided on the other side of the first conductivity type drift layer, and a second main surface provided in contact with the surface of the drain layer. Provided in contact with the drain electrode and the gate electrode layer Assuming the those in which a gate electrode, the vertical in becomes MOS type semiconductor device of a trench gate type, further enhanced semiconductor substrate utilization efficiency, versatile as the power semiconductor device.

A thick field insulating film is disposed between the first and second MOS type semiconductor elements on the first main surface, and a part of the gate electrode layer of the second MOS type semiconductor element is formed by the field insulating film. Second MOS on the first major surface, extended up
A portion having an insulating film thinner than the field insulating film between the first conductive type drift layer and the gate electrode layer around the second conductive type base region of the semiconductor device.

In this case, the inversion layer is prevented from being formed under the thick field insulating film in the thin insulating film portion, and the second conductive type base of the first and second MOS type semiconductor elements is prevented. It is possible to suppress a current from flowing between the regions. In particular, it is assumed that the thin insulating film has substantially the same thickness as the gate insulating film. In this case, the gate insulating film can be formed at the same time when the gate insulating film is formed, so that the manufacturing process is not complicated.

The first and second main surfaces facing each other, the first conductivity type drift layer having high specific resistance, and the second conductive layer formed on the surface layer on the first main surface side of the first conductivity type drift layer. A conductivity type base region, a first conductivity type source region separated from the first conductivity type drift layer by the second conductivity type base region, and sandwiched between the first conductivity type source region and the first conductivity type drift layer. A gate electrode layer provided on the surface of the second conductivity type base region via a gate insulating film; and a source electrode provided in common contact with the first conductivity type source region and the second conductivity type base region. And a second conductivity type drain layer provided on the other side of the first conductivity type drift layer, a drain electrode provided on the second main surface in contact with the surface of the second conductivity type drain layer, and a gate. High breakdown strength with a gate electrode provided in contact with the electrode layer In an OS type semiconductor device, that is, a planar type vertical IGBT, a ballast resistance layer is provided between the first conductivity type drift layer and the second conductivity type drain layer, and the specific resistance of the ballast resistance layer is 0.05. ~
The thickness of the portion in the range of 1 Ω · cm is about 30 μm to 80 μm.
It is important to be in the range of μm.

Even in the case of a so-called trench gate type IGBT having a trench dug deeper than the base region of the second conductivity type so that the source region of the first conductivity type is exposed on the inner wall, the first conductivity type drift layer and the second conductivity type are formed. Resistance of the ballast resistance layer between the gate type drain layer and the drain layer is 0.05 to 1Ω.
It is important that the thickness of the part, which is in the range of cm, is in the range of about 30 μm to 80 μm.

In this case, it is considered that the ballast resistance layer acts as a resistance and has an effect of dispersing the avalanche current. When the specific resistance is too low or the thickness is too small, there is no action as a resistance, and when the specific resistance is too high or the thickness is too thick, the action as the resistance is sufficient, but the ON voltage increases. And other properties. In particular, the range of the specific resistance of the ballast resistance layer is in the range of 0.1 to 0.4 Ω · cm.

As a result of the experiment, the range of the specific resistance was
It is also suitable as a device, and has an avalanche withstand capability due to the action of dispersing the avalanche current. The ballast resistance layer may be of the first conductivity type, or may be composed of a portion of the first conductivity type in contact with the drift region and a portion of the second conductivity type in contact with the drain region.

In either case, the ballast resistor layer acts as a resistor to disperse the avalanche current. Opposite first and second main surfaces, the first conductivity type drift layer, and the second conductivity type base region formed on the surface layer on the first main surface side of the first conductivity type drift layer, A first conductivity type source region separated from the first conductivity type drift layer by the second conductivity type base region, and a second conductivity type base region sandwiched between the first conductivity type source region and the first conductivity type drift layer. A gate electrode layer provided on the surface with a gate insulating film interposed therebetween,
A source electrode provided in common contact with the first conductivity type source region and the second conductivity type base region; and a lower resistance than the first conductivity type drift layer provided on the other side of the first conductivity type drift layer. A first conductive type drain layer, a drain electrode provided on the second main surface in contact with the surface of the first conductive type drain layer, and a gate electrode provided in contact with the gate electrode layer. In a breakdown type MOS semiconductor device, that is, a planar type vertical MOSFET, a first conductive type ballast resistance layer is provided between the first conductive type drift layer and the first conductive type drain layer. Is a region that is not depleted even when a high voltage is applied when an avalanche breakdown occurs when the MOS type semiconductor device is in an off state, and the specific resistance range is approximately the same as the specific resistance of the first conductivity type drift layer. Under, moreover assumed thickness of the portion is 1/10 or more is about 1μm or more.

A so-called trench gate type MOSFET having a trench dug deeper than the second conductivity type base region so that the first conductivity type source region is exposed on the inner wall.
Also, a ballast resistance layer of the first conductivity type is provided between the drift layer of the first conductivity type and the source / drain layer of the first conductivity type, and the ballast resistance layer is provided when the MOS type semiconductor device is in the off state. This is a region that is not depleted even when avalanche breakdown occurs due to application of a high voltage, and the specific resistance range is equal to or less than the specific resistance of the drift layer of the first conductivity type, and more than 1/10 of the specific resistance. The thickness of the part is about 1μ
It is important to be at least m.

The thickness of the portion of the ballast resistance layer is １ ／ or less of the thickness of the drift layer of the first conductivity type. In such a case, the ballast resistance layer serves as a resistor, and seems to have an effect of dispersing the avalanche current. If the thickness is too small, there is no effect as a resistor. If the thickness is too large, the effect as a resistor is sufficient, but other characteristics such as an increase in on-resistance are affected.

[0025]

Embodiments of the present invention will be described below with reference to the drawings based on embodiments of the present invention. In the following examples, regions and layers bearing n and p mean regions and layers having electrons and holes as majority carriers, respectively. The first conductivity type is n-type and the second conductivity type is p-type. Although it is a type, it is also possible to reverse this.

Embodiment 1 FIG. 2A is a plan view of an IGBT chip according to a first embodiment of the present invention (hereinafter, referred to as Embodiment 1). Reference numeral 1 denotes a first MOS-type semiconductor element, which is a main IGBT section for switching a load current, and reference numeral 2 denotes a second MOS-type semiconductor element, which is an auxiliary IGBT section for improving the immunity. 3 is a reverse series Zener diode,
4 is a gate pad. 2B to 2D are modified examples in which the arrangement is changed. The same reference sign means the same thing. As described above, it is preferable that the second MOS type semiconductor element is disposed near the periphery of the chip, and the reverse series Zener diode 3 is disposed between the second MOS semiconductor element and the gate pad 4.

FIG. 3 is an equivalent circuit diagram of the IGBT of the first embodiment. Here, the names are similar to the MOSFETs. That is, the collector of the IGBT is called a drain and the emitter is called a source. Between the drain D and the gate G of the main IGBT section which is the first MOS type semiconductor element 1, the second M
An auxiliary IGBT section, which is an OS type semiconductor element 2, and a reverse series Zener diode 3 are connected in series. The drain d of the auxiliary IGBT section and the gate g of the auxiliary IGBT section are short-circuited. The reverse series zener diode array 3 is configured by connecting zener diodes connected in the reverse direction in multiple stages. Further, between the source S and the gate G of the main IGBT section, a Zener diode 5 and a resistor 6 connected in opposite directions are connected in parallel. The Zener diode 5 has a function of protecting the element by bypassing when an overvoltage is applied between G and S. (Therefore, since the characteristics of the Zener diode may be appropriately selected depending on the required overvoltage, the Zener diode 5 is not necessarily a pair. It need not be, but only need to have at least one pair of reverse zener diodes). Further, the resistor 6 functions to prevent high voltage noise or the like from being applied to the gate G due to disconnection of the gate lead or the like.

FIG. 4 shows the IGBT of the first embodiment shown in FIG.
FIG. 4 is an enlarged perspective plan view of the vicinity of an auxiliary IGBT portion of the chip. The ends of the Al electrodes are indicated by dotted lines, and the ends of the polycrystalline silicon layer are indicated by thick lines. The gate electrode layer 3 of the auxiliary IGBT part is formed so as to partially overlap the peripheral electrode 32 of the IGBT chip.
8, a polycrystalline silicon layer is patterned.
The auxiliary source electrode 39 of the auxiliary IGBT is in contact with the silicon substrate surface at the hatched portion. Further, the source electrode 39 of the auxiliary IGBT section is connected to one end of the reverse series Zener diode 3. The other end of the reverse series Zener diode 3 is connected to the gate pad 4 of the main IGBT section.

FIG. 1 is a sectional view taken along line AA of FIG. Near the left end of the figure is a main IGBT unit 1 that performs current switching. The structure of this part is a general IG
It is almost the same as BT. In other words, p base regions 24 separated from each other are formed in a surface layer on one surface side of n drift layer 23 having a high specific resistance, and are further formed in a part of p base region 24 in order to prevent latch-up of a parasitic thyristor. A p ⁺ well region 25 having a greater diffusion depth than the p base region 24 is formed overlapping. On the other surface side of n drift layer 23, n ⁺ buffer layer 2 having a lower resistance than n drift layer 23 is provided.
2, a p drain layer 21 is formed. On the surface layer of p base region 24, n emitter region 26 is selectively formed. Then, a gate electrode layer 28 made of polycrystalline silicon is provided on the surface of p base region 24 interposed between n emitter region 26 and n drift layer 23 via gate oxide film 27 to form an n-channel MOSFET. Have been. The surface on this side is covered with an insulating film 31 such as borophosphorus glass (BPSG), and the p base region 2
Contact holes are formed so that the source electrode 29 is in common contact with the surface of the 4 and n source regions 26 and that a metal gate electrode (not shown) is in contact with the gate electrode layer 28. On the surface of the p drain layer 21, a drain electrode 30 is provided. The source electrode 29 often extends above the gate electrode layer 28 with the insulating film 31 interposed therebetween as shown in the figure.

On the right side of the figure, a cross section of the auxiliary IGBT unit 2 is shown. The structure of this auxiliary IGBT unit 2 is
Substantially the same as the T section 1, an auxiliary p base region 34 is formed in the surface layer of the n drift layer 23. Further, in order to prevent the latch-up of the parasitic thyristor, the auxiliary p base region 3
4, an auxiliary p ⁺ well region 35 having a greater diffusion depth than the auxiliary p base region 34 is formed. An auxiliary n source region 36 is provided on the surface layer of the auxiliary p base region 34.
Are selectively formed. An auxiliary gate electrode layer 38 made of polycrystalline silicon is provided on a surface of an auxiliary p base region 34 interposed between the auxiliary n source region 36 and the n drift layer 23 with an auxiliary gate oxide film 37 interposed therebetween. A type MOSFET is configured. The surface on this side is covered with an insulating film 31 such as boron phosphorus glass (BPSG), and the auxiliary p base region 34 and the auxiliary n source region 3
A contact hole is formed so that the auxiliary source electrode 39 is in common contact with the surface of the substrate 6. The other surface side of n drift layer 23 is common to the main IGBT portion.

A series Zener diode array 3 is formed on a thick oxide film 33 between the main IGBT 1 and the auxiliary IGBT 2. In this cross-sectional view, the peripheral electrode 32 is connected to the auxiliary gate electrode layer 38, the auxiliary source electrode 39 is connected to one end of the series Zener diode array 3, It can be seen that the electrode taken out from the other end is connected to the gate pad 4 of the main IGBT unit 1.

The IGBT of Example 1 is an element for 600 V, and has a specific resistance of 0.2 Ω · c as an n ⁺ buffer layer 22 on a p substrate having a specific resistance of 0.01 Ω · cm and a thickness of 500 μm.
As the n layer having a thickness of 30 μm and the n drift layer 23, a wafer having a specific resistance of 40Ω · cm and an n layer having a thickness of about 50 μm epitaxially grown was used. The subsequent process is
The IGBT can be manufactured in almost the same process as that of the conventional IGBT only by slightly changing the mask or the like. The main IGBT section and the auxiliary IGBT section may have the same dimensions, and can be manufactured simultaneously. That is, the main and auxiliary p base regions 24 and 34, the main and auxiliary p ⁺ well regions 25 and 3
5 and the p region of the series Zener diode string 3 are formed by ion implantation and thermal diffusion of boron ions.
The auxiliary n source regions 26 and 36 and the n region of the series Zener diode row 3 were formed by ion implantation of arsenic ions or phosphorus ions and thermal diffusion. The series Zener diode array 3 uses a polycrystalline silicon layer formed by the same low-pressure CVD method as the main and auxiliary gate electrode layers 28 and 38.
The ends of the main and auxiliary p base regions 24 and 34 and the main and auxiliary n source regions 26 and 36 are connected to the main and auxiliary gate electrode layers 28 and 38, respectively.
Are formed as a part of a mask and are positioned, and the intervals are determined by the respective lateral diffusions. main,
The auxiliary source electrodes 29 and 39 and the gate electrode are formed by sputtering of an Al alloy and subsequent photolithography, and the drain electrode 30 is formed by depositing three layers of Ti / Ni / Au by sputtering for soldering to a metal substrate. doing.

As an example of the dimensions of each part, the diffusion depth of the main and auxiliary p ⁺ well regions 25 and 35 is 6 μm, the diffusion depth of the main and auxiliary p base regions 24 and 34 is 2 μm, and the main and auxiliary n source regions 26. , 36 have a diffusion depth of 0.4 μm. The thickness of the main and auxiliary gate insulating films 27 and 37 is 25 n
m, the thickness of the polycrystalline silicon gate electrode layers 28 and 38, and the thickness of the insulating film 31 are all 1 μm.
The thickness of 39 is about 5 μm. The series Zener diode array 3 has a width of 100 μm.

The IGBT of the first embodiment thus formed
The operation of will be described next. The main source electrode 29 is grounded, and the drain electrode 30 is connected to a power supply via an inductive load. As described above, when the IGBT is turned off from on, the voltage applied to the drain electrode 30 increases due to the energy stored in the inductance. At this time, the voltage of the drain electrode 30 is also applied to the auxiliary gate electrode layer 38 through the peripheral electrode 32. On the other hand, auxiliary IGB
The auxiliary source electrode 39 of the T section 2 is fixed at a voltage higher by the voltage specified by the clamp voltage of the reverse series Zener diode 3. When the voltage of the drain electrode 30 exceeds the clamp voltage, the auxiliary IGBT unit 2 turns on. The series Zener diode array 3 has a Zener voltage of about 7
Approximately 50 stages of V zener diode pairs were connected in series.

When the auxiliary IGBT unit 2 is turned on, the current flows through the series Zener diode string 3 and the main IGBT unit 1
To turn on the main IGBT unit 1. In this manner, the energy stored in the inductance is released through the entire main IGBT unit 1. As in the case of the IGBT of the first embodiment, the current flowing through the auxiliary IGBT unit 2 is used to protect the element when an overvoltage is applied.
If the current is supplied to the gate electrode layer 28 of the GBT portion 1, a current can flow using the conductivity modulation, so that a large current can be supplied in a small area and the main IGBT portion 1 can be supplied.
Can be quickly turned on, and the avalanche resistance increases.

Although not shown in the cross-sectional view of FIG.
It is easy to similarly integrate the gate-source Zener diode pair 5 and the resistor 6 shown in the equivalent circuit on the semiconductor substrate. In FIG. 1, there is a portion 33a in which a part of the thick oxide film 33 is dug down to bring the auxiliary gate electrode layer 38 closer to the silicon substrate surface layer. This is because an inversion layer is formed near the surface of the n drift layer below the thick oxide film 33 to suppress the current from flowing from the auxiliary p base region 34 and the p peripheral region 32a to the p base region 24. If the thin oxide film portion 33a has the same thickness as the gate oxide film 27, there is no need to particularly increase the number of steps. This portion is shown in an annular shape in FIG. It is preferable that the width of the portion below the auxiliary gate electrode layer 38 outside the annular portion is as narrow as possible.

In particular, in the IGBT of the first embodiment, the specific resistance of the n ⁺ buffer layer 22 is 0.2 Ω · cm and the thickness is 30 μm.
It is important to note that FIG. 5 shows n of the avalanche resistance.
⁺ Is a diagram showing the thickness dependency of the buffer layer. The horizontal axis is n
⁺ The thickness of the buffer layer and the vertical axis are the avalanche resistance per unit area. The avalanche withstand capability increases as the thickness of the n ⁺ buffer layer increases, but tends to saturate at 30 μm or more. For example, if an n ⁺ buffer layer having a thickness of 30 μm is used to realize an avalanche withstand voltage of 200 mJ, the chip area (more precisely, the area of the active region) can be 10 mm ² , whereas the n ⁺ buffer layer has a thickness of 10 μm. ⁺
It can be seen that the buffer layer requires a double chip area of 20 mm ² .

FIG. 6 is a diagram showing the specific resistance dependence of the avalanche withstand voltage of the n ⁺ buffer layer when the thickness of the n ⁺ buffer layer 22 is 30 μm. The horizontal axis represents the specific resistance of the n ⁺ buffer layer, and the vertical axis represents the avalanche resistance. In the experimental range, the larger the specific resistance of the n ⁺ buffer layer is, the more the avalanche withstand capacity tends to increase, though moderately.
It can be seen that it is good in the range of 0.1 to 0.4 Ω · cm.

When avalanche breakdown occurs due to application of a high voltage, the depletion layer should spread throughout the n drift layer and also cover the n ⁺ buffer layer. FIG.
As shown in FIG. 6, as the thickness of the n ⁺ buffer layer is larger,
The reason why the avalanche resistance increases as the specific resistance increases is considered that the n ⁺ buffer layer which is not depleted acts as a ballast resistance and acts to average the overall avalanche current.

The specific resistance of the n ⁺ buffer layer is set to 0.05
The effect of setting the thickness in the range of 1 to 1 Ω · cm and the thickness of 30 to 80 μm is not necessarily limited to the MOS type semiconductor device having the reverse series Zener diode as in the first embodiment. I was assured. [Embodiment 2] FIG. 7 is a partial sectional view of an IGBT according to a second embodiment of the present invention (hereinafter, referred to as Embodiment 2). Basically, it is the same as the first embodiment of FIG. 1, except that a p / n ⁺ buffer layer 22a is provided between the n drift layer 23a and the p drain layer 21a instead of a single conductivity type n ⁺ buffer layer. The difference is that they are sandwiched. The specific resistance of the p / n ⁺ buffer layer 22a was substantially the same as that of the n ⁺ buffer layer of Example 1. And
The p layer of the p / n ⁺ buffer layer 22a is a p drain layer 21a.
Lower concentration.

As described above, the dependence of the avalanche resistance on the buffer layer thickness was also examined for the IGBT having the p / n ⁺ buffer layer 22a, and the results were almost the same as those of the first embodiment. [Embodiment 3] FIG. 8 is a partial sectional view of an IGBT according to a third embodiment (hereinafter, referred to as Embodiment 3) of the present invention. Main IGBT
The point that a reverse series Zener diode is provided between the unit and the auxiliary IGBT is the same as that of the first embodiment of FIG. 1, but the structures of the main IGBT and the auxiliary IGBT are slightly different.

That is, the trench 40 is provided in a surface layer on one surface side of the n drift layer 43 having a high specific resistance.
A p base region 44 is formed on both sides of the trench 40, and an n source region 46 is formed on a surface layer of the p base region 44.
Is formed, and p base region 44 and n source region 46 are exposed on the inner surface of trench 40. The inside of the trench 40 is filled with a gate electrode layer 48 made of polycrystalline silicon via a gate oxide film 47 to form an n-channel MOSFET. The surface is covered with an insulating film 51 such as borophosphorus glass (BPSG), so that the source electrode 49 is in common contact with the surfaces of the p base region 44 and the n source region 46, and a metal gate electrode (not shown). A contact hole is formed such that the contact hole comes into contact with the gate electrode layer 48. On the surface of the p drain layer 41, a drain electrode 50 is provided. The source electrode 49 often extends above the gate electrode layer 48 with the insulating film 51 interposed therebetween as shown in the figure.

Similarly, the auxiliary IGBT portion is an IGBT in which the auxiliary gate electrode layer 58 is filled in the trench via the auxiliary gate oxide film 57. Since such a trench gate IGBT can increase the cell density, it tends to be frequently used as a power semiconductor device. In this embodiment, the drain electrode 70 is formed similarly to the IGBT of the first embodiment.
Is connected to the auxiliary gate electrode layer 58, the auxiliary source electrode 59 is connected to one end of the series Zener diode array 60, and the electrode extracted from the other end of the series Zener diode array 60 is It is connected to the gate electrode layer 48 of the IGBT section 1.

Therefore, the operation is the same, and the auxiliary IGBT
When the section is turned on, the current is supplied to the gate electrode layer 48 of the main IGBT section 1 through the series Zener diode array 60 to turn on the main IGBT section. Since a current can flow using conductivity modulation, a large current can be supplied in a small area, the main IGBT portion can be quickly turned on, and the avalanche withstand capability increases.

[Embodiment 4] FIG. 9 shows a fourth embodiment (hereinafter referred to as Embodiment 4) of the present invention in which a semiconductor device is a MOSF.
It is a partial sectional view of an example of ET. The vicinity of the left end of the figure is an active region of the main MOSFET section that performs current switching. The structure of this active region is almost the same as a general MOSFET. That is, the n drift layer 63 having a high specific resistance
P base regions 64 separated from each other on the surface layer on one side of
Is formed, and an n source region 66 is selectively formed on the surface layer of p base region 64. n drift layer 63
There is an n ⁺ drain layer 61 on the other surface side. A gate electrode layer 68 made of polycrystalline silicon is provided on the surface of p base region 64 sandwiched between n source region 66 and n drift layer 63 via gate oxide film 67. The surface on this side is covered with an insulating film 71 of phosphor glass (PSG) or the like, so that the main source electrode 69 is in common contact with the surfaces of the p base region 64 and the n source region 66, and in part, A contact hole is formed so that a gate electrode (not shown) contacts the gate electrode layer 68. n
^On the surface of the ⁺ drain layer 61, a drain electrode 70 is provided. The source electrode 69 has an insulating film 71 as shown in FIG.
, And often extends above the gate electrode layer 68.

An auxiliary MOSFET section is formed on the right side of the drawing. The structure of this auxiliary MOSFET is
This is almost the same as the FET, in which an auxiliary p base region 74 is formed on the surface layer of the n drift layer 63, and an auxiliary n source region 76 is selectively formed on the surface layer of the auxiliary p base region 74. An auxiliary gate electrode layer 78 made of polysilicon is provided on a surface of an auxiliary p base region 74 interposed between an auxiliary n source region 76 and an n drift layer 63 via an auxiliary gate oxide film 77 to provide an n channel Type M
An OSFET is configured. The surface on this side is covered with an insulating film 71 made of phosphor glass (PSG) or the like, and a contact hole is formed so that the auxiliary emitter electrode 79 is in common contact with the surfaces of the auxiliary p base region 74 and the auxiliary n source region 76. It is open. The other surface side of n drift layer 63 is the main MO
It is common with the SFET section.

A series Zener diode array 80 is formed on the thick oxide film 73 between the main MOSFET section and the auxiliary MOSFET section. In this cross-sectional view, the peripheral electrode 72 is connected to the auxiliary gate electrode layer 78, the auxiliary source electrode 79 is connected to one end of the series Zener diode array 80, The electrode taken out from the other end is the main I
It can be seen that it is connected to the gate electrode layer 69 in the GBT section.

The MOSFET according to the fourth embodiment has a 60 V
Element, specific resistance 0.004Ω · cm, thickness 350
As an n drift layer 63 on a μm n-type silicon substrate,
A wafer on which an n layer having a specific resistance of 0.5 Ω · cm and a thickness of about 7.5 μm was epitaxially grown was used. The rest of the process is just a small change, such as changing the mask,
It can be manufactured in almost the same process as a conventional MOSFET. That is, the main and auxiliary p base regions 64 and 74 and the p region of the series Zener diode array 80 are formed by ion implantation and thermal diffusion of boron ions, and the main and auxiliary n source regions 66 and 76 and the series Zener diode array 80 are formed. Was formed by ion implantation of arsenic ions or phosphorus ions and thermal diffusion. Series Zener diode array 8
0 is the same reduced pressure CV as that of the main and auxiliary gate electrode layers 68 and 78.
A polycrystalline silicon layer by the D method was used. Main and auxiliary p base regions 64 and 74, main and auxiliary n source regions 66 and 76
Are formed by using the main and auxiliary gate electrode layers 68 and 78 made of polycrystalline silicon on a semiconductor substrate as masks, and the intervals are determined by their respective lateral diffusions. The main and auxiliary source electrodes 69 and 79 and the gate electrode are formed by sputtering of an Al alloy and subsequent photolithography, and the drain electrode 70 is formed by depositing three layers of Ti / Ni / Au by sputtering for soldering to a metal substrate. It is formed.

As an example of the dimensions of each part, the diffusion depth of the main and auxiliary p base regions 64 and 74 is 3 μm, the diffusion depth of the main and auxiliary p ⁺ contact regions 65 and 75 is 0.6 μm, and the main and auxiliary n source The diffusion depth of the regions 66 and 76 is 0.3
μm. The thickness of the main and auxiliary gate insulating films 67 and 77 is 25 nm, the thickness of the polycrystalline silicon layer of the main and auxiliary gate electrode layers 68 and 78 and the thickness of the insulating film 71 are both 1 μm, and the thickness of the main and auxiliary source electrodes 69 and 79. The length is about 5 μm.

The MOSF of the fourth embodiment thus formed
Next, the operation of the ET will be described. The main source electrode 69 is grounded, and the drain electrode 70 is connected to a power supply via an inductive load. As described above, when the MOSFET is turned off from on, the voltage applied to the drain electrode 70 increases due to the energy stored in the inductance. At this time, the voltage of the drain electrode 70 is
2 through the auxiliary gate electrode layer 78 of the auxiliary MOSFET section
Is applied to On the other hand, the auxiliary source electrode 79 of the auxiliary IGBT
Is fixed at a voltage higher than the source electrode 69 of the main MOSFET by the voltage specified by the clamp voltage of the series Zener diode array 80, and when the difference between this voltage and the collector voltage exceeds a certain value, the auxiliary MOSFET is turned on. become.

When the auxiliary MOSFET is turned on, its current flows through the series Zener diode array 80 and the main MOSFET
The main IGBT is supplied to the gate electrode layer 68 in the T section to turn on the main IGBT. In this way, the energy stored in the inductance is released. MOSFE of Embodiment 4
When the overvoltage is applied, as shown in FIG.
If a current is supplied to the gate electrode layer 68 of the SFET through the auxiliary MOSFET, the protection operation is reliably realized, and the avalanche withstand capability is increased.

In FIG. 9, there is a portion 73a in which a part of the thick oxide film 73 is dug down to bring the auxiliary gate electrode layer 78 closer to the silicon substrate surface layer. This is because an inversion layer is formed in the surface layer of the silicon substrate under the thick oxide film, and current is suppressed from flowing from the auxiliary p base region 74 and the p peripheral region 72a to the p base region 64.

In particular, in the MOSFET of the fourth embodiment,
It is also important that the thickness of the n drift layer is 7.5 μm. FIG. 10 is a diagram showing the dependency of the avalanche resistance on the thickness of the n drift layer. The horizontal axis is the thickness of the n drift layer,
The vertical axis is the avalanche resistance per unit area. n
As the thickness of the buffer layer is larger, the avalanche withstand capability is increased, but is substantially saturated at 7 μm or more. This abscissa also indicates a change in the thickness of the non-depleted n drift layer when the reading is changed.

The MOSFET of the fourth embodiment is rated at 60 V. When the specific resistance is 0.5 Ω · cm, the depletion layer expands by about 3 μm at 60 V. The diffusion depth of the p base region is 3 μm
Therefore, in the case of the n drift layer having a very small avalanche resistance and a thickness of 6 μm, there is almost no depleted portion. Conversely, if the thickness of the n-drift layer that is not depleted is 1 μm or more, the avalanche resistance is large and stable.

The reason why the thickness of the n-drift layer is large and the avalanche withstand capability is large is that the n-drift layer that is not depleted, that is, the ballast layer acts as a resistor to average the entire avalanche current. It is thought to be. The high-resistance layer is, for example, in a range until the specific resistance becomes 1/10 of that of the n drift layer. Therefore, in order to realize a high avalanche withstand capability, the thickness of the high-resistance ballast layer that does not deplete at the time of avalanche breakdown should be 0.5 μm or more.

The thickness of the high-resistance ballast layer is 0.5
Subsequent experiments confirmed that the effect of having a thickness of not less than μm is not necessarily limited to the MOS semiconductor device having the reverse series Zener diode as in the first embodiment. As described above, the vertical IGBT and the vertical MOSFET
However, the present invention is also applicable to an insulated gate thyristor and the like. Furthermore, if the element incorporates a plurality of inventions, the respective effects can be obtained repeatedly, and a MOS type semiconductor device having more excellent characteristics can be obtained.

The high breakdown voltage MOS type semiconductor device of the present invention can be used for driving a solenoid valve, a motor, etc.
It is excellent as a switching element of a switching power supply such as a DC converter. In particular, in the IGBT of the present invention, a motor vehicle used under severe conditions (a module is directly mounted on an engine with a common ground potential and a sudden temperature change such as -30 to 180 degrees or various noises) is used. It can be applied to a main switching element of a drive circuit of an ignition coil, and has a remarkable effect.

[0058]

As described above, the high breakdown voltage MOS type semiconductor device according to the present invention has a first MOS type semiconductor element through which a main current flows, and a structure smaller than the main current with the same structure as the first MOS type semiconductor element. A second MOS type semiconductor element for passing a current is provided on the same semiconductor substrate, and a drain electrode of the first MOS type semiconductor element and a drain electrode of the second MOS type semiconductor element are common, and a second MOS type semiconductor element is provided. A plurality of zener diode pairs connected in series in a reverse direction between the source electrode of the second MOS type semiconductor element and the gate electrode of the first MOS type semiconductor element. By this, when an overvoltage is applied between the drain electrode and the gate electrode of the first MOS type semiconductor element, the second MOS type semiconductor element turns on,
The current is supplied to the gate electrode of the first MOS semiconductor device through the reverse series Zener diode, and the first M
By turning on the OS type semiconductor element, the avalanche resistance of the MOS type semiconductor device is greatly increased.

In particular, if a reverse series Zener diode pair and a resistor are provided between the gate electrode and the source electrode of the first MOS type semiconductor device, the device can be operated even when an overvoltage is applied or the gate electrode is disconnected. Can be protected. M
As an OS type semiconductor element, it is applied to a planar type or trench gate type vertical MOSFET or IGBT.

In particular, in a vertical IGBT, the specific resistance between the first conductivity type drift layer and the second conductivity type drain layer is 0.5.
The thickness of the part in the range of 0.5 to 1 Ω · cm is about 30 μm
The examples show that the avalanche withstand capability can be greatly increased by providing a ballast resistor layer of ８０80 μm. Further, in the vertical MOSFET, depletion occurs even when a high voltage is applied between the first conductivity type drift layer and the first conductivity type drain layer when the MOS type semiconductor device is in an off state and avalanche breakdown occurs. This ballast resistance layer is a region where the specific resistance is not more than the specific resistance of the first conductivity type drift layer, and the thickness of the portion where the specific resistance is 1/10 or more is about 1 μm or more. It has been shown that the avalanche withstand capability can be greatly increased by the provision.

MOS frequently used as switching element
In recent years, MOS-type semiconductor devices, which are switching elements, have been subjected to more and more severe stress due to simplification of circuits such as elimination of snubber circuits and the like and miniaturization of devices in switching circuits. In such a situation, there is a great contribution of the present invention for improving the avalanche resistance.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view of an IGBT according to a first embodiment of the present invention.

FIG. 2A is a plan view of an IGBT chip according to a first embodiment, and FIGS. 2B, 2C, and 2D are plan views of modifications thereof.

FIG. 3 is an equivalent circuit diagram of the IGBT according to the first embodiment.

FIG. 4 is an enlarged view of an auxiliary element portion of the IGBT chip according to the first embodiment;

FIG. 5 is a view showing the dependency of avalanche resistance on the thickness of an n ⁺ buffer layer.

FIG. 6 is a graph showing the dependency of avalanche resistance on the specific resistance of an n ⁺ buffer layer.

FIG. 7 is a partial cross-sectional view of an IGBT according to a second embodiment of the present invention.

FIG. 8 is a partial cross-sectional view of an IGBT according to a third embodiment of the present invention.

FIG. 9 is a partial cross-sectional view of a MOSFET according to a fourth embodiment of the present invention.

FIG. 10 is a diagram showing the dependency of avalanche resistance on the thickness of an n drift layer.

FIG. 11 is a partial cross-sectional view of a conventional MOSFET.

[Explanation of symbols]

1 First MOS type semiconductor device or main I
GBT section 2 Second MOS type semiconductor element or auxiliary IGBT section 3 Reverse series Zener diode 4 Gate pad 5 Reverse Zener diode 6 Resistance 7 n ⁺ Contact region 8 Auxiliary electrode 9 Oxide film 10, 60, 80 Reverse series Zener diode 11, 61 n ⁺ drain layer 13, 23, 23a, 43, 63 n drift layer 14, 24, 44, 64 p base region 15, 65 p + contact region 16, 26, 46, 66 n source region 17, 27, 47, 67 Gate oxide film 18, 28, 48, 68 Gate electrode layer 19, 29, 49, 69 Source electrode 20, 30, 50, 70 Drain electrode 21, 21a, 41p Drain layer 22, 42n ⁺ buffer layer 22a p / n ⁺ buffer layer 25, 45 p ⁺ well region 31, 51, 71 insulating film 32,52,7 Peripheral electrode 33,53,73 oxide film 33a, 53a, 73a thin oxide portion 34, 54, 74 auxiliary p base region 35 the auxiliary p ⁺ well region 36,56,76 auxiliary n source regions 37,57,77 assist gate oxide Film 38, 58, 78 auxiliary gate electrode layer 39, 59, 79 auxiliary source electrode 40 trench 75 auxiliary contact region

Claims (20)

[Claims] A first MOS type semiconductor element for flowing a main current and a second MOS type semiconductor element for flowing a current smaller than the main current having the same structure as the first MOS type semiconductor element are provided on the same semiconductor substrate. A drain electrode of the first MOS-type semiconductor element and a drain electrode of the second MOS-type semiconductor element are common, and a gate electrode of the second MOS-type semiconductor element is connected to the drain electrode; A high breakdown voltage MOS type semiconductor device, comprising: a plurality of Zener diodes connected in series in a reverse direction between a source electrode of the element and a gate electrode of the first MOS type semiconductor element. 2. The high breakdown voltage MO according to claim 1, further comprising a reverse series Zener diode between the gate electrode and the source electrode of the first MOS type semiconductor device.
S-type semiconductor device. 3. The high breakdown voltage MOS type semiconductor device according to claim 1, wherein a resistance is provided between the gate electrode and the source electrode of the first MOS type semiconductor element. 4. A high breakdown voltage MO according to claim 1, wherein both the first and second MOS semiconductor elements are insulated gate bipolar transistors.
S-type semiconductor device. 5. A semiconductor device according to claim 1, wherein said first and second MOS type semiconductor elements have opposing first and second main surfaces, a first conductivity type drift layer, and a first main surface of said first conductivity type drift layer. A second conductivity type base region formed on the side surface layer, a first conductivity type source region separated from the first conductivity type drift layer by the second conductivity type base region, On the surface of the second conductivity type base region sandwiched between the one conductivity type drift layer, the gate electrode layer provided via the gate insulating film, and the first conductivity type source region and the second conductivity type base region. A source electrode provided in common contact, a drain layer provided on the other side of the first conductivity type drift layer, and a drain electrode provided on the second main surface in contact with the surface of the drain layer. And a gate electrode provided in contact with the gate electrode layer. Claims 1, characterized in Rukoto high ruggedness MOS semiconductor device according to any one of 4. 6. The first and second MOS semiconductor elements are opposed to each other by first and second main surfaces, a first conductivity type drift layer having a high specific resistance, and a first conductivity type drift layer. A second conductivity type base region formed in the surface layer on the one main surface side, a first conductivity type source region separated from the first conductivity type drift layer by the second conductivity type base region, A trench dug deeper than the second conductivity type base region so that the source region is exposed on the inner wall, a gate electrode layer formed in the trench via a gate insulating film, a first conductivity type source region and a second conductivity type A source electrode provided in common contact with the mold base region; a drain layer provided on the other side of the first conductivity type drift layer; and a second main surface provided in contact with the surface of the drain layer. Provided in contact with the drain electrode and the gate electrode layer High ruggedness MOS semiconductor device according to any one of claims 1 to 4, characterized in that the one having a gate electrode. 7. A thick field insulating film is disposed between the first and second MOS type semiconductor elements on the first main surface, and a part of the gate electrode layer of the second MOS type semiconductor element is formed in the field. The second MOS on the first main surface is extended on the insulating film
7. The semiconductor device according to claim 5, further comprising a portion having an insulating film thinner than the field insulating film between the first conductive type drift layer and the gate electrode layer around the second conductive type base region of the semiconductor device. 2. A high breakdown voltage MOS type semiconductor device according to item 1. 8. The high breakdown voltage MOS type semiconductor device according to claim 7, wherein said thin insulating film has substantially the same thickness as a gate insulating film. 9. The first and second main surfaces facing each other, the first conductivity type drift layer having a high specific resistance, and the surface layer on the first main surface side of the first conductivity type drift layer. A second conductivity type base region, a first conductivity type source region separated from the first conductivity type drift layer by the second conductivity type base region, and sandwiched between the first conductivity type source region and the first conductivity type drift layer. A gate electrode layer provided on the surface of the second conductive type base region provided via a gate insulating film, and provided in common contact with the first conductive type source region and the second conductive type base region. A source electrode, a second conductivity type drain layer provided on the other side of the first conductivity type drift layer, and a drain electrode provided on the second main surface in contact with the surface of the second conductivity type drain layer. High withstand voltage having a gate electrode provided in contact with the gate electrode layer In the OS type semiconductor device, a ballast resistance layer is provided between the first conductivity type drift layer and the second conductivity type drain layer, and the specific resistance of the ballast resistance layer is in a range of 0.05 to 1 Ω · cm. A high breakdown voltage MOS type semiconductor device, wherein a thickness of a certain portion is in a range of about 30 μm to 80 μm. 10. A first MOS type semiconductor element for flowing a main current and a second MOS type semiconductor element having the same structure as the first MOS type element and flowing a smaller current than the main current are formed on the same semiconductor substrate. The first and second MOS type semiconductor elements are provided so that the first and second main surfaces oppose each other, the first conductivity type drift layer having a high specific resistance, and the first main type drift layer of the first conductivity type drift layer. A second conductivity type base region formed in the surface layer on the side of the surface,
A first conductivity type source region separated from the first conductivity type drift layer by the second conductivity type base region, and a second conductivity type base region sandwiched between the first conductivity type source region and the first conductivity type drift layer A gate electrode layer provided on the surface of the substrate via a gate insulating film, a source electrode provided in common contact with the first conductivity type source region and the second conductivity type base region, and a first conductivity type. A second conductivity type drain layer provided on the other side of the drift layer, a drain electrode provided on the second main surface in contact with the surface of the second conductivity type drain layer, and in contact with the gate electrode layer In the high breakdown voltage MOS type semiconductor device having the provided gate electrode, a ballast resistance layer is provided between the first conductivity type drift layer and the second conductivity type drain layer. Is 0.05 to 1Ω · c About the thickness of the portion in the range of 30
5. The method according to claim 4, wherein the distance is in the range of [mu] m to 80 [mu] m.
The high breakdown voltage MOS type semiconductor device as described in the above. 11. A first conductive type drift layer having a high specific resistance, and a first conductive type drift layer having a high specific resistance and a surface layer on the first main surface side of the first conductive type drift layer. A second conductive type base region, a first conductive type source region separated from the first conductive type drift layer by the second conductive type base region, and a second conductive type source region such that the first conductive type source region is exposed to the inner wall. A trench that is dug deeper than the mold base region, a gate electrode layer formed in the trench via a gate insulating film, and a first conductivity type source region and a second conductivity type base region. A source electrode, a second conductivity type drain layer provided on the other side of the first conductivity type drift layer, and a drain electrode provided on the second main surface in contact with the surface of the second conductivity type drain layer. And a gate provided in contact with the gate electrode layer In the high breakdown voltage MOS type semiconductor device having a pole, the ballast resistance layer is provided between the first conductivity type drift layer and a second conductivity type drain layer,
The ballast resistance layer has a specific resistance of 0.05 to 1 Ω · cm.
Characterized in that the thickness of the portion in the range of (1) is in the range of about 30 μm to 80 μm. 12. A first MOS type semiconductor element for flowing a main current and a second MOS type semiconductor element having the same structure as the first MOS type element and flowing a smaller current than the main current are formed on the same semiconductor substrate. The first and second MOS type semiconductor elements are provided so that the first and second main surfaces oppose each other, the first conductivity type drift layer having a high specific resistance, and the first main type drift layer of the first conductivity type drift layer. A second conductivity type base region formed in the surface layer on the side of the surface,
A first conductivity type source region separated from the first conductivity type drift layer by the second conductivity type base region, and a trench dug deeper than the second conductivity type base region so that the first conductivity type source region is exposed on the inner wall. A gate electrode layer formed in the trench via a gate insulating film; a source electrode provided in common contact with the first conductivity type source region and the second conductivity type base region; A second conductivity type drain layer provided on the other side of the mold drift layer, a drain electrode provided on the second main surface in contact with the surface of the second conductivity type drain layer, and a gate electrode layer. In the high breakdown voltage MOS type semiconductor device having the gate electrode provided in the above manner, a ballast resistance layer is provided between the first conductivity type drift layer and the second conductivity type drain layer. Usually There high ruggedness MOS semiconductor device according to claim 4, wherein the thickness of the portion in the range of 0.05~1Ω · cm is in the range of about 30Myuemu～80myuemu. 13. The range of the specific resistance of the ballast resistance layer is as follows:
The high breakdown strength MO according to any one of claims 9 to 12, wherein the MO is in a range of 0.1 to 0.4 Ω · cm.
S-type semiconductor device. 14. The high breakdown voltage MOS type semiconductor device according to claim 9, wherein said ballast resistance layer is of a first conductivity type. 15. The ballast resistor layer according to claim 9, wherein said ballast resistance layer comprises a first conductivity type portion in contact with said drift region and a second conductivity type portion in contact with said drain region. High breakdown voltage MOS type semiconductor device. 16. A first conductive type drift layer opposed to a first conductive type drift layer and a second conductive type formed on a surface layer of the first conductive type drift layer on the first main surface side. A base region, a first conductivity type source region separated from the first conductivity type drift layer by the second conductivity type base region, and a second conductivity type sandwiched between the first conductivity type source region and the first conductivity type drift layer. On the surface of the conductive type base region, a gate electrode layer provided via a gate insulating film, a source electrode provided in common contact with the first conductive type source region and the second conductive type base region, A first conductive type drain layer having a lower resistance than the first conductive type drift layer provided on the other side of the first conductive type drift layer, and a second main surface in contact with the surface of the first conductive type drain layer. The provided drain electrode and the gate provided in contact with the gate electrode layer In the high breakdown voltage MOS type semiconductor device having a pole, a first conductivity type ballast resistance layer is provided between the first conductivity type drift layer and the first conductivity type drain layer, and the ballast resistance layer is a MOS type. It is a region that is not depleted even when avalanche breakdown occurs when a high voltage is applied when the semiconductor device is in an off state, and a specific resistance range is equal to or less than the specific resistance of the first conductivity type drift layer, and The thickness of the part which is 1/10 or more is about 1μ
m or more, and a high breakdown voltage MOS semiconductor device. 17. A semiconductor device comprising: a first MOS type semiconductor element for flowing a main current; and a second MOS type semiconductor element having the same structure as the first MOS type semiconductor element and flowing a smaller current than the main current. The first and second MOS type semiconductor elements are provided, and opposing first and second main surfaces, a first conductivity type drift layer, and a first main surface side of the first conductivity type drift layer. A second conductivity type base region formed in the surface layer; a first conductivity type source region separated from the first conductivity type drift layer by the second conductivity type base region; a first conductivity type source region; A gate electrode layer provided on the surface of the second conductivity type base region interposed between the mold drift layer and the gate insulating film, and shared by the first conductivity type source region and the second conductivity type base region. A source electrode provided in contact with the first conductivity type drift layer A first conductivity type drain layer having a lower resistance than the first conductivity type drift layer provided on the other side, and a drain electrode provided on the second main surface in contact with the surface of the first conductivity type drain layer, In a high breakdown voltage MOS type semiconductor device having a gate electrode provided in contact with a gate electrode layer, a ballast resistance layer of a first conductivity type is provided between the first conductivity type drift layer and the first conductivity type drain layer. This ballast resistance layer is a region that is not depleted even when a high voltage is applied and an avalanche breakdown occurs when the MOS type semiconductor device is in an off state, and the specific resistance range is the first conductivity type drift. 2. A high breakdown voltage MOS according to claim 1, wherein the thickness of a portion which is about the same as or less than the specific resistance of the layer and which is 1/10 or more thereof is about 1 μm or more.
Type semiconductor device. 18. The first and second main surfaces opposed to each other, the first conductivity type drift layer having a high specific resistance, and the surface layer on the first main surface side of the first conductivity type drift layer. A second conductive type base region, a first conductive type source region separated from the first conductive type drift layer by the second conductive type base region, and a second conductive type source region such that the first conductive type source region is exposed to the inner wall. A trench that is dug deeper than the mold base region, a gate electrode layer formed in the trench via a gate insulating film, and a first conductivity type source region and a second conductivity type base region. Source electrode, the first conductivity type drain layer provided on the other side of the first conductivity type drift layer, the first conductivity type drain layer having a lower resistance than the drift layer, and in contact with the surface of the first conductivity type drain layer. A drain electrode provided on the second main surface, and a gate In a high breakdown voltage MOS type semiconductor device having a gate electrode provided in contact with an extreme layer, a ballast resistance layer of a first conductivity type is provided between the first conductivity type drift layer and the first conductivity type drain layer. This ballast resistance layer is a region that is not depleted even when a high voltage is applied and an avalanche breakdown occurs when the MOS type semiconductor device is in an off state, and the specific resistance range is the first conductivity type drift layer. Less than or equal to the specific resistance of
A high breakdown voltage MOS type semiconductor device, characterized in that the thickness of a portion which is / 10 or more is about 1 μm or more. 19. A first MOS type semiconductor element for flowing a main current and a second MOS type semiconductor element having the same structure as the first MOS type element and flowing a smaller current than the main current are provided on the same semiconductor substrate. The first and second MOS type semiconductor elements are provided so that the first and second main surfaces oppose each other, the first conductivity type drift layer having a high specific resistance, and the first main type drift layer of the first conductivity type drift layer. A second conductivity type base region formed in the surface layer on the side of the surface,
A first conductivity type source region separated from the first conductivity type drift layer by the second conductivity type base region, and a trench dug deeper than the second conductivity type base region so that the first conductivity type source region is exposed on the inner wall. A gate electrode layer formed in the trench via a gate insulating film; a source electrode provided in common contact with the first conductivity type source region and the second conductivity type base region; A first conductivity type drain layer having a lower resistance than the first conductivity type drift layer provided on the other side of the mold drift layer, and provided on the second main surface in contact with the surface of the first conductivity type drain layer. In a high breakdown voltage MOS semiconductor device having a drain electrode and a gate electrode provided in contact with a gate electrode layer, a first conductivity type MOS transistor is disposed between the first conductivity type drift layer and the first conductivity type drain layer. Ballast The ballast resistance layer is a region that is not depleted even when a high voltage is applied and an avalanche breakdown occurs when the MOS type semiconductor device is in an off state, and the specific resistance range is the first conductive layer. 2. A high breakdown voltage MOS type semiconductor device according to claim 1, wherein the thickness of a portion which is equal to or less than the specific resistance of the mold drift layer and which is 1/10 or more thereof is about 1 μm or more. 20. The height according to claim 16, wherein the thickness of the ballast resistance layer is not more than half the thickness of the first conductivity type drift layer. Destruction resistant MOS semiconductor device.