WO2016104825A1 - Power semiconductor device having over-voltage protection diode element embedded therein and manufacturing method therefor - Google Patents

Power semiconductor device having over-voltage protection diode element embedded therein and manufacturing method therefor Download PDF

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Publication number
WO2016104825A1
WO2016104825A1 PCT/KR2014/012777 KR2014012777W WO2016104825A1 WO 2016104825 A1 WO2016104825 A1 WO 2016104825A1 KR 2014012777 W KR2014012777 W KR 2014012777W WO 2016104825 A1 WO2016104825 A1 WO 2016104825A1
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region
type semiconductor
zener diode
impurity
semiconductor device
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PCT/KR2014/012777
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French (fr)
Korean (ko)
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강이구
강태영
경신수
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극동대학교 산학협력단
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Priority to PCT/KR2014/012777 priority Critical patent/WO2016104825A1/en
Publication of WO2016104825A1 publication Critical patent/WO2016104825A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body

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  • the present invention relates to a power semiconductor device incorporating a transient voltage protection diode element and a method of manufacturing the same.
  • power semiconductor devices used in semiconductor integrated circuits formed on semiconductor substrates may be damaged by internal elements being destroyed by pulsed high voltages generated by electrostatic discharge (ESD) and surge voltages flowing from the outside.
  • ESD electrostatic discharge
  • the power semiconductor device must be protected from breakdown caused by excessive voltage inflow.
  • the transient voltage protection device is included through a process of wiring the protective diode or the transient voltage protection device by wiring in the package process for such transient voltage protection, or the ESD protection circuit is embedded in the control IC. The method was also adopted.
  • the present invention provides a method for manufacturing a power semiconductor device for efficiently embedding and manufacturing a transient voltage protection device capable of protecting a chip from a transient voltage during a main cell manufacturing process.
  • a polysilicon layer formed under the boundary region of the gate pad including the insulating film is formed, the polysilicon layer
  • a multistage zener diode is formed in which a first type semiconductor region in which a first type semiconductor impurity is heavily doped and a second type semiconductor region in which a second type semiconductor impurity is lowly doped is formed in alternating multistage series.
  • One end is connected to one gate of a power MOSFET cell formed in an active cell region adjacent to the gate pad region and the other end of the multi-stage zener diode region is connected to be connected to a source electrode of the power MOSFET cell
  • a power semiconductor device incorporating a voltage protection diode element is provided.
  • a second insulating film is formed below the multi-stage zener diode, and the second insulating film has a thickness of 1.4 to 1.6 times the thickness of the gate insulating film of the power MOSFET cell.
  • the first type semiconductor impurity is a P ⁇ type semiconductor impurity
  • the second type semiconductor impurity is an N + type semiconductor impurity
  • the multistage zener diode has a zener diode in which N + type semiconductor impurity acts as a cathode. It is characterized in that the structure is connected in series of 3 to 5 stages in series.
  • the width of the first type semiconductor region is 3 ⁇ 4 ⁇ m
  • the width of the second type semiconductor region is characterized in that the 3.5 ⁇ 4.5 ⁇ m.
  • the first type semiconductor region is implanted with a P - type semiconductor impurity at a concentration of 2.9 to 3.1e14 cm -2
  • the second semiconductor region is implanted with an N + type semiconductor impurity at a concentration of 0.9-1.1e16 cm -2 . It features.
  • the first type semiconductor impurity is a P ⁇ type semiconductor impurity
  • the second type semiconductor impurity is an N + type semiconductor impurity
  • the multistage zener diode has a zener diode in which N + type semiconductor impurity acts as a cathode.
  • Type 4 structure connected in series the width of the first type semiconductor region is 3.5 ⁇ ⁇
  • the width of the second type semiconductor region is 4 ⁇ ⁇
  • the first type semiconductor region is formed of P - type semiconductor impurities. It is implanted at a concentration of 2.9 ⁇ 3.1e14 cm -2
  • the second semiconductor region is characterized in that the implanted N + -type semiconductor impurities at a concentration of 1.0e16 cm -2 .
  • the multi-stage zener diode is characterized in that formed in 0.3 ⁇ m height.
  • the first type semiconductor impurity is a P ⁇ type semiconductor impurity
  • the second type semiconductor impurity is an N + type semiconductor impurity
  • the multistage zener diode is a back to back type, wherein the N + type semiconductor impurity acts as a cathode.
  • + / P - / N + / P - / N + / P - is characterized in that it has a / N + structure - / N + / P.
  • a method of manufacturing a power semiconductor device comprising: (a) forming a first insulating film in a region where a multi-stage zener diode is formed; (b) forming a second insulating film in a region where the power MOSFET cell is formed; (c) forming a polysilicon layer on the first and second insulating films; (d) etching a central region of the polysilicon layer and the second insulating layer except for a gate region among regions where the power MOSFET cell is formed; (e) implanting a P ⁇ type semiconductor impurity using a first mask to form an anode region of the multi-stage zener diode in the P-body and the polysilicon layer of the power MOSFET; (f) implanting an impurity in the P + type semiconductor P- Body by using a second mask to form the P + Ohmic Contact area; (g) implanting N + -type semiconductor impurities using a third mask
  • the multi-stage zener diode is formed under the boundary region of the gate pad including the pad insulating film.
  • the anode region is characterized in that 3 to 5 are formed in the range of 3 ⁇ 4 ⁇ m width.
  • step (g) four to six cathode regions are formed in a width range of 3.5 to 4.5 ⁇ m.
  • the first insulating film is characterized in that the thickness of 1.4 ⁇ 1.6 times the second insulating film.
  • step (e) four anode regions are formed in a range of 3.5 ⁇ m in width, and a concentration of P ⁇ -type impurities is injected at 3.0e14 cm ⁇ 2 .
  • step (g) five cathode regions are formed in a range of 4 ⁇ m in width, and the concentration of N + impurity is 1.0e16 cm ⁇ 2 .
  • a power semiconductor device and a method of manufacturing the same may be provided to include a device for transient voltage protection within a power semiconductor device chip size.
  • the transient voltage protection device inside the cell of the power semiconductor device, it is possible to reduce the additional process for the separate ESD protection device, thereby reducing the wiring process and parasitic parameters accordingly. It has an effect.
  • a transient voltage protection device that can protect the power semiconductor device from the transient voltage therein has the effect of increasing the space efficiency and reduce the overall packaging size.
  • the method of performing the power MOSFET active cell manufacturing process and the process of forming the transient voltage protection diode element in the same process can be increased.
  • FIG. 1 illustrates an example of a structure of a gate pad region of a conventional power MOSFET device.
  • FIG. 2 illustrates a structure of a power MOSFET device with a transient voltage protection diode device according to an embodiment of the present invention.
  • FIG 3 illustrates an internal equivalent circuit of a power MOSFET device having a back to back type zener diode device according to an embodiment of the present invention.
  • FIGS. 4 and 5 are graphs illustrating changes in zener voltage and resistance according to concentration and width of a P - type semiconductor impurity according to an embodiment of the present invention.
  • FIG. 6 is a graph illustrating zener voltages formed at respective stages of a back to back type zener diode according to an embodiment of the present invention.
  • FIG. 7 illustrates an image of an oscilloscope showing voltage characteristics of a back to back type zener diode according to an embodiment of the present invention.
  • FIG. 8 illustrates a planar layout of a power semiconductor device power MOSFET device chip incorporating a back to back type zener diode according to an embodiment of the present invention.
  • FIG. 9 illustrates a cross-sectional structure of part A of FIG. 8.
  • 10 to 24 illustrate a manufacturing process of a power semiconductor device incorporating a transient voltage protection diode device according to an embodiment of the present invention.
  • FIG. 1 illustrates an example of a structure of a gate pad region of a conventional power MOSFET device.
  • a passivation layer 3 for insulation protection is formed under a gate pad region of a conventional power MOSFET device and includes an insulated boundary region 50 to maintain insulation from a source pad region.
  • a gate electrode 21 made of polysilicon is formed under the passivation layer 3 for insulation protection, and a gate insulating layer 22 is formed under the insulation protection passivation layer 3.
  • FIG. 2 illustrates a structure of a power MOSFET device in which a transient voltage protection diode element (ED) is incorporated according to an embodiment of the present invention.
  • ED transient voltage protection diode element
  • the transient voltage protection diode device ED is formed under the boundary area 100 of the gate pad.
  • the transient voltage protection diode device ED is formed in a multi-stage zener diode shape in which a high concentration type 1 semiconductor impurity and a low concentration type 2 semiconductor impurity are alternately joined in multiple stages.
  • the first type semiconductor impurity is a P ⁇ type semiconductor impurity and the second type semiconductor impurity is an N + type semiconductor impurity.
  • the transient voltage protection diode device ED configures a zener diode in a back to back type in multiple stages.
  • a back-to-back type zener diode is formed in a series of 3 to 5 steps between the source electrode and the gate electrode under the boundary region 100 of the gate pad, and both ends of the gate pad are formed in series. It is connected to an electrode and a gate.
  • the transient voltage protection diode device is a back-to-back type in which N + type semiconductor impurities act as a common cathode, and are generally formed in an N + / P- / N + / P- / N + / P- / N + structure. .
  • a back to back type multi-stage zener diode includes a region 30 in which a high concentration of N + type semiconductor impurities are injected into a polysilicon region and a low concentration of P ⁇ type semiconductor. It is formed by alternately joining regions 31 implanted with impurities alternately.
  • one end of the back to back type multi-stage zener diode ED is connected to the gate 24.
  • the other end of the back to back type multi-stage zener diode is connected to the zener electrode 35, and the zener electrode 35 is connected to the conductor 34 and connected to the source electrode 15.
  • the source electrode 15 is connected to the source pad.
  • An ohmic contact region 14 doped with high P + type impurities for connecting the P-type body region 12 and the source electrode 15 is formed under the source electrode 15.
  • Source regions 13 connected to the gate insulating film 33 are formed at both side ends of the ohmic contact region 14, respectively.
  • a portion of the upper end of the center side is connected to the source electrode 15.
  • P - type body regions 12 doped with low P ⁇ type semiconductor impurities are formed under the two source regions 13 formed at both ends of the ohmic contact region 14.
  • the P ⁇ body region 12 is formed in a semi-elliptic shape to surround all of the lower portion of the source region 13.
  • one end of the back to back type multi-stage zener diode ED is formed to be connected to one gate of a POWER MOSFET cell formed in an active cell region adjacent to the gate pad region.
  • a zener insulating layer 23 having a thickness of 1.4 to 1.6 times thicker than the gate insulating layer 33 is formed in consideration of the zener voltage.
  • a JFET region layer 32 is formed under the Zener insulating layer 23.
  • the JFET region 32 is to reduce the resistance caused by the depletion layer in the space between the P-type bodies when the planar gate-type MOSFET is in the on-state, and is doped with N - type impurities. Area layer.
  • An N ⁇ drift region 10 is formed under the JFET region layer 32 to maintain a breakdown voltage of the power MOSFET.
  • the N ⁇ drift region 10 is formed by low doping with N type impurities.
  • a drain region 18 heavily doped with N + type impurities is formed under the N ⁇ drift region 10.
  • FIG. 3 illustrates an internal equivalent circuit of a power MOSFET device having a back to back type multi-stage zener diode device according to an embodiment of the present invention.
  • a back to back type multi-stage zener diode (ED) according to an embodiment of the present invention is formed in a structure connected in parallel to the gate and the drain of the power MOSFET device.
  • the back to back type multi-stage zener diode is a high concentration of polysilicon
  • the N + -type semiconductor impurity 30 and the low concentration P ⁇ -type semiconductor impurity 31 are formed in such a manner that they are alternately joined in four stages in series.
  • a back to back type multistage zener diode structure in which a high concentration of N + type semiconductor impurities 30 and a low level P-type semiconductor impurity 31 are alternately bonded to the polysilicon in series of 3 to 5 steps is formed. Can be adopted.
  • a depletion layer structure is adopted so that Zener breakdown occurs before Avalanche occurs due to a breakdown phenomenon caused by the generation of an Electron-Hole pair.
  • the dose amount and width of each stage of the region 30 into which the polysilicon layer is implanted with high concentration of N + -type semiconductor impurities and the region 31 into which low concentration of P ⁇ -type semiconductor impurities are injected are set accordingly.
  • a zener voltage proportional to the number of stages may be secured.
  • the zener voltage increases as the width thereof increases, but the resistance in the on state increases, so that the efficiency may decrease.
  • the zener voltage increases and the on-state resistance drops.
  • the width of the impurity layer is larger than the appropriate width, the on-state resistance increases and the efficiency is lowered. If the width of the impurity layer is smaller, the Zener BV (Break Voltage) falls and is inefficient. In addition, the BV is lowered if the dose of impurities is less than the appropriate amount.
  • FIGS. 4 and 5 are graphs illustrating changes in zener voltage and zener resistance according to concentrations and widths of P - type semiconductor impurities according to an exemplary embodiment of the present invention.
  • FIG. 4 is a graph showing the relationship between the zener current and the zener voltage according to the concentration and width of the P - type semiconductor impurity through various simulations
  • FIG. 5 illustrates the change of the zener voltage and zener resistance according to the concentration and width. It is shown graphically.
  • the ON state resistance is small when P ⁇ dose 3.0e14 cm ⁇ 2 is formed at P ⁇ width 3.5 ⁇ m.
  • the formation width of the region into which the N + -type semiconductor impurities are implanted is slightly smaller than the formation width of the region into which the P - type semiconductor impurities are implanted At large widths, it was tested that a stable Zener breakdown occurred before Avalanche.
  • the concentration of P - type semiconductor impurities is injected into the polysilicon layer at different concentrations (2.8e14, 2.9e14, 3.0e14) for the back to back type multistage zener diode having four zener diodes.
  • FIG. 6 is a graph illustrating zener voltages formed at each stage of a back to back type multi-stage zener diode according to an exemplary embodiment of the present invention.
  • a zener voltage proportional to the number of stages may be secured.
  • the back to back type multi-stage zener diode has a high semiconductor impurity region and a P ⁇ region having a width of 4 ⁇ m of the N + region and 1.0e16 cm ⁇ 2 of the impurity concentration of the N + .
  • FIG. 7 illustrates an image of an oscilloscope showing voltage characteristics of a back to back type multi-stage zener diode according to an embodiment of the present invention.
  • a forward zener voltage is 39V
  • a reverse zener voltage is 35V.
  • FIG. 8 illustrates a planar layout of a power semiconductor device power MOSFET device chip incorporating a back to back type multi-stage zener diode according to an embodiment of the present invention.
  • FIG. 9 illustrates a cross-sectional structure of part A of FIG. 8.
  • a back to back type multi-stage zener diode for transient voltage protection is formed under the boundary region 100 of the gate pad region 200.
  • the boundary region 100 of the gate pad region 200 is formed to include a pad insulating layer 210 formed between the gate pad and the source pad, and a back according to an embodiment of the present invention is disposed below the insulating layer 210.
  • a to back type multistage zener diode is formed.
  • a power semiconductor device incorporating a transient voltage protection diode device has an effect of embedding a back to back type zener diode without changing the overall chip size.
  • FIG. 8B illustrates an equivalent circuit of a back to back type multi-stage zener diode for part A of FIG. 8A according to an embodiment of the present invention.
  • one back to back type multi-stage Zener diodes according to the embodiment of the present invention as a whole N + / P - / N + / P - / N + / P - / N + / P - / N + structure and its equivalent circuit is a structure in which four pairs of back to back type zener diodes are connected in series.
  • the zener diode, N + region of the width (a) 4 ⁇ m, the height (c) made of a high concentration of 0.3 ⁇ m semiconductor impurity region and P - region of Low concentration semiconductor impurity regions of width (b) 3.5 ⁇ m height (c) 0.3 ⁇ m are alternately formed in series in four stages.
  • 10 to 24 illustrate a manufacturing process of a power semiconductor device incorporating a transient voltage protection diode device according to an embodiment of the present invention.
  • the step of forming the JFET layer 122 on the surface of the N - drift layer 121 is performed.
  • FIG. 10 shows a process for implanting N ⁇ ions to form a JFET layer.
  • the JFET layer 122 is formed by doping a low concentration of N ions to the entire surface of the prepared N - drift layer 121.
  • the step of forming the first insulating film 123 on the JFET layer 122 is performed.
  • FIG 11 illustrates a process in which the first insulating layer 123 is formed according to an embodiment of the present invention.
  • the first insulating layer 123 may be an oxide film by using a diffusion process, or may be formed by depositing an oxide film by a CVD method.
  • the first insulating layer 123 may be manufactured using SiON, HfO, or the like depending on process characteristics.
  • a portion of the first insulating layer may be removed from a portion corresponding to the POWER MOSFET active cell region of the first insulating layer.
  • FIG. 12 illustrates a process in which a part of the first insulating film in a portion corresponding to a portion of the power MOSFET active cell region is removed.
  • a method of removing the first insulating film of the portion corresponding to the POWER MOSFET active cell region portion may be performed by photomasking and peeling off with dry etching, and after placing SiN or the like on the photomasking method. It may be performed by any one of a method of etching the SiN of the portion corresponding to the area of the active power MOSFET active cell, and then peeled off by the wet etching process.
  • FIG. 13 illustrates a process in which a second insulating film 124 is formed in a portion corresponding to a portion of a power MOSFET active cell region.
  • the second insulating layer 124 is a gate insulating layer 124 formed at a thickness different from that of the first insulating layer 123 under the gate.
  • the first insulating layer 123 is formed in a range of 1.4 to 1.6 times the thickness of the second insulating layer 124, which is a gate insulating layer, and has different thicknesses for the active region and the back to back type multi-stage zener diode region.
  • the first insulating layer 123 is to insulate the lower portion of the region where the back to back type zener diode is formed according to an embodiment of the present invention, and to prevent the incoming transient voltage from affecting the power MOSFET active cell region.
  • the thickness of the second insulating layer 124 is greater than that of the gate insulating layer 124.
  • the second insulating layer 124 which is a gate insulating layer, is formed by growing an entire oxide layer by a diffusion method.
  • the oxide film grows well in only the POWER MOSFET active cell region where the Si surface is exposed, and the back to back type multi-stage zener diode region in which the Si surface is not exposed is grown on the entire wafer WF using the feature that the oxide layer does not grow.
  • the first insulating film 123 and the second insulating film 124 having different thicknesses for each region may be formed.
  • the polysilicon layer 126 is formed.
  • FIG. 14 illustrates a process in which the polysilicon layer 126 is formed on the first and second insulating layers.
  • the polysilicon layer 126 forms a gate in the POWER MOSFET active cell region and a back to back zener diode in the back to back zener diode region.
  • a photoetch process is performed to etch the remaining central region 127 of the polysilicon layer and the second insulating layer except for the gate region of the POWER MOSFET active cell region using a mask.
  • FIG. 15 illustrates a process of etching the remaining central region 127 of the polysilicon layer and the second insulating layer except for the gate region of the POWER MOSFET active cell region.
  • a power MOSFET P ⁇ is formed by using a mask for a first photo resist (PR) on the etched polysilicon layer. After masking to form a space for forming the body and Zener diode anode regions, a process of implanting P ⁇ impurities at a low concentration is performed.
  • PR photo resist
  • the anode regions 131 to 134 of the back to back type multi-stage Zener diode are injected into the polysilicon layer 126 by injecting P ⁇ type semiconductor impurities into a range of 3.5 ⁇ m in width and 0.3 ⁇ m in height. Is formed.
  • three to five anode regions of the back to back type multi-stage Zener diode may be formed in a range of 3 to 4 ⁇ m in width and 0.2 to 0.4 ⁇ m in height.
  • the second PR mask is removed, and only a central portion of the P ⁇ body region is formed on the etched polysilicon layer.
  • a process of implanting P + impurities is performed to form an ohmic contact region 129 connected to the P ⁇ body region 138 by contact.
  • FIG. 17 illustrates a process of injecting P + impurities using a second PR mask 182 having a space formed only in a central portion of the P ⁇ body region.
  • FIG. 18 illustrates a process of forming an anode region and a P + ohmic contact region of a P-body, a back to back type multi-stage Zener diode.
  • the mask for the second photo resist is removed, and the N + source region space and the Zener diode cathode region are formed thereon.
  • a third PR (Photo Resist) mask having a space
  • a process of implanting N + type semiconductor impurities for forming an N + source region and a Zener diode cathode region is performed.
  • FIG. 19 is a mask 183 for a third PR (Photo Resist) mask, and N + source regions 141 and 142 and N for forming cathode regions 151 to 155 of a back to back type multi-stage Zener diode. The process of injecting + type semiconductor impurity is shown.
  • PR Photo Resist
  • FIG 19 illustrates a process in which an N + source, back to back type multi-stage Zener diode region is formed according to an embodiment of the present invention.
  • the N + source regions 141 and 142 are formed by diffusing so that each half region of the N + source regions 141 and 142 spans the gate insulating film 124.
  • the width of the cathode region (N + region) of the back to back type multistage Zener diode is the anode region (P ⁇ region) of the back to back type multistage Zener diode. It is carried out to form slightly thicker than the width of.
  • N + regions are formed between the Zener diode anode regions having a width of 4 ⁇ m and a height of 0.3 ⁇ m by injecting N + type semiconductor impurities into the polysilicon layer 126. do.
  • Zener diode cathode regions may be formed in a range of 3.5 to 4.5 ⁇ m in width and 0.2 to 0.4 ⁇ m in height.
  • the third insulating layer 143 is formed on the top.
  • FIG. 21 illustrates a process in which the third insulating layer 143 is formed thereon.
  • a process of depositing a SiO 2 insulator such as PSG, BPSG, or FSG by CVD is performed.
  • a step of forming a source electrode and a zener electrode, and forming a metal electrode body 146 formed such that they are connected to each other is performed.
  • the source electrode space including each half region of the N + source regions 141 and 142, which are parts connected to the metal electrode body, and the terminal space on one side of the zener diode are etched. After performing the process, a process of forming the metal electrode body 146 in the etched space is performed.
  • the etching process proceeds to a dry etching process, the N + Source region, P + Ohmic Contact region, one cathode region of the back to back type multi-stage Zener diode all by the metal electrode body Etching at once to be connected.
  • FIG. 22 illustrates a process of etching the space where the metal electrode body is to be connected in the third insulating layer.
  • the process of forming the metal electrode body in the etched space is filled with a metal conductor 146 such as Al using a Sputtering or Metal Deposition method.
  • the metal electrode body 146 may be integrally formed such that the power MOSFET source and the one side cathode of the back to back type multi-stage Zener diode are all connected at once.
  • FIG. 23 illustrates a process in which a metal conductor 146 is connected to a power MOSFET source and a cathode of one end of a back to back type multistage Zener diode.
  • FIG. 24 illustrates a process of injecting N + type semiconductor impurities into the bottom surface to form N + Drain.
  • the step of forming the N + Drain to attach a protective film or the like so that the upper side is not contaminated or invaded After that, a process of inverting and injecting N + impurities entirely onto the bottom surface of the wafer is performed.
  • a separate additional process step for embedding the transient voltage protection diode device is not required, and a power MOSFET active cell manufacturing process is performed.
  • the efficiency of the process can be increased by performing the process of forming a diode element for transient voltage protection in parallel.

Abstract

Provided is a power semiconductor device having an over-voltage protection diode element embedded therein, including an insulating film between a source pad and a gate pad, having a polysilicon layer formed under a boundary region of the gate pad, including the insulating film, and having a multi-stage Zener diode in which a first-type semiconductor region doped with first-type semiconductor impurities in a high concentration and a second-type semiconductor region doped with second-type semiconductor impurities in a low concentration are alternately formed in multiple stages in series on the polysilicon layer, wherein one end of the multi-stage Zener diode is connected to one gate of a power MOSFET cell formed in an active cell region adjacent to a gate pad region and the other end of a back-to-back type multi-stage Zener diode region is connected to a source electrode of the power MOSFET cell.

Description

과도전압 보호용 다이오드 소자를 내장하는 전력 반도체 장치 및 그 제조방법 Power semiconductor device containing a diode element for transient voltage protection and its manufacturing method
본 발명은 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치 및 그 제조방법에 관한 것이다.The present invention relates to a power semiconductor device incorporating a transient voltage protection diode element and a method of manufacturing the same.
일반적으로 반도체 기판 상에 형성된 반도체 집적 회로에 사용되는 전력 반도체 장치는 정전기(ESD)에 기인해 발생하는 펄스 고전압 및 순간적으로 외부에서 유입되는 써지 전압으로 인하여 내부 요소가 파괴되는 손상을 받을 수가 있다.In general, power semiconductor devices used in semiconductor integrated circuits formed on semiconductor substrates may be damaged by internal elements being destroyed by pulsed high voltages generated by electrostatic discharge (ESD) and surge voltages flowing from the outside.
이에 따라 전력 반도체 장치는 과도 전압 유입에 따른 브레이크다운으로부터 보호되어야 한다. Accordingly, the power semiconductor device must be protected from breakdown caused by excessive voltage inflow.
반도체 장치의 꾸준한 집적 연구 및 동작 전압의 소비 전력의 감소 노력과 더불어, 반도체 장치를 이루는 반도체 소자의 구조는 더 정교하게 되고, 고밀도화 되면서, 그 크기가 지속적으로 축소되어 왔다. 일반적으로, 정교한 고밀도 반도체의 정전기적 브레이크다운은 쉽게 발생한다.With the steady integration research of semiconductor devices and efforts to reduce the power consumption of operating voltages, the structure of semiconductor devices constituting the semiconductor devices has become more sophisticated and denser, and the size thereof has been continuously reduced. In general, electrostatic breakdown of sophisticated high density semiconductors occurs easily.
종래에는 과도전압 유입으로부터 반도체 장치를 보호하기 위한 일환으로, 별도의 diode Limiter를 사용하여 ESD전류를 bypass하는 방법이 채택되었다. Conventionally, as a part of protecting a semiconductor device from an excessive voltage inflow, a method of bypassing an ESD current using a separate diode limiter has been adopted.
종래의 전력 모스펫 장치의 경우 이러한 과도전압 보호를 위해 package 과정에서 보호용 Diode나 과도 전압 보호소자를 와이어링으로 접합하는 공정을 통하여 과도 전압 보호 장치를 포함하도록 하거나, Control IC에 ESD보호회로를 내장하는 방법이 채택되기도 하였다.In the case of the conventional power MOSFET device, the transient voltage protection device is included through a process of wiring the protective diode or the transient voltage protection device by wiring in the package process for such transient voltage protection, or the ESD protection circuit is embedded in the control IC. The method was also adopted.
본 발명의 배경기술은 대한민국 공개특허공보 제10-2011-0109847호(2011.10.06)에 개시되어 있다.Background art of the present invention is disclosed in Republic of Korea Patent Publication No. 10-2011-0109847 (2011.10.06).
본 발명은 메인 셀 제조공정 중에 과도전압으로부터 칩을 보호할 수 있는 과도 전압 보호용 소자를 효율적으로 내장하여 제조하도록 하는 전력 반도체 장치의 제조 방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention provides a method for manufacturing a power semiconductor device for efficiently embedding and manufacturing a transient voltage protection device capable of protecting a chip from a transient voltage during a main cell manufacturing process.
본 발명의 또 다른 목적은 게이트 패드 영역 내에 과도 전압 보호용 소자를 내장하도록 함으로서 내부 공간이 효율적으로 형성되는 전력반도체 장치 및 그 제조방법을 제공하는 것이다.It is still another object of the present invention to provide a power semiconductor device and a method for manufacturing the same, in which an internal space is efficiently formed by embedding a transient voltage protection device in a gate pad region.
본 발명의 일 측면에 따르면, 소스 패드와 게이트 패드 사이에 절연막을 포함하는 전력 반도체 장치에 있어서, 상기 절연막을 포함하는 게이트 패드의 경계 영역 하부에 형성된 폴리실리콘층이 형성되고, 상기 폴리실리콘층에 제1 형 반도체 불순물이 고농도로 도핑되는 제1 형 반도체 영역과 제2 형 반도체 불순물이 저농도로 도핑되는 제2 형 반도체 영역이 교대로 다단 직렬로 형성된 다단 제너 다이오드가 형성되며, 상기 다단 제너다이오드의 일측단은 상기 게이트 패드 영역에 인접된 액티브 셀 영역에 형성된 전력 모스펫 셀의 일측 게이트에 접속되고 상기 다단 제너다이오드 영역의 타측단은 상기 전력 모스펫 셀의 소스 전극에 연결되도록 접속되는 것을 특징으로 하는 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치가 제공된다.According to an aspect of the present invention, in a power semiconductor device including an insulating film between a source pad and a gate pad, a polysilicon layer formed under the boundary region of the gate pad including the insulating film is formed, the polysilicon layer A multistage zener diode is formed in which a first type semiconductor region in which a first type semiconductor impurity is heavily doped and a second type semiconductor region in which a second type semiconductor impurity is lowly doped is formed in alternating multistage series. One end is connected to one gate of a power MOSFET cell formed in an active cell region adjacent to the gate pad region and the other end of the multi-stage zener diode region is connected to be connected to a source electrode of the power MOSFET cell A power semiconductor device incorporating a voltage protection diode element is provided.
또한, 상기 다단 제너 다이오드의 하부에는 제2 절연막이 형성되며, 상기 제2 절연막은 상기 전력 모스펫 셀의 게이트 절연막의 두께의 1.4 ~ 1.6 배의 두께를 가지는 것을 특징으로 한다.In addition, a second insulating film is formed below the multi-stage zener diode, and the second insulating film has a thickness of 1.4 to 1.6 times the thickness of the gate insulating film of the power MOSFET cell.
또한, 상기 제1 형 반도체 불순물은 P-형 반도체 불순물이며, 제2 형 반도체불순물은 N+형 반도체 불순물이며, 상기 다단 제너 다이오드는 N+형 반도체 불순물이 캐소드로 작용하는 제너다이오드가 back to back 타입으로 3 ~ 5단 직렬로 접속된 구조인 것을 특징으로 한다.In addition, the first type semiconductor impurity is a P − type semiconductor impurity, the second type semiconductor impurity is an N + type semiconductor impurity, and the multistage zener diode has a zener diode in which N + type semiconductor impurity acts as a cathode. It is characterized in that the structure is connected in series of 3 to 5 stages in series.
또한, 상기 제1 형 반도체 영역의 폭은 3 ~ 4㎛이고, 상기 제2 형 반도체 영역의 폭은 3.5 ~ 4.5㎛인 것을 특징으로 한다.In addition, the width of the first type semiconductor region is 3 ~ 4㎛, the width of the second type semiconductor region is characterized in that the 3.5 ~ 4.5㎛.
또한, 상기 제1 형 반도체 영역은 P-형 반도체 불순물이 2.9 ~ 3.1e14 cm-2 농도로 주입되며, 제2 반도체 영역은 N+형 반도체 불순물이 0.9 ~ 1.1e16 cm-2 농도로 주입된 것을 특징으로 한다.In addition, the first type semiconductor region is implanted with a P - type semiconductor impurity at a concentration of 2.9 to 3.1e14 cm -2 , and the second semiconductor region is implanted with an N + type semiconductor impurity at a concentration of 0.9-1.1e16 cm -2 . It features.
또한, 상기 제1 형 반도체 불순물은 P-형 반도체 불순물이며, 제2 형 반도체불순물은 N+형 반도체 불순물이며, 상기 다단 제너 다이오드는 N+형 반도체 불순물이 캐소드로 작용하는 제너다이오드가 back to back 타입으로 4단 직렬로 접속된 구조이고, 상기 제1 형 반도체 영역의 폭은 3.5㎛이고, 상기 제2 형 반도체 영역의 폭은 4㎛이며, 상기 제1 형 반도체 영역은 P-형 반도체 불순물이 2.9 ~ 3.1e14 cm-2 농도로 주입된 것이고, 제2 반도체 영역은 N+형 반도체 불순물이 1.0e16 cm-2 농도로 주입된 것을 특징으로 한다.In addition, the first type semiconductor impurity is a P − type semiconductor impurity, the second type semiconductor impurity is an N + type semiconductor impurity, and the multistage zener diode has a zener diode in which N + type semiconductor impurity acts as a cathode. Type 4 structure connected in series, the width of the first type semiconductor region is 3.5 占 퐉, the width of the second type semiconductor region is 4 占 퐉, and the first type semiconductor region is formed of P - type semiconductor impurities. It is implanted at a concentration of 2.9 ~ 3.1e14 cm -2 , the second semiconductor region is characterized in that the implanted N + -type semiconductor impurities at a concentration of 1.0e16 cm -2 .
또한, 상기 다단 제너 다이오드는 0.3㎛ 높이로 형성된 것을 특징으로 한다.In addition, the multi-stage zener diode is characterized in that formed in 0.3㎛ height.
또한, 상기 제1 형 반도체 불순물은 P-형 반도체 불순물이며, 제2 형 반도체불순물은 N+형 반도체 불순물이며, 상기 다단 제너 다이오드는 back to back 타입으로서 N+형 반도체 불순물이 캐소드로 작용하는 N+/P-/N+/P-/N+/P-/N+/P-/N+ 구조를 가지는 것을 특징으로 한다.The first type semiconductor impurity is a P − type semiconductor impurity, the second type semiconductor impurity is an N + type semiconductor impurity, and the multistage zener diode is a back to back type, wherein the N + type semiconductor impurity acts as a cathode. + / P - / N + / P - / N + / P - is characterized in that it has a / N + structure - / N + / P.
본 발명의 또 다른 측면에 따르면, 전력 반도체 장치를 제조하는 방법에 있어서, (a) 다단 제너 다이오드가 형성되는 영역에 제1 절연막을 형성하는 단계; (b)전력 모스펫 셀이 형성되는 영역에 제2 절연막을 형성하는 단계; (c) 상기 제1, 2 절연막 위에 폴리실리콘층을 형성하는 단계; (d) 상기 전력 모스펫 셀이 형성되는 영역 중에서 게이트 영역을 제외한 상기 폴리실리콘층과 제2 절연막층의 중앙 영역을 식각하는 단계; (e) 제1 마스크를 이용하여 P- 형 반도체 불순물을 주입하여 상기 전력 모스펫의 P- Body 및 상기 폴리실리콘층에 상기 다단 제너다이오드의 애노드 영역을 형성하는 단계; (f) 제2 마스크를 이용하여 상기 P- Body 내에 P+ 형 반도체 불순물을 주입하여 P+ Ohmic Contact 영역을 형성하는 단계; (g) 제3 마스크를 이용하여 N+ 형 반도체 불순물을 주입하여 상기 전력 모스펫의 N+ Source 영역 및 상기 폴리실리콘층에 상기 다단 제너다이오드의 캐소드 영역을 형성하는 단계; (h) 상기 (g) 단계 이후에 상부 전체에 제3 절연층을 형성하는 단계; (i) 소스 전극 공간 및 상기 다단 제너다이오드의 일측 단자 공간을 에칭하는 단계; 및 (j) 상기 에칭된 공간을 금속물로 메꾸어서 소스 전극과 상기 다단 제너다이오드의 일측 단자 전극을 연결하는 금속 전극체를 형성하는 단계; 를 포함하는 것을 특징으로 하는 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치 제조 방법이 제공된다.According to still another aspect of the present invention, there is provided a method of manufacturing a power semiconductor device, comprising: (a) forming a first insulating film in a region where a multi-stage zener diode is formed; (b) forming a second insulating film in a region where the power MOSFET cell is formed; (c) forming a polysilicon layer on the first and second insulating films; (d) etching a central region of the polysilicon layer and the second insulating layer except for a gate region among regions where the power MOSFET cell is formed; (e) implanting a P − type semiconductor impurity using a first mask to form an anode region of the multi-stage zener diode in the P-body and the polysilicon layer of the power MOSFET; (f) implanting an impurity in the P + type semiconductor P- Body by using a second mask to form the P + Ohmic Contact area; (g) implanting N + -type semiconductor impurities using a third mask to form cathode regions of the multi-stage zener diodes in the N + Source region and the polysilicon layer of the power MOSFET; (h) forming a third insulating layer over the entire upper part after step (g); (i) etching the source electrode space and one side terminal space of the multi-stage zener diode; And (j) filling the etched space with a metal material to form a metal electrode body connecting the source electrode and one terminal electrode of the multi-stage zener diode; Provided is a method for manufacturing a power semiconductor device incorporating a transient voltage protection diode element.
또한, 소스 패드와 게이트 패드 사이에 패드 절연막을 포함하는 상기 전력 반도체 장치에서, 상기 다단 제너 다이오드는, 상기 패드 절연막을 포함하는 상기 게이트 패드의 경계 영역 하부에 형성되는 것을 특징으로 한다.In the power semiconductor device including a pad insulating film between a source pad and a gate pad, the multi-stage zener diode is formed under the boundary region of the gate pad including the pad insulating film.
또한, 상기 (e) 단계에서 상기 애노드 영역은 폭 3 ~ 4㎛ 범위로 3 ~ 5개가 형성되는 것을 특징으로 한다.In addition, in the step (e), the anode region is characterized in that 3 to 5 are formed in the range of 3 ~ 4㎛ width.
또한, 상기 (g) 단계에서 상기 캐소드 영역은 폭 3.5 ~ 4.5 ㎛ 범위로 4 ~ 6개가 형성되는 것을 특징으로 한다.In addition, in the step (g), four to six cathode regions are formed in a width range of 3.5 to 4.5 μm.
또한, 상기 제1 절연막은 상기 제2절연막의 1.4 ~ 1.6 배의 두께로 형성되는 것을 특징으로 한다.In addition, the first insulating film is characterized in that the thickness of 1.4 ~ 1.6 times the second insulating film.
또한, 상기 (e)단계에서 상기 애노드 영역은 폭 3.5㎛ 범위로 4개가 형성되며 P-형 불순물의 농도가 3.0e14 cm-2로 주입되며, 상기 (g) 단계에서 상기 캐소드 영역은 폭 4 ㎛ 범위로 5개가 형성되며, N+불순물의 농도가 1.0e16 cm-2로 주입되는 것을 특징으로 한다.In addition, in the step (e), four anode regions are formed in a range of 3.5 μm in width, and a concentration of P − -type impurities is injected at 3.0e14 cm −2 . In the step (g), five cathode regions are formed in a range of 4 μm in width, and the concentration of N + impurity is 1.0e16 cm −2 .
본 발명의 일 실시 예에 따르면, 전력 반도체 장치 칩 사이즈 내에서 과도 전압 보호용 소자를 포함하도록 하는 전력반도체 장치 및 그 제조방법을 제공할 수 있다.According to an embodiment of the present invention, a power semiconductor device and a method of manufacturing the same may be provided to include a device for transient voltage protection within a power semiconductor device chip size.
본 발명의 일 실시 예에 따르면, 전력 반도체 장치의 셀 내부에 과도 전압 보호용 소자를 포함하도록 함으로써, 별도의 ESD보호용 소자에 대한 추가 공정을 줄일 수 있으므로, 이에 따른 와이어링 공정 및 기생 파라미터를 줄일 수 있는 효과가 있다. According to an embodiment of the present invention, by including the transient voltage protection device inside the cell of the power semiconductor device, it is possible to reduce the additional process for the separate ESD protection device, thereby reducing the wiring process and parasitic parameters accordingly. It has an effect.
또한, 본 발명의 일 실시 예에 따르면, 과도전압으로부터 전력 반도체 장치를 보호할 수 있는 과도 전압 보호용 소자를 내부에 내장시킴으로 인하여 공간 효율성을 높이고 전체 팩케이징 사이즈를 줄일 수 있는 효과를 가진다.In addition, according to an embodiment of the present invention, by embedding a transient voltage protection device that can protect the power semiconductor device from the transient voltage therein has the effect of increasing the space efficiency and reduce the overall packaging size.
또한, 본 발명의 일 실시 예에 따른 과도전압 보호용 다이오드 소자를 내장하는 전력 반도체 장치 제조 방법에 의하면, POWER MOSFET Active cell 제조 공정과 과도전압 보호용 다이오드 소자를 형성하는 공정을 동일한 공정으로 수행하는 방벙을 제공함으로써, 공정의 효율성을 높일 수 있다.In addition, according to the power semiconductor device manufacturing method including the transient voltage protection diode element according to an embodiment of the present invention, the method of performing the power MOSFET active cell manufacturing process and the process of forming the transient voltage protection diode element in the same process. By providing this, the efficiency of the process can be increased.
도 1은 종래 전력 모스펫 장치의 게이트 패드 영역의 구조의 일 예를 도시한 것이다.1 illustrates an example of a structure of a gate pad region of a conventional power MOSFET device.
도 2는 본 발명의 일 실시 예에 따른 과도전압 보호용 다이오드 소자가 내장된 전력 모스펫 장치의 구조를 도시한 것이다.2 illustrates a structure of a power MOSFET device with a transient voltage protection diode device according to an embodiment of the present invention.
도 3은 본 발명의 일 실시 예에 따른 back to back 타입 제너다이오드 소자를 내장하는 전력 모스펫 장치의 내부 등가 회로를 도시한 것이다.3 illustrates an internal equivalent circuit of a power MOSFET device having a back to back type zener diode device according to an embodiment of the present invention.
도 4, 5는 본 발명의 일 실시 예에 따른 P-형 반도체불순물의 농도 및 폭에 따른 제너전압 및 저항의 변화를 그래프로 도시한 것이다.4 and 5 are graphs illustrating changes in zener voltage and resistance according to concentration and width of a P - type semiconductor impurity according to an embodiment of the present invention.
도 6은 본 발명의 일 실시 예에 따른 back to back 타입 제너다이오드의 각 단별 형성되는 제너 전압을 그래프로 도시한 것이다.FIG. 6 is a graph illustrating zener voltages formed at respective stages of a back to back type zener diode according to an embodiment of the present invention.
도 7은 본 발명의 일 실시 예에 따른 back to back 타입 제너다이오드의 전압 특성을 나타낸 오실로스코프의 이미지를 도시한 것이다.7 illustrates an image of an oscilloscope showing voltage characteristics of a back to back type zener diode according to an embodiment of the present invention.
도 8은 본 발명의 일 실시 예에 따른 back to back 타입 제너다이오드를 내장하는 전력 반도체 장치 전력 모스펫 장치 칩의 평면 레이아웃을 도시한 것이다.8 illustrates a planar layout of a power semiconductor device power MOSFET device chip incorporating a back to back type zener diode according to an embodiment of the present invention.
도 9은 도 8에서 A부분에 대한 단면 구조를 도시한 것이다.FIG. 9 illustrates a cross-sectional structure of part A of FIG. 8.
도 10 내지 도 24는 본 발명의 일 실시 예에 따른 과도전압 보호용 다이오드 소자가 내장된 전력 반도체 장치의 제조 공정을 도시한 것이다.10 to 24 illustrate a manufacturing process of a power semiconductor device incorporating a transient voltage protection diode device according to an embodiment of the present invention.
본 발명은 다양한 변경을 가할 수 있고 여러 가지 실시 예를 가질 수 있는바, 특정 실시 예들을 도면에 예시하고 이를 상세한 설명을 통해 상세히 설명하고자 한다.As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description.
그러나 이는 본 발명을 특정한 실시 형태에 대해 한정하려는 것이 아니며, 본 발명의 사상 및 기술 범위에 포함되는 모든 변경, 균등물 내지 대체물을 포함하는 것으로 이해되어야 한다.However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention.
본 발명을 설명함에 있어서, 관련된 공지 기술에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그 상세한 설명을 생략한다.In describing the present invention, when it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.
그리고 도면에서 본 발명을 명확하게 설명하기 위해서 설명과 관계없는 부분은 생략하였으며, 명세서 전체를 통하여 유사한 부분에 대해서는 유사한 도면 부호를 붙였다.In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.
도 1은 종래 전력 모스펫 장치의 게이트 패드 영역의 구조의 일 예를 도시한 것이다.1 illustrates an example of a structure of a gate pad region of a conventional power MOSFET device.
도 1을 참조하면, 종래의 전력 모스펫 장치의 게이트 패드 영역 하부에는 절연보호용 passivation 층(3)이 형성되며 소스 패드 영역과 절연을 유지하기 위하여 절연된 경계 영역(50)을 포함한다. Referring to FIG. 1, a passivation layer 3 for insulation protection is formed under a gate pad region of a conventional power MOSFET device and includes an insulated boundary region 50 to maintain insulation from a source pad region.
또한, 절연보호용 passivation층(3) 하부에는 폴리실리콘 재질의 게이트 전극(21)이 형성되고 그 하부에는 게이트 절연막(22)이 형성된다. In addition, a gate electrode 21 made of polysilicon is formed under the passivation layer 3 for insulation protection, and a gate insulating layer 22 is formed under the insulation protection passivation layer 3.
도 2는 본 발명의 일 실시 예에 따른 과도전압 보호용 다이오드 소자(ED)가 내장된 전력 모스펫 장치의 구조를 도시한 것이다.2 illustrates a structure of a power MOSFET device in which a transient voltage protection diode element (ED) is incorporated according to an embodiment of the present invention.
도 2를 참조하면, 본 발명의 일 실시 예에 따른 과도전압 보호용 다이오드 소자(ED)는 게이트 패드의 경계 영역(100) 하부에 형성된다.Referring to FIG. 2, the transient voltage protection diode device ED is formed under the boundary area 100 of the gate pad.
본 발명의 일 실시 예에 따른 과도전압 보호용 다이오드 소자(ED)는 고농도의 제1형 반도체불순물과 저농도의 제2형 반도체불순물이 교대로 다단으로 접합되는 다단 제너다이오드 형상으로 형성된다.The transient voltage protection diode device ED according to the embodiment of the present invention is formed in a multi-stage zener diode shape in which a high concentration type 1 semiconductor impurity and a low concentration type 2 semiconductor impurity are alternately joined in multiple stages.
본 발명의 일 실시 예에 따르면, 제1 형 반도체 불순물은 P-형 반도체 불순물이며, 제2 형 반도체불순물은 N+형 반도체 불순물이다.According to an embodiment of the present invention, the first type semiconductor impurity is a P − type semiconductor impurity and the second type semiconductor impurity is an N + type semiconductor impurity.
도 2를 참조하면, 본 발명의 일 실시 예에 따른 과도전압 보호용 다이오드 소자(ED)는 제너다이오드를 back to back 타입으로 다단으로 구성한다.Referring to FIG. 2, the transient voltage protection diode device ED according to the exemplary embodiment of the present invention configures a zener diode in a back to back type in multiple stages.
본 발명의 일 실시 예에 따르면, 게이트 패드의 경계 영역(100) 하부에 백투백(back to back) 타입 제너다이오드를 소스전극과 게이트전극 사이에 3 ~ 5단 직렬로 형성하고 그 양측단은 각각 소스전극과 게이트에 접속된다.According to an embodiment of the present invention, a back-to-back type zener diode is formed in a series of 3 to 5 steps between the source electrode and the gate electrode under the boundary region 100 of the gate pad, and both ends of the gate pad are formed in series. It is connected to an electrode and a gate.
본 발명의 일 실시 예에 따른 과도전압 보호용 다이오드 소자는 N+형 반도체 불순물이 공통 캐소드로 작용하는 백투백 타입으로서, 전체적으로 N+/P-/N+/P-/N+/P-/N+ 구조로 형성된다.The transient voltage protection diode device according to an embodiment of the present invention is a back-to-back type in which N + type semiconductor impurities act as a common cathode, and are generally formed in an N + / P- / N + / P- / N + / P- / N + structure. .
도 2를 참조하면, 본 발명의 일 실시 예에 따른 back to back 타입 다단 제너다이오드(ED)는 폴리 실리콘 영역에 고농도의 N+형 반도체 불순물을 주입된 영역(30)과 저농도의 P-형 반도체 불순물을 주입된 영역(31)을 교대로 다단 접합하여 형성된다.Referring to FIG. 2, a back to back type multi-stage zener diode (ED) according to an embodiment of the present invention includes a region 30 in which a high concentration of N + type semiconductor impurities are injected into a polysilicon region and a low concentration of P − type semiconductor. It is formed by alternately joining regions 31 implanted with impurities alternately.
또한, back to back 타입 다단 제너다이오드(ED)의 일측단은 게이트(24)에 접속된다.In addition, one end of the back to back type multi-stage zener diode ED is connected to the gate 24.
또한, back to back 타입 다단 제너다이오드의 타측단은 제너 전극(35)에 접속되며, 상기 제너 전극(35)은 도전체(34)로 이어져서 소스 전극(15)에 연결된다.In addition, the other end of the back to back type multi-stage zener diode is connected to the zener electrode 35, and the zener electrode 35 is connected to the conductor 34 and connected to the source electrode 15.
소스 전극(15)은 소스패드와 연결된다. The source electrode 15 is connected to the source pad.
소스 전극(15) 하부에는 P형 Body 영역(12)과 상기 Source 전극(15)을 연결시켜 주기 위한 P+형 불순물이 높게 도핑 된 Ohmic Contact 영역(14)이 형성된다.An ohmic contact region 14 doped with high P + type impurities for connecting the P-type body region 12 and the source electrode 15 is formed under the source electrode 15.
Ohmic Contact 영역(14)의 양 측단에는 각각 게이트 절연막(33)에 접속되는 소스영역(13)이 형성된다. Source regions 13 connected to the gate insulating film 33 are formed at both side ends of the ohmic contact region 14, respectively.
또한, Ohmic Contact 영역(14)은 중앙측 상단 일부는 소스 전극(15)에 접속된다.In the ohmic contact region 14, a portion of the upper end of the center side is connected to the source electrode 15.
상기 Ohmic Contact 영역(14)의 양 측단에 형성된 두 소스 영역(13) 하부에는 P- 형 반도체 불순물이 낮게 도핑된 P- 형 Body 영역(12)이 형성된다.P - type body regions 12 doped with low P − type semiconductor impurities are formed under the two source regions 13 formed at both ends of the ohmic contact region 14.
상기 P- 형 Body 영역(12)은 상기 소스 영역(13) 하부를 모두 감싸도록 반타원형 형상으로 형성된다.The P − body region 12 is formed in a semi-elliptic shape to surround all of the lower portion of the source region 13.
본 발명의 일 실시 예에 따르면, back to back 타입 다단 제너다이오드(ED)의 일측단은 게이트 패드 영역에 인접된 액티브 셀 영역에 형성된 POWER MOSFET 셀의 일측 게이트에 접속되도록 형성된다.According to an embodiment of the present invention, one end of the back to back type multi-stage zener diode ED is formed to be connected to one gate of a POWER MOSFET cell formed in an active cell region adjacent to the gate pad region.
back to back 타입 제너다이오드(ED)의 하부는 제너 전압을 고려하여 게이트 절연막(33)보다 1.4 ~ 1.6배 더 두꺼운 두께를 가진 제너 절연막(23)이 형성된다.In the lower portion of the back to back type zener diode ED, a zener insulating layer 23 having a thickness of 1.4 to 1.6 times thicker than the gate insulating layer 33 is formed in consideration of the zener voltage.
본 발명의 일 실시 예에 따르면, 상기 제너 절연막(23) 하부에는 JFET 영역층(32)이 형성된다.According to an embodiment of the present invention, a JFET region layer 32 is formed under the Zener insulating layer 23.
본 발명의 일 실시 예에 따른 JFET 영역(32)은 Planar 타입 게이트 타입의 MOSFET가 온-상태일때, P형 Body사이의 공간의 공핍층에 의한 저항을 줄이기 위한 것으로써 N-형 불순물이 도핑 된 영역층이다.The JFET region 32 according to an embodiment of the present invention is to reduce the resistance caused by the depletion layer in the space between the P-type bodies when the planar gate-type MOSFET is in the on-state, and is doped with N - type impurities. Area layer.
상기 JFET 영역층(32) 하부에는 Power MOSFET의 항복전압(Breakdown Voltage)을 유지하여 주는 역할을 하는 N- 드리프트 영역(10)이 형성된다.An N − drift region 10 is formed under the JFET region layer 32 to maintain a breakdown voltage of the power MOSFET.
N- 드리프트 영역(10)은 N형 불순물이 낮게 도핑되어 형성된다.The N − drift region 10 is formed by low doping with N type impurities.
N- 드리프트 영역(10) 하부에는 N+형 불순물이 높게 도핑된 드레인 영역(18) 이 형성된다.A drain region 18 heavily doped with N + type impurities is formed under the N − drift region 10.
도 3은 본 발명의 일 실시 예에 따른 back to back 타입 다단 제너다이오드 소자를 내장하는 전력 모스펫 장치의 내부 등가 회로를 도시한 것이다.3 illustrates an internal equivalent circuit of a power MOSFET device having a back to back type multi-stage zener diode device according to an embodiment of the present invention.
도 3을 참조하면, 본 발명의 일 실시 예에 따른 back to back 타입 다단 제너다이오드(ED)는 전력 모스펫 장치의 게이트와 드레인에 병렬로 접속되는 구조로 형성된다. Referring to FIG. 3, a back to back type multi-stage zener diode (ED) according to an embodiment of the present invention is formed in a structure connected in parallel to the gate and the drain of the power MOSFET device.
본 발명의 일 실시 예에 따르면, 정전기(ESD)에 기인해 발생하는 일정 전압 이상의 펄스 고전압 및 순간적으로 외부에서 유입되는 써지전압은 back to back 타입 다단 제너다이오드(ED)로 흘려 보냄으로써, 내부 요소가 과도 전압에 의해 파괴되는 손상을 방지할 수 있다.According to an embodiment of the present invention, the pulse high voltage and the surge voltage flowing out from the outside instantaneously generated by the electrostatic discharge (ESD) flows to the back to back type multi-stage zener diode (ED), thereby internal elements It is possible to prevent the damage which is destroyed by the transient voltage.
본 발명의 일 실시 예에서, 전력 모스펫 장치의 정상 작동 전압의 범위를 초과하는 ESD전압 범위 및 회로 효율을 고려한 다양한 실험 결과, 상기 back to back 타입 다단 제너다이오드(ED)는, 폴리실리콘에 고농도의 N+형 반도체 불순물(30)과 저농도의 P-형 반도체불순물(31)이 교대로 4단 직렬로 접합되는 구조로 형성된다.According to one embodiment of the present invention, various experiment results in consideration of the ESD voltage range and the circuit efficiency exceeding the normal operating voltage range of the power MOSFET device, the back to back type multi-stage zener diode (ED) is a high concentration of polysilicon The N + -type semiconductor impurity 30 and the low concentration P − -type semiconductor impurity 31 are formed in such a manner that they are alternately joined in four stages in series.
또 다른 실시 예에서는, 폴리실리콘에 고농도의 N+형 반도체 불순물(30)과 저농도의 P-형 반도체불순물(31)이 교대로 3 ~ 5단 직렬로 접합되는 back to back 타입 다단 제너다이오드 소자 구조가 채택될 수 있다.In another embodiment, a back to back type multistage zener diode structure in which a high concentration of N + type semiconductor impurities 30 and a low level P-type semiconductor impurity 31 are alternately bonded to the polysilicon in series of 3 to 5 steps is formed. Can be adopted.
또한, 본 발명의 일 실시 예에 따르면, Electron-Hole pair 생성에 의한 breakdown 현상으로 발생되는 Avalanche가 일어나기 전에 Zener breakdown이 일어나도록 하는 공핍층 구조가 채택된다.In addition, according to an embodiment of the present invention, a depletion layer structure is adopted so that Zener breakdown occurs before Avalanche occurs due to a breakdown phenomenon caused by the generation of an Electron-Hole pair.
예를 들면, 폴리실리콘층에 고농도의 N+형 반도체 불순물이 주입된 영역(30)과 저농도의 P-형 반도체 불순물이 주입된 영역(31)의 도즈량 및 각 단의 폭이 이에 맞추어 설정된다.For example, the dose amount and width of each stage of the region 30 into which the polysilicon layer is implanted with high concentration of N + -type semiconductor impurities and the region 31 into which low concentration of P − -type semiconductor impurities are injected are set accordingly. .
또한, 상기 back to back 타입 다단 제너다이오드는 여러 단을 직렬로 접속한 형태로 형성하면 그 단수에 비례한 제너 전압이 확보될 수 있다.In addition, when the back to back type multi-stage zener diode is formed in a form in which several stages are connected in series, a zener voltage proportional to the number of stages may be secured.
한편, 본 발명의 back to back 타입 다단 제너다이오드에 적용되는 P-형 반도체 불순물의 경우 그 폭이 커지면 제너 전압은 증가되나, 온 상태의 저항이 증가하여 효율이 떨어질 수 있다. 또한, P-형 반도체 불순물을 더 많이 주입하면 제너 전압이 증가되고 온상태의 저항은 떨어지게 된다.On the other hand, in the case of the P − type semiconductor impurity applied to the back to back type multi-stage zener diode of the present invention, the zener voltage increases as the width thereof increases, but the resistance in the on state increases, so that the efficiency may decrease. In addition, when more P - type semiconductor impurities are injected, the zener voltage increases and the on-state resistance drops.
즉, 불순물층의 폭이 적정 폭보다 커지면 온 상태 저항이 증가하여 효율이 떨어지고, 불순물층의 폭이 작아지면 제너 BV(Break Voltage)가 떨어져서 비효율적이다. 또한, 불순물의 주입량(dose)이 적정량보다 적게 주입되면 BV가 낮아지게 된다.In other words, if the width of the impurity layer is larger than the appropriate width, the on-state resistance increases and the efficiency is lowered. If the width of the impurity layer is smaller, the Zener BV (Break Voltage) falls and is inefficient. In addition, the BV is lowered if the dose of impurities is less than the appropriate amount.
따라서, 과도전압 보호에 대한 신뢰성을 높이기 위해서는 불순물의 농도와 불순물의 폭 및 단수를 적정 수준으로 결정하는 것이 중요하다.Therefore, in order to increase the reliability of the transient voltage protection, it is important to determine the concentration of the impurity, the width and the number of the impurity to an appropriate level.
도 4, 5는 본 발명의 일 실시 예에 따른 P-형 반도체 불순물의 농도 및 폭에 따른 제너 전압 및 제너 저항의 변화를 그래프로 도시한 것이다.4 and 5 are graphs illustrating changes in zener voltage and zener resistance according to concentrations and widths of P - type semiconductor impurities according to an exemplary embodiment of the present invention.
도 4는 다양한 시물레이션을 통하여 P-형 반도체불순물의 농도 및 폭에 따른 제너 전류와 제너 전압과의 관계 결과를 그래프로 도시한 것이고, 도 5는 농도 및 폭에 따른 제너 전압 및 제너 저항의 변화를 그래프로 도시한 것이다.FIG. 4 is a graph showing the relationship between the zener current and the zener voltage according to the concentration and width of the P - type semiconductor impurity through various simulations, and FIG. 5 illustrates the change of the zener voltage and zener resistance according to the concentration and width. It is shown graphically.
도 5를 참조하면, P-width 3.5㎛에서는 P-dose 3.0e14 cm-2일 때가 온 상태 저항이 작게 형성되는 것을 알 수 있다.Referring to FIG. 5, it can be seen that the ON state resistance is small when P − dose 3.0e14 cm −2 is formed at P − width 3.5 μm.
또한, 상술한 범위의 P-반도체 불순물 형성 조건을 가지는 back to back 타입 다단 제너다이오드에서, N+형 반도체 불순물이 주입되는 영역의 형성 폭은 P-형 반도체 불순물이 주입되는 영역의 형성 폭보다 약간 큰 폭을 가질 때, Avalanche가 일어나기 전에 안정적인 Zener breakdown이 일어나는 것으로 실험되었다.In addition, in the back to back type multi-stage zener diode having the above-mentioned P - semiconductor impurity formation conditions, the formation width of the region into which the N + -type semiconductor impurities are implanted is slightly smaller than the formation width of the region into which the P - type semiconductor impurities are implanted At large widths, it was tested that a stable Zener breakdown occurred before Avalanche.
따라서, 바람직한 실시 예에서는 제너다이오드를 4단으로 형성한 back to back 타입 다단 제너다이오드에 대하여 폴리실리콘층에 P-형 반도체 불순물의 농도를 각각 다른 농도(2.8e14, 2.9e14, 3.0e14 )로 주입하고 서로 다른 넓이 폭으로 형성한다. 이 경우, 바람직한 최적의 범위는 도즈 전류가 일정 규모(1uA/um) 이하이면서 35V ~ 39V의 제너전압 범위에서P-width=3.5㎛, P-dose=3.0e14cm-2로 설정된다.Therefore, in the preferred embodiment, the concentration of P - type semiconductor impurities is injected into the polysilicon layer at different concentrations (2.8e14, 2.9e14, 3.0e14) for the back to back type multistage zener diode having four zener diodes. To form different widths. In this case, the preferred optimum range is set to P - width = 3.5 占 퐉 and P - dose = 3.0e14cm -2 in the zener voltage range of 35V to 39V while the dose current is below a certain scale (1uA / um).
본 발명의 일 실시 예에 따르면, 35V ~ 40V 사이에서 안정적인 Zener breakdown 전압을 가지는 back to back 타입 제너다이오드의 적정 실시 예는 폴리실리콘층에 N+ width=4um, N+dose=1.0.e16 cm-2로 주입되는 고농도의 반도체 불순물 영역과 P-width=3.5um, P-dose=3.0e14 cm-2로 주입되는 저농도의 반도체 불순물 영역이 교대로 4단으로 접합되며, 전체적으로 N+/P-/N+/P-/N+/P-/N+/P-/N+ 구조를 이루게 된다.According to one embodiment of the present invention, a suitable embodiment of the back to back type zener diode having a stable Zener breakdown voltage between 35V and 40V is N + width = 4um, N + dose = 1.0.e16 cm − in the polysilicon layer. a high concentration impurity region of the semiconductor with P that is injected into 2 - width = 3.5um, P - a semiconductor impurity region of low concentration is introduced into the dose = 3.0e14 cm -2 are in turn bonded to the 4-speed, overall N + / P - / N + / P - / N + / P - / N + / P - a / N + structure is formed.
본 발명의 또 다른 실시 예에서는 전력 모스펫 장치의 특성을 고려하여 폴리실리콘층에 N+ width = 3.5 ~ 4.5㎛, N+dose= 0.9 ~ 1.1e16 cm-2로 주입되는 고농도의 반도체 불순물 영역과 P-width = 3 ~ 4㎛, P-dose= 2.9 ~ 3.1e14 cm-2로 이루어지는 저농도의 반도체 불순물 영역이 교대로 3 ~ 5단으로 접합되는 구조로 형성될 수 있다.In another embodiment of the present invention, a high concentration of semiconductor impurity regions and P implanted into a polysilicon layer with N + width = 3.5 to 4.5 µm and N + dose = 0.9 to 1.1e16 cm -2 in consideration of characteristics of a power MOSFET device - width = 3 ~ 4㎛, P - can be formed of a dose = 2.9 ~ to a low-concentration impurity region of the semiconductor structure is bonded alternately with 3-5 made of 3.1e14 cm -2.
도 6는 본 발명의 일 실시 예에 따른 back to back 타입 다단 제너다이오드의 각 단별 형성되는 제너 전압을 그래프로 도시한 것이다.FIG. 6 is a graph illustrating zener voltages formed at each stage of a back to back type multi-stage zener diode according to an exemplary embodiment of the present invention.
도 6을 참조하면, back to back 타입 다단 제너다이오드는 여러 단을 직렬단으로 형성하면 그 단수에 비례하는 제너 전압이 확보될 수 있다.Referring to FIG. 6, when the back to back type multi-stage zener diode is formed in series, a zener voltage proportional to the number of stages may be secured.
본 발명의 일 실시 예에 따른 back to back 타입 다단 제너다이오드는, N+ 영역의 폭(width) 4um, N+의 불순물 농도(dose) 1.0e16cm-2로 이루어지는 고농도의 반도체 불순물 영역과 P- 영역의 폭(width)=3.5um P- 의 불순물 농도(dose) 3.0e14 cm-2로 이루어지는 저농도의 반도체 불순물 영역이 교대로 4단으로 접합되어 35V ~ 39V의 제어전압을 가지게 된다.The back to back type multi-stage zener diode according to an embodiment of the present invention has a high semiconductor impurity region and a P − region having a width of 4 μm of the N + region and 1.0e16 cm −2 of the impurity concentration of the N + . The semiconductor impurity regions of low concentration consisting of an impurity concentration (dose) of 3.0e14 cm −2 of width = 3.5um P − are alternately bonded in four stages to have a control voltage of 35V to 39V.
도 7은 본 발명의 일 실시 예에 따른 back to back 타입 다단 제너다이오드의 전압 특성을 나타낸 오실로스코프의 이미지를 도시한 것이다.FIG. 7 illustrates an image of an oscilloscope showing voltage characteristics of a back to back type multi-stage zener diode according to an embodiment of the present invention.
도 7을 참조하면 정방향의 전압이 공급될 때 정방향 제너 전압(Forward Voltage)은 39V이고, 역방향 제너 전압(Reverse Voltage)은 35V의 전기적인 특성을 나타낸다.Referring to FIG. 7, when a forward voltage is supplied, a forward zener voltage is 39V, and a reverse zener voltage is 35V.
도 8은 본 발명의 일 실시 예에 따른 back to back 타입 다단 제너다이오드를 내장하는 전력 반도체 장치 전력 모스펫 장치 칩의 평면 레이아웃을 도시한 것이다.8 illustrates a planar layout of a power semiconductor device power MOSFET device chip incorporating a back to back type multi-stage zener diode according to an embodiment of the present invention.
도 9은 도 8에서 A부분에 대한 단면 구조를 도시한 것이다.FIG. 9 illustrates a cross-sectional structure of part A of FIG. 8.
도 8, 9를 참조하면, 본 발명의 일 실시 예에 따른 과도 전압 보호용 back to back 타입 다단 제너다이오드는 게이트 패드 영역(200) 중 경계 영역(100) 하부에 형성된다.8 and 9, a back to back type multi-stage zener diode for transient voltage protection according to an embodiment of the present invention is formed under the boundary region 100 of the gate pad region 200.
게이트 패드 영역(200)의 경계 영역(100)은 게이트 패드와 소스 패드 사이에 형성된 패드 절연막 영역(210)을 포함하여 형성되며, 상기 절연막 영역(210) 하부에 본 발명의 일 실시 예에 따른 back to back 타입 다단 제너다이오드가 형성된다.The boundary region 100 of the gate pad region 200 is formed to include a pad insulating layer 210 formed between the gate pad and the source pad, and a back according to an embodiment of the present invention is disposed below the insulating layer 210. A to back type multistage zener diode is formed.
따라서 본 발명의 일 실시 예에 따른 과도전압 보호용 다이오드 소자를 내장하는 전력 반도체 장치는 전체 칩 사이즈의 변동이 없이 back to back 타입 제너다이오드를 내장할 수 있는 효과를 가진다.Therefore, a power semiconductor device incorporating a transient voltage protection diode device according to an embodiment of the present invention has an effect of embedding a back to back type zener diode without changing the overall chip size.
도 8의 (b)은 본 발명의 일 실시 예에 따른 도 8의 (a)의 A부분에 대한 back to back 타입 다단 제너다이오드의 등가 회로를 도시한 것이다.FIG. 8B illustrates an equivalent circuit of a back to back type multi-stage zener diode for part A of FIG. 8A according to an embodiment of the present invention.
도 8의 (b)을 참조하면, 본 발명의 일 실시 예에 따른 back to back 타입 다단 제너다이오드는 전체적으로 N+/P-/N+/P-/N+/P-/N+/P-/N+ 구조를 가지며 그 등가 회로는 back to back 타입 제너다이오드 4조가 직렬로 연결되는 구조이다.Referring to Fig. 8 (b), one back to back type multi-stage Zener diodes according to the embodiment of the present invention as a whole N + / P - / N + / P - / N + / P - / N + / P - / N + structure and its equivalent circuit is a structure in which four pairs of back to back type zener diodes are connected in series.
도 9을 참조하면 본 발명의 일 실시 예에 따른 back to back 타입 제너다이오드는, N+영역의 폭(a) 4㎛, 높이(c) 0.3㎛로 이루어지는 고농도의 반도체 불순물 영역과 P- 영역의 폭(b) 3.5㎛ 높이(c) 0.3㎛로 이루어지는 저농도의 반도체 불순물 영역이 교대로 4단으로 직렬 접합되도록 형성된다.Referring to Figure 9 back to back type according to one embodiment of the invention the zener diode, N + region of the width (a) 4㎛, the height (c) made of a high concentration of 0.3㎛ semiconductor impurity region and P - region of Low concentration semiconductor impurity regions of width (b) 3.5 µm height (c) 0.3 µm are alternately formed in series in four stages.
도 10 내지 도 24은 본 발명의 일 실시 예에 따른 과도전압 보호용 다이오드 소자가 내장된 전력 반도체 장치의 제조 공정을 도시한 것이다.10 to 24 illustrate a manufacturing process of a power semiconductor device incorporating a transient voltage protection diode device according to an embodiment of the present invention.
본 발명의 일 실시 예에 따른 과도전압 보호용 다이오드 소자가 내장된 전력 반도체 장치는, 먼저 N- 드리프트층(121)의 표면에 JFET층(122)을 형성하는 단계가 수행된다.In the power semiconductor device in which the transient voltage protection diode device is incorporated, the step of forming the JFET layer 122 on the surface of the N - drift layer 121 is performed.
도 10은 JFET층을 형성하기 위하여 N- 이온을 주입하는 공정을 도시한 것이다.10 shows a process for implanting N − ions to form a JFET layer.
JFET층(122)을 형성하는 단계에서는 준비된 N- drift층(121)의 표면에 전면으로 N 이온의 농도를 낮게 도핑하여 형성한다.In the step of forming the JFET layer 122 is formed by doping a low concentration of N ions to the entire surface of the prepared N - drift layer 121.
다음은, JFET층(122) 위에 제1 절연막(123)을 형성하는 단계가 수행된다.Next, the step of forming the first insulating film 123 on the JFET layer 122 is performed.
도 11은 본 발명의 일 실시 예에 따른 제1 절연막(123)이 형성된 공정을 도시한 것이다.11 illustrates a process in which the first insulating layer 123 is formed according to an embodiment of the present invention.
제1 절연막(123)은 Diffusion 공정을 이용하여 산화막을 만들 수도 있고, CVD 방법으로 산화막 Deposition을 하여 형성할 수 있다.The first insulating layer 123 may be an oxide film by using a diffusion process, or may be formed by depositing an oxide film by a CVD method.
본 발명의 일 실시 예에서는 SiO2를 사용하였으나, 제1 절연막(123)은 공정 특성에 따라 SiON, HfO 등을 사용하여 제조될 수 있다.In an embodiment of the present invention, SiO 2 is used, but the first insulating layer 123 may be manufactured using SiON, HfO, or the like depending on process characteristics.
다음은 POWER MOSFET 액티브 셀 영역이 형성되도록 마스킹 한 후, 상기 제1 절연막 중 POWER MOSFET 액티브 셀 영역 부분에 해당하는 부분에 대하여 상기 제1 절연막의 일부를 제거하는 단계를 수행한다.Next, after masking the POWER MOSFET active cell region to be formed, a portion of the first insulating layer may be removed from a portion corresponding to the POWER MOSFET active cell region of the first insulating layer.
도 12는 POWER MOSFET 액티브 셀 영역 부분에 해당하는 부분의 제1 절연막의 일부가 제거된 공정을 도시한 것이다.FIG. 12 illustrates a process in which a part of the first insulating film in a portion corresponding to a portion of the power MOSFET active cell region is removed.
본 발명의 일 실시 예에 따르면, POWER MOSFET 액티브 셀 영역 부분에 해당하는 부분의 제1 절연막을 제거하는 방법은 Photo Masking을 하여 Dry Etch로 벗겨내브 방법과, SiN 등을 위에 올린 후 Photo Masking한 이후에 POWER MOSFET Active cell 영역에 해당하는 부분의 SiN을 식각하고, 이후에 Wet Etch 공정으로 벗겨내는 방법중 어느 하나에 의하여 수행될 수 있다.According to an embodiment of the present invention, a method of removing the first insulating film of the portion corresponding to the POWER MOSFET active cell region portion may be performed by photomasking and peeling off with dry etching, and after placing SiN or the like on the photomasking method. It may be performed by any one of a method of etching the SiN of the portion corresponding to the area of the active power MOSFET active cell, and then peeled off by the wet etching process.
다음은, POWER MOSFET 액티브 셀 영역 부분에 해당하는 부분에 제2 절연막(124)을 형성하는 단계가 수행된다.Next, forming the second insulating film 124 in a portion corresponding to the portion of the power MOSFET active cell region is performed.
도 13은 POWER MOSFET 액티브 셀 영역 부분에 해당하는 부분에 제2 절연막(124)이 형성된 공정을 도시한 것이다.FIG. 13 illustrates a process in which a second insulating film 124 is formed in a portion corresponding to a portion of a power MOSFET active cell region.
제2 절연막(124)은 게이트 하부에 제1 절연막(123)과 다른 두께로 형성되는 게이트 절연막(124)이다.The second insulating layer 124 is a gate insulating layer 124 formed at a thickness different from that of the first insulating layer 123 under the gate.
제1 절연막(123)은 게이트 절연막인 제2절연막(124)의 두께의 1.4 ~ 1.6배 범위에서 형성되어 액티브 영역 및 back to back 타입 다단 제너다이오드 영역별로 서로 다른 두께를 가진다.The first insulating layer 123 is formed in a range of 1.4 to 1.6 times the thickness of the second insulating layer 124, which is a gate insulating layer, and has different thicknesses for the active region and the back to back type multi-stage zener diode region.
제1 절연막(123)은 본 발명의 일 실시 예에 따른 back to back 타입 제너다이오드가 형성되는 영역의 하부를 절연하기 위한 것으로서, 유입되는 과도 전압이 POWER MOSFET 액티브 셀 영역에 영향을 주는 것을 방지하기 위하여 게이트 절연막인 제2절연막(124) 보다 두껍게 형성된다.The first insulating layer 123 is to insulate the lower portion of the region where the back to back type zener diode is formed according to an embodiment of the present invention, and to prevent the incoming transient voltage from affecting the power MOSFET active cell region. The thickness of the second insulating layer 124 is greater than that of the gate insulating layer 124.
본 발명의 일 실시 예에 따르면, 게이트 절연막인 제2절연막(124)은 Diffusion 방식으로 산화막을 전면 성장시켜 형성된다.According to an embodiment of the present disclosure, the second insulating layer 124, which is a gate insulating layer, is formed by growing an entire oxide layer by a diffusion method.
또는, Si 표면이 드러난 상태의 POWER MOSFET Active cell 영역만 산화막이 잘 자라게 되고, Si 표면이 드러나지 않은 back to back 타입 다단 제너다이오드 영역은 산화막이 성장하지 않는 특징을 이용하여 웨이퍼(WF) 전체에 성장시켜 각기 영역별 두께가 다른 제1 절연막(123)과 제2 절연막(124)을 형성할 수 있다.Alternatively, the oxide film grows well in only the POWER MOSFET active cell region where the Si surface is exposed, and the back to back type multi-stage zener diode region in which the Si surface is not exposed is grown on the entire wafer WF using the feature that the oxide layer does not grow. The first insulating film 123 and the second insulating film 124 having different thicknesses for each region may be formed.
다음은 폴리실리콘층(126)을 형성하는 단계를 수행한다.Next, the polysilicon layer 126 is formed.
도 14는 제1, 2 절연막 위에 폴리실리콘층(126)이 형성된 공정을 도시한 것이다.FIG. 14 illustrates a process in which the polysilicon layer 126 is formed on the first and second insulating layers.
폴리실리콘층(126)은 POWER MOSFET Active cell 영역에서는 게이트를 형성하고 back to back 타입 제너다이오드 영역에서는 back to back 타입 제너다이오드를 형성하기 위한 것이다.The polysilicon layer 126 forms a gate in the POWER MOSFET active cell region and a back to back zener diode in the back to back zener diode region.
다음은 게이트를 형성하기 위하여 마스크를 이용하여 POWER MOSFET 액티브 셀 영역 중에서 게이트 영역을 제외하고 폴리실리콘층과 제2 절연막층의 나머지 중앙 영역(127)을 Photo etch 공정으로 식각하는 단계를 수행한다.Next, in order to form the gate, a photoetch process is performed to etch the remaining central region 127 of the polysilicon layer and the second insulating layer except for the gate region of the POWER MOSFET active cell region using a mask.
도 15는 POWER MOSFET 액티브 셀 영역 중에서 게이트 영역을 제외하고 폴리실리콘층과 제2 절연막층의 나머지 중앙 영역(127)이 식각된 공정을 도시한 것이다.FIG. 15 illustrates a process of etching the remaining central region 127 of the polysilicon layer and the second insulating layer except for the gate region of the POWER MOSFET active cell region.
다음은, Power MOSFET의 P- Body 및 Zener diode anode 영역을 형성하는 단계가 수행된다.Next, forming the P - body and Zener diode anode regions of the Power MOSFET is performed.
Power MOSFET P- Body 및 back to back 타입 다단 Zener diode의 anode 영역을 형성하는 단계에서는, 상기 식각된 폴리실리콘층 상부에 제1 PR(Photo Resist)용 마스크(mask)를 이용하여, Power MOSFET P- Body 및 Zener diode anode 영역을 형성하기 위한 공간을 형성하도록 masking을 한 후, P- 불순물을 낮은 농도로 주입하는 공정을 수행한다.In the forming of the anode regions of the power MOSFET P - body and the back to back type multi-stage Zener diode, a power MOSFET P − is formed by using a mask for a first photo resist (PR) on the etched polysilicon layer. After masking to form a space for forming the body and Zener diode anode regions, a process of implanting P − impurities at a low concentration is performed.
도 16은 제1 PR(Photo Resist)용 마스크(181)를 이용하여, Power MOSFET P- Body 및 back to back 타입 다단 제너다이오드의 anode 영역을 형성하기 위한 공간을 형성하도록 masking을 한 후, P- 형 반도체 불순물을 주입하는 공정을 도시한 것이다.16 is masked to form a space for forming an anode region of a power MOSFET P − body and a back to back type multi-stage zener diode using a mask 181 for a first photo resist (PR), and then P −. The process of injecting a type semiconductor impurity is shown.
본 발명의 일 실시 예에서는 상기 back to back 타입 다단 Zener diode의 anode 영역(131 ~ 134)은 폴리실리콘층(126)에 P- 형 반도체 불순물을 주입하여 폭 3.5㎛, 높이 0.3㎛ 범위로 4개가 형성된다.According to an embodiment of the present invention, the anode regions 131 to 134 of the back to back type multi-stage Zener diode are injected into the polysilicon layer 126 by injecting P − type semiconductor impurities into a range of 3.5 μm in width and 0.3 μm in height. Is formed.
본 발명의 또 다른 실시 예에 따르면, 상기 back to back 타입 다단 Zener diode의 anode 영역은 폭 3 ~ 4㎛, 높이 0.2 ~ 0.4㎛ 범위로 3 ~ 5개가 형성될 수 있다.According to another embodiment of the present invention, three to five anode regions of the back to back type multi-stage Zener diode may be formed in a range of 3 to 4 μm in width and 0.2 to 0.4 μm in height.
다음은, 상기 P- Body 내에 P+ Ohmic Contact 영역(129)을 형성하는 단계가 수행된다.Next, forming the P + Ohmic Contact region 129 in the P - Body is performed.
P+ Ohmic Contact 영역(129)을 형성하는 단계에서는, 상기 제1 PR(Photo Resist)용 마스크를 제거하고, 상기 식각된 폴리실리콘층 상부에 P- Body 영역의 중심부만 공간이 형성된 제2 PR(Photo Resist)용 마스크(182)를 이용하여, P- Body 영역(138)과 Contact로 연결된 Ohmic Contact 영역(129)을 형성하기 위해 P+ 불순물은 주입하는 공정이 수행된다.In the forming of the P + Ohmic Contact region 129, the second PR mask is removed, and only a central portion of the P − body region is formed on the etched polysilicon layer. Using the mask 182 for photo resist, a process of implanting P + impurities is performed to form an ohmic contact region 129 connected to the P − body region 138 by contact.
도 17은 P- Body 영역의 중심부만 공간이 형성된 제2 PR(Photo Resist)용 마스크(182)를 이용하여 P+ 불순물이 주입되는 공정을 도시한 것이다.FIG. 17 illustrates a process of injecting P + impurities using a second PR mask 182 having a space formed only in a central portion of the P − body region.
도 18은 P- body, back to back 타입 다단 Zener diode의 anode 영역 및 P+ Ohmic Contact 영역이 형성된 공정을 도시한 것이다.FIG. 18 illustrates a process of forming an anode region and a P + ohmic contact region of a P-body, a back to back type multi-stage Zener diode.
다음은 N+ Source 영역(141, 142) 및 back to back 타입 다단 Zener diode의 cathode 영역을 형성하는 단계를 수행한다.Next, the cathode regions of the N + source regions 141 and 142 and the back to back type multi-stage Zener diode are formed.
N+ Source 영역 및 back to back 타입 다단 Zener diode의 cathode 영역을 형성하는 단계에서는, 상기 제2 PR(Photo Resist)용 마스크를 제거하고, 상부에 N+ Source 영역 공간 및 Zener Diode cathode 영역 형성을 위한 공간이 형성된 제3 PR(Photo Resist)용 마스크(183)로 마스킹을 한 후, N+ Source 영역 및 Zener Diode cathode 영역을 형성하기 위한 N+ 형 반도체 불순물을 주입하는 공정이 수행된다.In the step of forming the cathode region of the N + source region and the back to back type multi-stage Zener diode, the mask for the second photo resist is removed, and the N + source region space and the Zener diode cathode region are formed thereon. After masking with a third PR (Photo Resist) mask having a space, a process of implanting N + type semiconductor impurities for forming an N + source region and a Zener diode cathode region is performed.
도 19는 제3 PR(Photo Resist)용 마스크(183)로 마스킹을 하고, N+ Source 영역(141, 142) 및 back to back 타입 다단 Zener diode의 cathode 영역(151 ~ 155)을 형성하기 위한 N+ 형 반도체 불순물을 주입하는 공정을 도시한 것이다.FIG. 19 is a mask 183 for a third PR (Photo Resist) mask, and N + source regions 141 and 142 and N for forming cathode regions 151 to 155 of a back to back type multi-stage Zener diode. The process of injecting + type semiconductor impurity is shown.
도 19는 본 발명의 일 실시 예에 따라 N+ 소스, back to back 타입 다단 Zener diode 영역이 형성된 공정을 도시한 것이다.19 illustrates a process in which an N + source, back to back type multi-stage Zener diode region is formed according to an embodiment of the present invention.
N+ 소스 영역(141, 142)은 N+ 소스 영역(141, 142)의 각 1/2 영역이 게이트 절연막(124)에 걸쳐지도록 확산하여 형성된다.The N + source regions 141 and 142 are formed by diffusing so that each half region of the N + source regions 141 and 142 spans the gate insulating film 124.
본 발명의 일 실시 예에 따르면, 안정적인 제너 전압을 형성하기 위하여 상기 back to back 타입 다단 Zener diode의 cathode 영역(N+영역)의 폭은 back to back 타입 다단 Zener diode의 anode 영역(P- 영역)의 폭보다 약간 두껍게 형성되도록 수행된다.According to an embodiment of the present invention, in order to form a stable zener voltage, the width of the cathode region (N + region) of the back to back type multistage Zener diode is the anode region (P − region) of the back to back type multistage Zener diode. It is carried out to form slightly thicker than the width of.
본 발명의 바람직한 실시 예에서는 상기 cathode 영역(N+영역)은 폴리실리콘층(126)에 N+ 형 반도체 불순물을 주입하여 폭 4㎛, 높이 0.3㎛ 범위로 상기 Zener diode anode 영역 사이에 5개가 형성된다.In the preferred embodiment of the present invention, five cathode regions (N + regions) are formed between the Zener diode anode regions having a width of 4 μm and a height of 0.3 μm by injecting N + type semiconductor impurities into the polysilicon layer 126. do.
본 발명의 또 다른 실시 예에 따르면, 상기 Zener diode cathode 영역은 폭 3.5 ~ 4.5 ㎛, 높이 0.2 ~ 0.4㎛ 범위로 4 ~ 6개가 형성될 수 있다.According to another embodiment of the present invention, four to six Zener diode cathode regions may be formed in a range of 3.5 to 4.5 μm in width and 0.2 to 0.4 μm in height.
다음은 상부에 제3 절연막층(143)이 형성되는 단계가 수행된다.Next, the third insulating layer 143 is formed on the top.
도 21은 상부에 제3 절연막층(143)이 형성된 공정을 도시한 것이다.FIG. 21 illustrates a process in which the third insulating layer 143 is formed thereon.
제3 절연막층(143)이 형성되는 단계에서는 PSG 또는 BPSG 또는 FSG 등의 SiO2 절연물을 CVD 방법으로 Deposition하여 형성되는 공정이 수행된다.In the step of forming the third insulating layer 143, a process of depositing a SiO 2 insulator such as PSG, BPSG, or FSG by CVD is performed.
다음은 소스 전극과 제너전극을 형성하고, 이들이 서로 연결되도록 형성된 금속 전극체(146)를 형성하는 단계가 수행된다. Next, a step of forming a source electrode and a zener electrode, and forming a metal electrode body 146 formed such that they are connected to each other is performed.
금속 전극체(146)를 형성하는 단계에서는 금속 전극체로 연결되는 부분인 N+ 소스 영역(141, 142)의 각 1/2 영역을 포함하는 소스 전극 공간 및 제너다이오드의 일측 의 단자 공간을 에칭하는 공정을 수행한 후, 상기 에칭된 공간에 금속 전극체(146)를 형성하는 공정을 수행한다.In the forming of the metal electrode body 146, the source electrode space including each half region of the N + source regions 141 and 142, which are parts connected to the metal electrode body, and the terminal space on one side of the zener diode are etched. After performing the process, a process of forming the metal electrode body 146 in the etched space is performed.
본 발명의 일 실시 예에 따르면, 상기 에칭하는 공정은 Dry Etch공정으로 진행하며, N+ Source 영역, P+ Ohmic Contact 영역, back to back 타입 다단 Zener diode의 일측 cathode영역이 모두 금속 전극체에 의하여 연결될 수 있도록 한번에 Etching을 하여준다.According to one embodiment of the present invention, the etching process proceeds to a dry etching process, the N + Source region, P + Ohmic Contact region, one cathode region of the back to back type multi-stage Zener diode all by the metal electrode body Etching at once to be connected.
도 22는 제3 절연막층에서 금속 전극체가 연결될 공간이 에칭된 공정을 도시한 것이다.FIG. 22 illustrates a process of etching the space where the metal electrode body is to be connected in the third insulating layer.
본 발명의 일 실시 예에 따르면, 에칭된 공간에 금속 전극체를 형성하는 공정은 Al 등의 금속 도전체(146)를 Sputtering 또는 Metal Deposition 방법을 사용하여 채워 넣는다.According to an embodiment of the present invention, the process of forming the metal electrode body in the etched space is filled with a metal conductor 146 such as Al using a Sputtering or Metal Deposition method.
본 발명의 일 실시 예에 따르면, Power MOSFET 소스와 back to back 타입 다단 Zener diode의 일측 캐소드가 모두 한번에 연결되도록 금속 전극체(146)를 일체형으로 형성될 수 있다.According to an embodiment of the present disclosure, the metal electrode body 146 may be integrally formed such that the power MOSFET source and the one side cathode of the back to back type multi-stage Zener diode are all connected at once.
도 23은 Power MOSFET 소스와 back to back 타입 다단 Zener diode의 일측단 cathode가 연결된 금속 도전체(146)가 형성된 공정을 도시한 것이다.FIG. 23 illustrates a process in which a metal conductor 146 is connected to a power MOSFET source and a cathode of one end of a back to back type multistage Zener diode.
다음은 바닥면의 N+ Drain 을 형성하는 단계가 수행된다.Next, a step of forming N + Drain of the bottom surface is performed.
도 24는 N+ Drain 을 형성하기 위하여 바닥면에 N+ 형 반도체 불순물을 주입하는 공정을 도시한 것이다.FIG. 24 illustrates a process of injecting N + type semiconductor impurities into the bottom surface to form N + Drain.
본 발명의 일 실시 예에 따르면, 금속 도전체(146)를 형성하는 공정을 포함하여 상부 공정의 마무리 이후, N+ Drain을 형성하는 단계에서는 상부 측이 오염이나 침해되지 않도록 보호필름 등을 부착한 후, 뒤집어서 웨이퍼 바닥면에 N+ 불순물을 전면 주입하는 공정이 수행된다.According to an embodiment of the present invention, after the completion of the upper process, including the process of forming the metal conductor 146, in the step of forming the N + Drain to attach a protective film or the like so that the upper side is not contaminated or invaded After that, a process of inverting and injecting N + impurities entirely onto the bottom surface of the wafer is performed.
본 발명의 일 실시 예에 따른 과도전압 보호용 다이오드 소자를 내장하는 전력 반도체 장치 제조 방법에 의하면, 과도전압 보호용 다이오드 소자를 내장하기 위한 별도의 추가 공정 단계가 요구되지 않으며, POWER MOSFET Active cell 제조 공정을 활용하여 과도전압 보호용 다이오드 소자를 형성하는 공정을 병행하여 수행하도록 함으로써 공정의 효율성을 높일 수 있다.According to the method of manufacturing a power semiconductor device incorporating a transient voltage protection diode device according to an embodiment of the present invention, a separate additional process step for embedding the transient voltage protection diode device is not required, and a power MOSFET active cell manufacturing process is performed. The efficiency of the process can be increased by performing the process of forming a diode element for transient voltage protection in parallel.

Claims (14)

  1. 소스 패드와 게이트 패드 사이에 패드 절연막을 포함하는 전력 반도체 장치에 있어서,A power semiconductor device comprising a pad insulating film between a source pad and a gate pad,
    상기 패드 절연막을 포함하는 상기 게이트 패드의 경계 영역 하부에는 폴리 실리콘층이 형성되며,A polysilicon layer is formed under the boundary region of the gate pad including the pad insulating layer.
    상기 폴리실리콘층은 제1 형 반도체 불순물이 고농도로 도핑되는 제1 형 반도체 영역과 제2 형 반도체 불순물이 저농도로 도핑되는 제2 형 반도체 영역이 교대로 다단 직렬로 형성된 다단 제너 다이오드가 형성되는 것을 포함하며,The polysilicon layer may include a multi-stage zener diode in which a first type semiconductor region in which a first type semiconductor impurity is heavily doped and a second type semiconductor region in which a second type semiconductor impurity is lowly doped are alternately formed in series. Include,
    상기 다단 제너다이오드의 일측단은 상기 게이트 패드 영역에 인접된 액티브 셀 영역에 형성된 전력 모스펫 셀의 일측 게이트에 연결되도록 접속되고 상기 다단 제너다이오드 영역의 타측단은 상기 전력 모스펫 셀의 소스 전극에 연결되도록 접속되는 것을 특징으로 하는 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치One end of the multistage zener diode is connected to one gate of a power MOSFET cell formed in an active cell region adjacent to the gate pad region and the other end of the multistage zener diode region is connected to a source electrode of the power MOSFET cell. Power semiconductor device containing a diode device for transient voltage protection, characterized in that connected
  2. 제1 항에 있어서,According to claim 1,
    상기 다단 제너 다이오드의 하부에는 제2 절연막이 형성되며, 상기 제2 절연막은 상기 전력 모스펫 셀의 게이트 절연막의 두께의 1.4 ~ 1.6 배의 두께를 가지는 것을 특징으로 하는 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치A second insulating film is formed below the multi-level zener diode, and the second insulating film has a thickness of 1.4 to 1.6 times the thickness of the gate insulating film of the power MOSFET cell. Semiconductor devices
  3. 제1 항에 있어서,According to claim 1,
    상기 제1 형 반도체 불순물은 P-형 반도체 불순물이며, 제2 형 반도체불순물은 N+형 반도체 불순물이며,The first type semiconductor impurity is a P − type semiconductor impurity, the second type semiconductor impurity is an N + type semiconductor impurity,
    상기 다단 제너 다이오드는 N+형 반도체 불순물이 캐소드로 작용하는 제너다이오드가 back to back 타입으로 3 ~ 5단 직렬로 접속된 구조인 것을 특징으로 하는 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치The multi-stage Zener diode is a power semiconductor device having a diode structure for transient voltage protection, wherein a Zener diode in which N + type semiconductor impurities act as a cathode is connected in series of 3 to 5 steps in a back to back type.
  4. 제3 항에 있어서,The method of claim 3, wherein
    상기 제1 형 반도체 영역의 폭은 3 ~ 4㎛이고, 상기 제2 형 반도체 영역의 폭은 3.5 ~ 4.5㎛인 것을 특징으로 하는 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치 The width of the first type semiconductor region is 3 ~ 4㎛, the width of the second type semiconductor region is 3.5 ~ 4.5㎛ power semiconductor device with a built-in transient voltage protection diode element
  5. 제 3항에 있어서,The method of claim 3, wherein
    상기 제1 형 반도체 영역은 P-형 반도체 불순물이 2.9 ~ 3.1e14 cm-2 농도로 주입되며, 제2 반도체 영역은 N+형 반도체 불순물이 0.9 ~ 1.1e16 cm-2 농도로 주입된 것을 특징으로 하는 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치 The first type semiconductor region is implanted with a concentration of 2.9 ~ 3.1e14 cm -2 P - type semiconductor impurities, the second semiconductor region is implanted with a concentration of 0.9 ~ 1.1e16 cm -2 N + type semiconductor impurities Power semiconductor device with built-in diode for transient voltage protection
  6. 제1 항에 있어서,According to claim 1,
    상기 제1 형 반도체 불순물은 P-형 반도체 불순물이며, 제2 형 반도체불순물은 N+형 반도체 불순물이며,The first type semiconductor impurity is a P − type semiconductor impurity, the second type semiconductor impurity is an N + type semiconductor impurity,
    상기 다단 제너 다이오드는 N+형 반도체 불순물이 캐소드로 작용하는 제너다이오드가 back to back 타입으로 4단 직렬로 접속된 구조이고,The multi-stage Zener diode has a structure in which a Zener diode in which N + type semiconductor impurities act as a cathode is connected in series in a back to back type,
    상기 제1 형 반도체 영역의 폭은 3.5㎛이고, 상기 제2 형 반도체 영역의 폭은 4㎛이며, 상기 제1 형 반도체 영역은 P-형 반도체 불순물이 2.9 ~ 3.1e14 cm-2 농도로 주입된 것이고, 제2 반도체 영역은 N+형 반도체 불순물이 1.0e16 cm-2 농도로 주입된 것을 특징으로 하는 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치 The width of the first type semiconductor region is 3.5 μm, the width of the second type semiconductor region is 4 μm, and the first type semiconductor region is implanted with a P − type semiconductor impurity at a concentration of 2.9 to 3.1e14 cm −2 . The second semiconductor region is a power semiconductor device incorporating a transient voltage protection diode element, wherein the N + -type semiconductor impurity is injected at a concentration of 1.0e16 cm -2 .
  7. 제6 항에 있어서,The method of claim 6,
    상기 다단 제너 다이오드는 0.3㎛ 높이로 형성된 것을 특징으로 하는 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치 The multi-stage zener diode is a power semiconductor device with a built-in transient voltage protection diode element, characterized in that formed in 0.3㎛ height
  8. 제1 항에 있어서,According to claim 1,
    상기 제1 형 반도체 불순물은 P-형 반도체 불순물이며, 제2 형 반도체불순물은 N+형 반도체 불순물이며,The first type semiconductor impurity is a P − type semiconductor impurity, the second type semiconductor impurity is an N + type semiconductor impurity,
    상기 다단 제너 다이오드는 back to back 타입으로서 N+형 반도체 불순물이 캐소드로 작용하는 N+/P-/N+/P-/N+/P-/N+/P-/N+ 구조를 가지는 것을 특징으로 하는 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치 The multi-stage Zener diodes are N + / P, which is N + type semiconductor impurity acting as a cathode as a back to back type - that has a / N + structure - / N + / P - / N + / P - / N + / P Power semiconductor device with built-in transient voltage protection diode element
  9. 전력 반도체 장치를 제조하는 방법에 있어서,In the method of manufacturing a power semiconductor device,
    (a) 다단 제너 다이오드가 형성되는 영역에 제1 절연막을 형성하는 단계;(a) forming a first insulating film in a region where the multistage zener diode is formed;
    (b) 전력 모스펫 셀이 형성되는 영역에 제2 절연막을 형성하는 단계;(b) forming a second insulating film in a region where the power MOSFET cell is formed;
    (c) 상기 제1, 2 절연막 위에 폴리실리콘층을 형성하는 단계;(c) forming a polysilicon layer on the first and second insulating films;
    (d) 상기 전력 모스펫 셀이 형성되는 영역 중에서 게이트 영역을 제외한 상기 폴리실리콘층과 제2 절연막층의 중앙 영역을 식각하는 단계;(d) etching a central region of the polysilicon layer and the second insulating layer except for a gate region among regions where the power MOSFET cell is formed;
    (e) 제1 마스크를 이용하여 P- 형 반도체 불순물을 주입하여 상기 전력 모스펫의 P- Body 및 상기 폴리실리콘층에 상기 다단 제너다이오드의 애노드 영역을 형성하는 단계;(e) implanting a P − type semiconductor impurity using a first mask to form an anode region of the multi-stage zener diode in the P-body and the polysilicon layer of the power MOSFET;
    (f) 제2 마스크를 이용하여 상기 P- Body 내에 P+ 형 반도체 불순물을 주입하여 P+ Ohmic Contact 영역을 형성하는 단계;(f) implanting an impurity in the P + type semiconductor P- Body by using a second mask to form the P + Ohmic Contact area;
    (g) 제3 마스크를 이용하여 N+ 형 반도체 불순물을 주입하여 상기 전력 모스펫의 N+ Source 영역 및 상기 폴리실리콘층에 상기 back to back 타입 다단 제너다이오드의 캐소드 영역을 형성하는 단계;(g) implanting N + type semiconductor impurities using a third mask to form a cathode region of the back to back type zener diode in the N + Source region and the polysilicon layer of the power MOSFET;
    (h) 상기 (g) 단계 이후에 상부 전체에 제3 절연층을 형성하는 단계;(h) forming a third insulating layer over the entire upper part after step (g);
    (i) 소스 전극 공간 및 상기 다단 제너다이오드의 일측 단자 공간을 에칭하는 단계; 및(i) etching the source electrode space and one side terminal space of the multi-stage zener diode; And
    (j) 상기 에칭된 공간을 금속물로 메꾸어서 소스 전극과 상기 다단 제너다이오드의 일측 단자 전극을 연결하는 금속 전극체를 형성하는 단계;(j) filling the etched space with a metal material to form a metal electrode body connecting the source electrode and one terminal electrode of the multi-stage zener diode;
    를 포함하는 것을 특징으로 하는 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치 제조 방법Method of manufacturing a power semiconductor device with a built-in transient voltage protection diode element comprising a
  10. 제9 항에 있어서,The method of claim 9,
    소스 패드와 게이트 패드 사이에 패드 절연막을 포함하는 상기 전력 반도체 장치에서, 상기 다단 제너 다이오드는, 상기 패드 절연막을 포함하는 상기 게이트 패드의 경계 영역 하부에 형성되는 것을 특징으로 하는 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치 제조 방법The power semiconductor device including a pad insulating film between a source pad and a gate pad, wherein the multi-stage zener diode is formed under the boundary region of the gate pad including the pad insulating film. Built-in power semiconductor device manufacturing method
  11. 제9 항에 있어서, The method of claim 9,
    상기 (e) 단계에서 상기 애노드 영역은 폭 3 ~ 4㎛ 범위로 3 ~ 5개가 형성되는 것을 특징으로 하는 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치 제조 방법In the step (e), the anode region is a power semiconductor device manufacturing method with a built-in transient voltage protection diode element, characterized in that three to five are formed in the range of 3 ~ 4㎛ width.
  12. 제9 항에 있어서, The method of claim 9,
    상기 (g) 단계에서 상기 캐소드 영역은 폭 3.5 ~ 4.5 ㎛ 범위로 4 ~ 6개가 형성되는 것을 특징으로 하는 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치 제조 방법In the step (g), the cathode region is a power semiconductor device manufacturing method with a built-in transient voltage protection diode element, characterized in that 4 to 6 are formed in the range of 3.5 to 4.5 ㎛ width.
  13. 제9 항에 있어서,The method of claim 9,
    상기 제1 절연막은 상기 제2절연막의 1.4 ~ 1.6 배의 두께로 형성되는 것을 특징으로 하는 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치 제조 방법The first insulating film is 1.4 ~ 1.6 times the thickness of the second insulating film is a power semiconductor device manufacturing method containing a transient voltage protection diode element, characterized in that formed.
  14. 제9 항에 있어서,The method of claim 9,
    상기 (e)단계에서 상기 애노드 영역은 폭 3.5㎛ 범위로 4개가 형성되며 P-형 불순물의 농도가 3.0e14 cm-2로 주입되며, 상기 (g) 단계에서 상기 캐소드 영역은 폭 4㎛ 범위로 5개가 형성되며, N+불순물의 농도가 1.0e16 cm-2로 주입되는 것을 특징으로 하는 과도전압 보호용 다이오드 소자를 내장한 전력 반도체 장치 제조 방법In the step (e), four anode regions are formed with a width of 3.5 μm, and the concentration of the P - type impurities is injected at 3.0e14 cm −2 . In the step (g), five cathode regions are formed in a range of 4 μm in width, and a N + impurity concentration is injected at 1.0e16 cm −2 to manufacture a power semiconductor device incorporating a transient voltage protection diode element. Way
PCT/KR2014/012777 2014-12-24 2014-12-24 Power semiconductor device having over-voltage protection diode element embedded therein and manufacturing method therefor WO2016104825A1 (en)

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JPH09186315A (en) * 1995-12-28 1997-07-15 Hitachi Ltd Semiconductor device
JPH10321857A (en) * 1997-03-17 1998-12-04 Fuji Electric Co Ltd Mos semiconductor device having high breakdown strength
JP2000174272A (en) * 1998-12-09 2000-06-23 Mitsubishi Electric Corp Power semiconductor element
JP2011003728A (en) * 2009-06-18 2011-01-06 Fuji Electric Systems Co Ltd Semiconductor device
WO2011093472A1 (en) * 2010-01-29 2011-08-04 富士電機システムズ株式会社 Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09186315A (en) * 1995-12-28 1997-07-15 Hitachi Ltd Semiconductor device
JPH10321857A (en) * 1997-03-17 1998-12-04 Fuji Electric Co Ltd Mos semiconductor device having high breakdown strength
JP2000174272A (en) * 1998-12-09 2000-06-23 Mitsubishi Electric Corp Power semiconductor element
JP2011003728A (en) * 2009-06-18 2011-01-06 Fuji Electric Systems Co Ltd Semiconductor device
WO2011093472A1 (en) * 2010-01-29 2011-08-04 富士電機システムズ株式会社 Semiconductor device

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