JP2012084914A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for a trench gate power MISFET including a dummy gate electrode capable of preventing electrostatic breakdown of a gate insulator while achieving performance improvement of MISFET.SOLUTION: A trench gate power MISFET including a dummy gate electrode 9a, and a protective diode are formed on the same semiconductor substrate 1. The protective diode is disposed between a source electrode 24 and gate wiring 25. A manufacturing method of the above-described semiconductor device comprises the steps of simultaneously forming a polysilicon film for the dummy gate electrode 9a and a polysilicon film for the protective diode, and forming the source region of the power MISFET and an ntype semiconductor region 15 of the protective diode are formed in the same process.

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly, to a power MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a trench gate configuration including a dummy gate electrode and a technique effective when applied to the manufacturing thereof.

  Japanese Patent No. 3413569 (Patent Document 1) discloses a structure in which a power MISFET 101 having a trench gate configuration, a planar gate type MISFET 102, and a protection diode 103 are formed on the same substrate as shown in FIG. In the formation process of this structure, the polysilicon film constituting the gate electrode of the power MISFET 101 and the polysilicon film constituting the protection diode 103 are formed in separate steps. The polysilicon film constituting the gate electrode is formed thicker than the polysilicon film constituting the protective diode 103. The source region of the power MISFET 101 and the cathode of the protection diode are formed in the same process.

  Japanese Patent Laying-Open No. 2000-307109 (Patent Document 2) discloses a structure in which a planar gate type power MISFET and a protection diode are formed on the same substrate. In the formation process of this structure, the polysilicon film constituting the gate electrode of the planar gate type power MISFET and the polysilicon film constituting the protection diode are formed in the same process. Further, the source region of the planar gate type power MISFET and the cathode of the protection diode are formed in the same process.

  US Pat. No. 5,998,833 (Patent Document 3) discloses a power MISFET having a trench gate structure including a dummy gate electrode. In this power MISFET, the dummy gate electrode is connected to the source potential.

  Japanese Patent Laying-Open No. 63-296282 (Patent Document 4) discloses a power MISFET having a trench gate structure including a dummy gate electrode. In this power MISFET, the dummy gate electrode is connected to a positive potential.

  Japanese Patent Laying-Open No. 04-229662 (Patent Document 5) discloses a power MISFET having a trench gate structure including a dummy gate electrode. In this power MISFET, the dummy gate electrode is in a floating state.

Japanese Patent No. 3413569 JP 2000-307109 A US Pat. No. 5,998,833 JP 63-296282 A Japanese Patent Laid-Open No. 04-229662

  A power MISFET (field effect transistor) having a trench gate structure has a structure in which a gate electrode is embedded in a trench dug in a main surface of a semiconductor substrate via a gate insulating film. And while providing in the surface layer part of the main surface of a semiconductor substrate, the drain region is provided in the back surface on the opposite side to the main surface of a semiconductor substrate. A channel is formed in the semiconductor region between the source region and the drain region and facing the side surface of the gate electrode provided in the trench. Thereby, a current flows between the source region and the drain region via the channel. That is, the power MISFET having a trench gate configuration is configured such that current flows in the vertical direction (the thickness direction of the semiconductor substrate).

  In recent years, a power MISFET having a trench gate structure provided with a dummy gate electrode has been developed by improving the power MISFET having the trench gate structure described above. The power MISFET having a trench gate structure provided with the dummy gate electrode is provided by laminating a dummy gate electrode and a gate electrode in a trench dug in the main surface of the semiconductor substrate, and the dummy gate electrode and the gate electrode are provided with an insulating film. It has an insulated structure. An insulating film is formed between the dummy gate electrode and the trench, and a gate insulating film is formed between the gate electrode and the trench. By providing the dummy gate electrode in this manner, parasitic capacitance (feedback capacitance) generated between the gate electrode and the drain region can be reduced. That is, a non-negligible parasitic capacitance is generated between the gate electrode formed in the trench and the drain region formed on the back surface of the semiconductor substrate. However, a dummy gate electrode is provided between the gate electrode and the drain region, and by connecting the dummy gate electrode to the source potential, a shielding effect for reducing parasitic capacitance can be obtained. Therefore, the parasitic effect between the gate electrode and the drain region can be reduced by the shielding effect by the dummy gate electrode, and therefore, an advantage that high-speed switching can be realized as compared with the power MISFET having the trench gate configuration without the dummy gate electrode. There is.

  Further, when a voltage is applied to the drain region with the gate and source regions grounded, the electric field is strongest at the bottom of the trench. For this reason, the breakdown voltage (BVdss) is determined by the voltage at which avalanche breakdown occurs near the bottom of the groove. However, in a power MISFET having a trench gate configuration provided with a dummy gate electrode, the electric field at the bottom of the groove is weakened due to the electric field relaxation effect of the dummy gate electrode, and avalanche breakdown near the bottom of the groove can be made difficult to occur. . Therefore, there is an advantage that the breakdown voltage (BVdss) can be improved. For this reason, power MISFETs having a trench gate structure having a dummy gate electrode have been used. Note that the breakdown voltage (BVdss) is a breakdown voltage when a voltage is applied between the source region and the drain region in a state where the gate electrode is short-circuited with the source region.

  Here, in a power MISFET having a trench gate configuration without a dummy gate electrode, even if an attempt is made to improve the performance of the MISFET by thinning the gate insulating film, a corner (weak spot) at the bottom of the groove in which the gate electrode is embedded For example, a gate insulating film formation failure is likely to occur. For this reason, the gate insulating film cannot be thinned. On the other hand, in a power MISFET having a trench gate configuration including a dummy gate electrode, a dummy gate electrode is formed at the corner of the groove bottom via an insulating film. This insulating film is set to be thicker than the gate insulating film so that the electric field at the bottom of the trench can be relaxed and the breakdown voltage (BVdss) can be improved. For this reason, even if the gate insulating film is thinned, the corner of the groove bottom does not become a weak spot. For this reason, a power MISFET having a trench gate configuration including a dummy gate electrode has an advantage that high performance of the MISFET can be easily realized by reducing the on-resistance by reducing the thickness of the gate insulating film.

  However, when the gate insulating film is made thin, there arises a problem that the electrostatic breakdown resistance of the gate insulating film is lowered. That is, by making the gate insulating film thin, it is possible to realize high performance of the MISFET, but there arises a problem that the electrostatic breakdown resistance of the MISFET with respect to noise such as static electricity (surge) is lowered.

  In addition, in power MISFETs for automobile applications, there is an increasing need for mounting a protection circuit against noise such as static electricity.

  An object of the present invention is to provide a technique capable of preventing electrostatic breakdown of a gate insulating film while improving the performance of a MISFET in a power MISFET having a trench gate configuration including a dummy gate electrode.

  Another object of the present invention is to provide a technique capable of easily forming a structure for preventing electrostatic breakdown of a gate insulating film in a manufacturing technique of a power MISFET having a trench gate configuration including a dummy gate electrode.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to the present invention is a semiconductor device in which a field effect transistor and a diode are formed on the same semiconductor substrate, the drain region of the field effect transistor formed on the semiconductor substrate, and on the drain region A channel formation region of the field effect transistor formed; and a source region of the field effect transistor formed on the channel formation region. A groove reaching the drain region from the upper surface of the source region; a first insulating film formed in the groove; and a first conductive film formed on the first insulating film in the groove; And a gate insulating film of the field effect transistor formed on the first conductive film in the trench. A gate electrode of the field effect transistor formed on the gate insulating film in the trench; a second conductive film formed on the semiconductor substrate and made of the same layer as the first conductive film; An anode region and a cathode region of the diode are formed in the second conductive film. The anode region and the cathode region of the diode are electrically connected to the gate electrode or the source region of the field effect transistor, respectively.

  The semiconductor device according to the present invention includes (a) a field effect transistor having a trench gate configuration including a dummy gate electrode, and (b) a protection diode for protecting the field effect transistor from electrostatic breakdown. The field effect transistor and the protection diode are formed on the same semiconductor substrate.

  In addition, a method for manufacturing a semiconductor device according to the present invention relates to a method for manufacturing a semiconductor device having a field effect transistor having a trench gate configuration including a dummy gate electrode and a protection diode for protecting the field effect transistor from electrostatic breakdown. is there. The protective diode polysilicon film constituting the protection diode and the dummy electrode polysilicon film constituting the dummy gate electrode are formed in the same step. Further, the cathode of the protection diode and the source region of the field effect transistor are formed in the same process.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since the power MISFET having the trench gate configuration including the dummy gate electrode and the protection diode are formed on the same semiconductor substrate, electrostatic breakdown of the gate insulating film can be prevented while improving the performance of the MISFET.

  The protective diode polysilicon film constituting the protection diode and the dummy electrode polysilicon film constituting the dummy gate electrode are formed in the same process. In addition, the cathode of the protective diode and the source region of the power MISFET having a trench gate configuration including a dummy gate electrode are formed in the same process. As a result, it is possible to easily form a power MISFET and a protection diode having a trench gate configuration including a dummy gate electrode while suppressing the complexity of the processing process.

It is sectional drawing which showed the structure of the semiconductor device which the present inventors examined. It is the top view which showed the semiconductor device in embodiment of this invention. It is sectional drawing cut | disconnected by the AA line of FIG. It is sectional drawing cut | disconnected by the BB line of FIG. 5 is a diagram illustrating an example of a circuit using the semiconductor device in Embodiment 1. FIG. It is sectional drawing which showed the manufacturing process of the semiconductor device in embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; It is the top view which showed the manufacturing process of the semiconductor device in embodiment. FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12; It is the top view which showed the manufacturing process of the semiconductor device in embodiment. FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 15; It is the top view which showed the manufacturing process of the semiconductor device in embodiment. FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 19 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 18; It is the top view which showed the manufacturing process of the semiconductor device in embodiment. FIG. 20 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 19; It is the top view which showed the manufacturing process of the semiconductor device in embodiment. FIG. 22 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 21; 4 is a plan view illustrating an example of a layout configuration of a semiconductor device in an embodiment. FIG. 4 is a plan view illustrating an example of a layout configuration of a semiconductor device in an embodiment. FIG.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  Embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. In order to make the figure easy to see, even a plan view may be hatched.

  FIG. 2 is a schematic plan view showing the semiconductor chip CP in the present embodiment. As shown in FIG. 2, the source electrode 24 of the power MISFET is formed in the central portion of the semiconductor chip CP, and a part of the source electrode 24 serves as the source pad SP. That is, although not shown in FIG. 2, a polyimide resin film is formed as a surface protective film on the main surface of the semiconductor chip CP, and a part of the source electrode 24 is exposed from the polyimide resin film. Thus, a source pad SP is formed.

  A gate wiring 25 is formed so as to surround the outer periphery of the source electrode 24. The gate wiring 25 is also covered with a polyimide resin film, and a part of the gate wiring 25 is exposed from the polyimide resin film to form a gate pad GP. A bonding wire or the like is connected to the source pad SP and the gate pad GP.

A plurality of n ⁺ type semiconductor regions 15 and p ⁻ type semiconductor regions 8a are formed between the source electrode 24 and the gate pad GP. In other words, a plurality of protective diodes (zener diodes) made of pn junctions are formed between the source electrode 24 and the gate pad GP. In FIG. 2, two pairs of protective diodes are connected in series between the source electrode 24 and the gate pad GP so as to be connected back to back. Specifically, two pairs of protection diodes connecting anode electrodes (p ⁻ type semiconductor regions 8a which are anode regions) are connected in series, and cathode electrodes of the pair of protection diodes (n ⁺ type which is a cathode region). The semiconductor region 15) is connected to the gate wiring 25. The cathode electrode (n ⁺ type semiconductor region 15) of another pair of protective diodes is connected to the source electrode 24.

  3 is a cross-sectional view showing a cross section taken along line AA of FIG. In FIG. 3, an n-type epitaxial layer 2 into which an n-type impurity is introduced is formed on a semiconductor substrate 1, and a p-type well 3 into which a p-type impurity is introduced is formed in the n-type epitaxial layer 2. Has been. An element isolation region 4 for isolating elements is formed in a predetermined region on the n-type epitaxial layer 2. An n-channel power MISFET is formed in the active region isolated by the element isolation region 4. The p-type well 3 is provided to form a pn junction having a high breakdown voltage, and is connected to the source potential.

  The n-channel type power MISFET has a source region 14 which is a semiconductor region provided in the n-type epitaxial layer 2 and a drain region composed of the n-type epitaxial layer 2 and the semiconductor substrate 1. A channel-forming semiconductor region (channel forming region) 13 is formed in the n-type epitaxial layer 2 between the source region 14 and the drain region. For example, phosphorus (P) or arsenic (As) is introduced into the source region 14, and boron (B) is introduced into the semiconductor region 13 for forming the channel.

  A plurality of grooves 6 extending in a direction orthogonal to the main surface of the semiconductor substrate 1 (a thickness direction of the semiconductor substrate 1) are formed on the main surface of the semiconductor substrate 1. The groove 6 is formed so as to penetrate the semiconductor region 13 for channel formation from the main surface of the semiconductor substrate 1 and terminate at the lower part of the n-type epitaxial layer 2. That is, the trench 6 is formed so as to reach the drain region from the upper surface of the source region 14.

  In FIG. 3, a dummy gate electrode 9 a is formed below the inside of the two grooves 6 on the right side via an insulating film (first insulating film) 7. A gate electrode 11 a is formed above the inside of the trench 6 with a gate insulating film 10 interposed therebetween. Both the insulating film 7 and the gate insulating film 10 are made of, for example, a silicon oxide film, but the insulating film 7 is formed thicker than the gate insulating film 10. Specifically, the insulating film 7 has a thickness of about 200 nm, for example, and the gate insulating film 10 has a thickness of about 50 nm, for example.

  The dummy gate electrode 9a and the gate electrode 11a are both made of, for example, a low-resistance polysilicon film, but are insulated from each other by an insulating film interposed between the dummy gate electrode 9a and the gate electrode 11a. The dummy gate electrode (made of the first conductive film) 9a is electrically connected to the gate electrode 11a. That is, in the first embodiment, by setting the dummy gate electrode 9a and the gate electrode 11a to the same potential, the insulation resistance of the insulating film interposed between the dummy gate electrode 9a and the gate electrode 11a can be increased. Can be made unaffected. Therefore, the breakdown voltage of the gate electrode 11a can be improved. That is, the breakdown voltage of the gate electrode 11a is easily affected by the insulation resistance of the insulating film interposed between the dummy gate electrode 9a and the gate electrode 11a. In the first embodiment, the dummy gate electrode sandwiching this insulating film is used. By making 9a and the gate electrode 11a have the same potential, a voltage load is not applied to the intervening insulating film, so that the breakdown voltage of the gate electrode 11a can be improved.

  The gate electrode 11a is a control electrode for the power MISFET, and a voltage for controlling the operation of the power MISFET is applied to the gate electrode 11a. The upper surface of the gate electrode 11a is slightly lower than the main surface of the semiconductor substrate 1 (the upper surface of the source region 14), and the sidewall 12 made of, for example, a silicon oxide film is formed on the upper surface of the gate electrode 11a that is recessed. Is embedded. The channel of the power MISFET is formed in the semiconductor region 13 for channel formation facing the side surface of the gate electrode 11a. That is, the channel current of the power MISFET flows in the thickness direction of the semiconductor substrate 1 orthogonal to the semiconductor substrate 1 along the side surface of the groove 6.

  In FIG. 3, the outermost (left) groove 6 has a structure that does not function as a power MISFET, and a dummy gate electrode lead portion 9 b is formed through an insulating film 7. A gate electrode lead portion 11b is formed on the dummy gate electrode lead portion 9b with a gate insulating film 10 interposed therebetween. The dummy gate electrode lead portion 9b is electrically connected to the dummy gate electrode 9a, and the gate electrode lead portion 11b is electrically connected to the gate electrode 11a.

  Further, an interlayer insulating film 16 is formed on the main surface of the semiconductor substrate 1, and a contact hole (second contact hole) 17 reaching from the interlayer insulating film 16 to the gate electrode lead portion 11b is formed. . Similarly, a contact hole 18 reaching the channel forming semiconductor region 13 from the interlayer insulating film 16 is formed. The contact hole 18 is in contact with the source region 14. Although not shown in FIG. 3, a contact hole (first contact hole) reaching the dummy gate electrode lead portion 9b without being in contact with the gate electrode lead portion 11b from the interlayer insulating film 16 is also formed. Yes.

  A gate wiring 25 is formed so as to fill the contact hole 17 reaching from the interlayer insulating film 16 to the gate electrode lead portion 11b. In other words, the gate electrode lead portion 11 b is electrically connected to the gate wiring 25. Similarly, a source electrode 24 is formed so as to fill the contact hole 18 that reaches the semiconductor region 13 for channel formation from the interlayer insulating film 16. The source electrode 24 and the gate wiring 25 are composed of a laminated film of a barrier metal film and a metal film. The barrier metal film is made of, for example, a titanium tungsten (TiW) film 22, and the metal film is made of, for example, an aluminum film 23 or an aluminum alloy film.

  The source electrode 24 is in contact with the source region 14 through the side surface of the contact hole 18 reaching the channel forming semiconductor region 13. Thereby, the source electrode 24 is electrically connected to the source region 14. A p-type semiconductor region 20 is formed at the bottom of the contact hole 18, and the source electrode 24 is electrically connected to the channel-forming semiconductor region 13 through the p-type semiconductor region 20.

  A polyimide resin film 27 is formed as a surface protective film on the main surface of the semiconductor substrate 1 on which the source electrode 24 and the gate wiring 25 are formed. Then, on the source pad that is a part of the source electrode 24, the polyimide resin film 27 is removed, and the source pad is exposed. A drain electrode 29 is formed on the back surface opposite to the main surface of the semiconductor substrate 1. The drain electrode 29 is composed of a laminated film of, for example, a titanium (Ti) film 28a, a nickel (Ni) film 28b, and a gold (Au) film 28c.

  Next, in the power MISFET in the present embodiment, the dummy gate electrode 9a is provided. The function of the dummy gate electrode 9a will be described.

  In a power MISFET in which the dummy gate electrode 9a is not provided, when a voltage is applied to the drain region with the gate electrode and the source region grounded, the electric field is strongest at the bottom of the groove where the gate electrode is formed. Therefore, the breakdown voltage (BVdss) of the power MISFET is determined by the voltage at which avalanche breakdown occurs near the bottom of the trench. Since there is only a relatively thin gate insulating film at the bottom of this groove, the electric field between the gate and the drain tends to be stronger.

  On the other hand, in the power MISFET provided with the dummy gate electrode 9a as shown in FIG. 3, the electric field at the bottom of the groove 6 of the dummy gate electrode 9a tends to be strongest, but the insulating film 7 thicker than the gate insulating film 10 Therefore, the electric field between the dummy gate electrode 9a and the drain region can be easily relaxed. Therefore, the breakdown voltage (BVdss) can be improved as compared with the power MISFET not provided with the dummy gate electrode 9a.

  Further, the provision of the dummy gate electrode 9a has the following advantages. In the power MISFET, the performance can be improved by reducing the thickness of the gate insulating film. However, in the power MISFET in which the dummy gate electrode 9a is not provided, the thickness of the gate insulating film is reduced too much. There is a problem that can not be. That is, in the power MISFET not provided with the dummy gate electrode 9a, the gate electrode is formed in the groove through the gate insulating film, but the weakly formed gate insulating film is likely to occur at the corner of the bottom of the groove. There is a spot. For this reason, the thickness of the gate insulating film cannot be reduced.

  On the other hand, in the power MISFET provided with the dummy gate electrode 9a, the dummy gate electrode 9a is formed below the inside of the groove 6 via the insulating film 7, and the gate insulating film 10 is formed above the inside of the groove 6. A gate electrode 11a is formed therethrough. Therefore, not the gate insulating film 10 but the insulating film 7 is formed at the corner of the bottom of the trench 6. Since this insulating film 7 is set to be thicker than the gate insulating film 10 in order to improve the breakdown voltage (BVdss), even if the gate insulating film 10 is thinned, the corner portion of the groove bottom does not become a weak spot. Therefore, the power MISFET provided with the dummy gate electrode 9a has an advantage that the performance can be improved by reducing the thickness of the gate insulating film.

  However, when the gate insulating film 10 is thinned, the electrostatic breakdown resistance of the gate insulating film 10 is reduced. Therefore, in the present embodiment, the power MISFET provided with the dummy gate electrode 9a and the protective diode connected to the power MISFET are formed on the same semiconductor substrate 1. As a result, the electrostatic breakdown resistance of the gate insulating film 10 can be ensured while the thickness of the gate insulating film 10 is reduced.

FIG. 4 is a cross-sectional view showing a cross section taken along line BB in FIG. In FIG. 4, on the main surface of the semiconductor substrate 1, a power MISFET provided with a dummy gate electrode 9a and a protection diode are formed. The protection diode is formed by a pn junction generated between the p ⁻ type semiconductor region 8 a and the n ⁺ type semiconductor region 15. In FIG. 4, p ⁻ type semiconductor regions 8 a and n ⁺ type semiconductor regions 15 are alternately formed between the gate wiring 25 (electrically connected to the gate electrode 11 a) and the source electrode 24. Two protective diodes are formed. By the four protection diodes, two pairs of protection diodes connected in different directions are arranged in series.

  Thus, it will be described that the gate insulating film 10 can be protected from electrostatic breakdown by electrically connecting a protective diode between the gate wiring 25 and the source electrode 24. For example, it is assumed that a surge voltage exceeding the electrostatic breakdown tolerance of the gate insulating film 10 is applied between the gate wiring 25 and the source electrode 24. At this time, when a protective diode is not provided between the gate wiring 25 and the source electrode 24, a surge voltage exceeding the electrostatic breakdown resistance is applied to the gate insulating film 10. For this reason, the gate insulating film 10 is destroyed.

  On the other hand, when a protection diode is connected between the gate line 25 and the source electrode 24, a reverse bias voltage is applied to the protection diode by a surge voltage, for example. When the reverse bias voltage due to the surge voltage exceeds the breakdown voltage, a breakdown current flows in the protection diode. At this time, a breakdown voltage is applied to the protection diode, but this breakdown voltage is constant. That is, even if a surge voltage exceeding the breakdown voltage is applied to the protection diode, the voltage applied to the protection diode is a constant breakdown voltage. Therefore, the breakdown voltage applied to the protection diode is applied to the gate insulating film 10. That is, by providing a protective diode, even if a surge voltage exceeding the dielectric breakdown resistance is applied between the gate wiring 25 and the source electrode 24 of the power MISFET, the gate insulating film 10 is only subjected to a breakdown voltage due to the protective diode. It is. It is possible to protect the gate insulating film 10 from being applied with a voltage exceeding the dielectric breakdown resistance by designing the breakdown voltage by the protection diode to be a predetermined value or less.

  In this embodiment, two pairs of protective diodes connected in different directions are provided, but the protective diodes connected in different directions are formed with different polarities. This is because the surge voltage is applied. That is, the protection diode functions even when surge voltages having different polarities are applied between the gate wiring 25 and the source electrode 24 of the power MISFET. As a configuration of a pair of protection diodes connected in different directions, for example, anode electrodes are connected to each other, and one cathode electrode is connected to the gate wiring 25. The other cathode electrode can be connected to the source electrode 24. Conversely, the cathode electrodes may be connected, one of the anode electrodes may be connected to the gate wiring 25, and the other of the anode electrodes may be connected to the source electrode 24.

  In addition, when it is only necessary to protect against a surge voltage having a specific polarity (for example, a voltage at which a positive voltage is applied to the gate wiring 25 with respect to the source electrode), a pair of protection diodes having different directions may be used. There is no need to provide it, and only one protective diode may be provided. At this time, the cathode electrode of the protective diode can be connected to the gate wiring 25 and the anode electrode can be connected to the source electrode 24. Conversely, the cathode electrode may be connected to the source electrode 24, and the anode electrode may be connected to the gate wiring 25.

  In this embodiment, two pairs of protective diodes connected in different directions are formed, but this is only an example, and the voltage at which the protective diode operates is adjusted to a predetermined value. It was formed from the viewpoint. Therefore, only one pair of protective diodes may be used, or for example, three or more pairs of protective diodes may be provided.

  Next, an example of a circuit configured using the power MISFET in this embodiment will be described. FIG. 5 shows an example of a motor control circuit configured using the power MISFET in the present embodiment. This motor control circuit is used, for example, as a circuit for controlling a motor of a power window device mounted on an automobile.

  In FIG. 5, the motor control circuit includes a gate drive circuit 30, a motor 31, power MISFETs 32-35, a DC power supply 36, and protective diodes 37-40. In this motor control circuit, the gate electrodes of the power MISFETs 32 to 35 are connected to the gate drive circuit 30, and the drain electrodes of the power MISFETs 32 and 34 are connected in parallel to the positive electrode of the DC power supply 36. The source electrode of the power MISFET 32 is connected to the drain electrode of the power MISFET 33, and the source electrode of the power MISFET 34 is connected to the drain electrode of the power MISFET 35. Further, the negative electrode of the DC power source 36 is connected to the source electrode of the power MISFET 33 and the source electrode of the power MISFET 35. The motor 31 is connected between a connection portion between the power MISFET 32 and the power MISFET 33 and a connection portion between the power MISFET 34 and the power MISFET 35. Further, protection diodes 37 to 40 are electrically connected between the gate electrodes and the source electrodes of the individual power MISFETs 32 to 35, respectively. As described above, in the motor control circuit shown in FIG. 5, a pair of protection diodes having different directions (back to back) are connected in two stages between the gate electrodes and the source electrodes of the power MISFETs 32 to 35 (protection diode 37). ~ 40). The motor control circuit is configured so that the power MISFETs 32 to 35 become an H bridge (full bridge) with respect to the motor 31.

  The gate drive circuit 30 is configured so that a predetermined voltage can be applied to the gate electrodes of the power MISFETs 32 to 35, and the power MISFETs 32 to 35 can be controlled on / off. The power MISFETs 32 to 35 are power MISFETs having a trench gate structure provided with the dummy gate electrodes described with reference to FIGS. 2 to 4, and are high-performance power MISFETs having a thin gate insulating film. The protection diodes 37 to 40 are formed on the same semiconductor substrate as the power MISFETs 32 to 35.

  The operation of the motor control circuit in the present embodiment will be described below. First, by the gate drive circuit 30, the power MISFET 33 and the power MISFET 34 are turned on, while the power MISFET 32 and the power MISFET 35 are turned off. Then, the positive electrode of the DC power supply 36 is connected to the terminal 31 a of the motor 31 via the power MISFET 34. On the other hand, the negative electrode of the DC power source 36 is connected to the terminal 31 b of the motor 31 through the power MISFET 33. Thereby, the motor 31 rotates in a predetermined direction. Next, the power MISFET 32 and the power MISFET 35 are turned on by the gate drive circuit 30, and the power MISFET 33 and the power MISFET 34 are turned off. Then, the positive electrode of the DC power source 36 is connected to the terminal 31 b of the motor 31 via the power MISFET 32. On the other hand, the negative electrode of the DC power source 36 is connected to the terminal 31 a of the motor 31 via the power MISFET 35. As a result, the motor 31 is reversely connected to the previous connection state, and thus rotates in the reverse direction. Thus, according to the motor control circuit in the present embodiment, the rotation direction of the motor 31 can be controlled.

  Here, for example, it is assumed that a surge voltage higher than the breakdown voltage of the protection diode 37 is applied between the gate electrode and the source electrode of the power MISFET 32. At this time, a protection diode 37 is connected between the gate electrode and the source electrode of the power MISFET 32. Since the surge voltage is higher than the breakdown voltage of the protection diode 37, a reverse current flows through the protection diode 37. When a reverse current flows through the protection diode 37, the voltage applied to both ends of the protection diode 37 is a constant breakdown voltage. Therefore, a breakdown voltage lower than the surge voltage is applied to the gate insulating film of the power MISFET 32. Thus, even when a surge voltage that causes breakdown of the gate insulating film is applied, a breakdown voltage that does not cause breakdown is applied to the gate insulating film by the protection function of the protective diode 37. . In this way, destruction of the power MISFET 32 can be prevented.

  Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to the drawings. In the semiconductor device according to the present embodiment, a power MISFET having a trench gate configuration including a dummy gate electrode and a protection diode are formed on the same semiconductor substrate. When manufacturing such a semiconductor device, it is necessary to form a polysilicon film for a dummy gate electrode, a polysilicon film for a gate electrode, and a polysilicon film for a protective diode in separate steps, considering a normal method. At the same time, it is necessary to process each polysilicon film separately. For this reason, when a protective diode is also mounted, there arises a problem that the processing steps are very complicated and the number of steps is increased as compared with the case where only a power MISFET having a trench gate configuration including a dummy gate electrode is formed.

  Therefore, in this embodiment, the manufacturing process can be simplified by adopting a semiconductor device manufacturing method as described below.

  In the cross-sectional views described below, the left region indicates a power MISFET formation region, and the right region indicates a protection diode formation region.

First, as shown in FIG. 6, an n-type epitaxial layer 2 made of a high-resistance n-type silicon single crystal is formed on a semiconductor substrate 1 made of a low-resistance n ⁺ -type silicon (Si) single crystal. prepare. Subsequently, a p-type well 3 is formed in the n-type epitaxial layer 2 by using a photolithography technique and an ion implantation method. The p-type well 3 is formed by introducing a p-type impurity such as boron (B) by ion implantation. This p-type well 3 is formed in order to make a pn junction having a high breakdown voltage. Then, the element isolation region 4 is formed using, for example, a selective oxidation method (LOCOS method). The element isolation region 4 is formed from, for example, a silicon oxide film. In the protection diode formation region, the p-type well 3 is covered with the element isolation region 4.

Subsequently, an insulating film 5 made of, for example, a silicon oxide film is formed on the main surface of the semiconductor substrate 1. Although a silicon oxide film is used here, another material such as a silicon nitride film (Si ₃ N ₄ ) may be used. Thereafter, a resist pattern is formed on the insulating film 5 through a series of photolithography techniques such as application of a photoresist film (hereinafter simply referred to as a resist film), exposure, and development. Then, using this resist pattern as an etching mask, the insulating film 5 is etched, and the resist pattern is removed to pattern the groove forming insulating film 5. The pattern of the insulating film 5 functions as a hard mask film for forming a groove. In the protection diode formation region, the insulating film 5 covers the element isolation region 4.

  Next, as shown in FIG. 7, the semiconductor substrate 1 is etched by anisotropic dry etching using the pattern of the insulating film 5 as an etching mask to form a groove 6. The groove 6 is formed in the power MISFET formation region, but is not formed in the protection diode formation region.

  FIG. 8 shows a plan view of the semiconductor substrate 1 on which the steps so far are performed. FIG. 8 shows the chip region CR of the semiconductor substrate 1. In FIG. 8, a region surrounded by the element isolation region 4 is an active region, and a groove 6 is formed in this active region. 8 shows the power MISFET formation region in the cross-sectional view (FIG. 6 and the like), and the DD cross-section shows the protection diode formation region in the cross-sectional view.

  Subsequently, as shown in FIG. 9, by subjecting the semiconductor substrate 1 to thermal oxidation, an insulating film (for example, a silicon oxide film) is formed on the main surface of the semiconductor substrate 1 (including the inner surface of the groove 6). Insulating film) (first insulating film) 7 is formed. The thickness of this insulating film 7 is, for example, about 200 nm.

  Then, a polysilicon film (first polysilicon film) 8 is formed on the main surface of the semiconductor substrate 1. The polysilicon film 8 is an intrinsic polysilicon film into which no conductive impurities are introduced, and is formed by, for example, a CVD (Chemical Vapor Deposition) method. The polysilicon film 8 is formed in the power MISFET formation region and the protection diode formation region. As will be described later, the polysilicon film 8 becomes a dummy gate electrode polysilicon film (first conductive film) and a protective diode polysilicon film (second conductive film). That is, in the first embodiment, the polysilicon film for the dummy gate electrode and the polysilicon film for the protective diode are formed simultaneously by the polysilicon film 8. Therefore, there is an advantage that the process can be simplified as compared with the case where the polysilicon film for the dummy gate electrode and the polysilicon film for the protective diode are formed in separate processes.

Next, as shown in FIG. 10, a p ^- type semiconductor region is formed by introducing a p-type impurity such as boron (B) into the polysilicon film 8 formed on the semiconductor substrate 1 using an ion implantation method. 8a is formed. Thereafter, as shown in FIG. 11, by using a photolithography technique and an ion implantation method, a high concentration n-type impurity is introduced into the p ⁻ -type semiconductor region 8a of the power MISFET formation region, thereby forming an n ⁺ -type semiconductor region. 8b is formed. Examples of the n-type impurity include phosphorus (P), arsenic (As), and antimony (Sb). Subsequently, the semiconductor substrate 1 is subjected to a heat treatment (annealing process) at 1100 ° C. or higher, for example. This heat treatment is performed to increase the grain size (crystal grains) of the polysilicon film 8 constituting the p ⁻ type semiconductor region 8a and the n ⁺ type semiconductor region 8b. As will be described later, the p ⁻ type semiconductor region 8a becomes a part of the protection diode, but the leakage current of the protection diode can be reduced by increasing the grain size of the p ⁻ type semiconductor region 8a. This is presumably because the grain size increases due to high-temperature heat treatment, and the grain boundaries (crystal grain boundaries) crossing the pn junction of the protective diode decrease. That is, since the grain boundary that becomes the path of the leakage current is reduced, the leakage current of the protective diode can be reduced. This high-temperature heat treatment is desirably performed before forming a semiconductor region for forming a channel, which will be described later. If this high-temperature heat treatment is performed after the formation of the semiconductor region for forming the channel, the semiconductor region for forming the channel diffuses, making it impossible to realize a shallow junction of the channel, which is disadvantageous for improving the performance of the power MISFET. Because it will end up.

Next, as shown in FIG. 12, the polysilicon film 8 constituting the n ⁺ type semiconductor region 8b is patterned by using a photolithography technique and an etching technique. As a result, the polysilicon film 8 formed in the trench 6 is etched to an intermediate depth to form a dummy gate electrode 9 a in the trench 6. Further, a dummy gate electrode lead portion 9b is formed on the semiconductor substrate 1 by patterning. The dummy gate electrode lead portion 9b is formed so as to be electrically connected to the dummy gate electrode 9a. Here, the grain size of the polysilicon film 8 constituting the n ⁺ type semiconductor region 8b is increased by the heat treatment described above. For this reason, the effect which can prevent the shape defect of the dummy gate electrode 9a is also acquired.

Next, as shown in FIG. 13, the insulating film 7 is patterned using a photolithography technique and an etching technique. FIG. 14 is a plan view of the chip region CR in which the steps up to here are performed. In FIG. 14, it can be seen that ap ⁻ type semiconductor region (anode region) 8a is formed in the protective diode formation region, and a dummy gate electrode lead portion 9b is formed on the outer periphery of the power MISFET formation region.

  Subsequently, as shown in FIG. 15, a gate insulating film 10 is formed on the main surface of the semiconductor substrate 1 including the side surfaces of the trench 6. The gate insulating film 10 is made of, for example, a silicon oxide film formed by thermal oxidation, and is formed to be thinner than the insulating film 7. This is necessary for improving the current driving capability of the power MISFET and lowering the on-resistance. The thickness of the gate insulating film 10 is, for example, about 50 nm.

  Then, a polysilicon film (second polysilicon film) is formed on the semiconductor substrate 1 including the gate insulating film 10. This polysilicon film is formed by using, for example, a CVD method, and an n-type impurity is added. That is, when forming this polysilicon film, for example, an n-type impurity such as phosphorus or arsenic is introduced into the polysilicon film. Thereafter, the gate electrode 11a is formed in the trench 6 by patterning the polysilicon film using a photolithography technique and an etching technique. The gate electrode 11 a has a recess structure in which the upper surface is recessed from the main surface of the semiconductor substrate 1. Further, the gate electrode lead portion 11b is formed by patterning the polysilicon film. The gate electrode lead portion 11b is electrically connected to the gate electrode 11a.

  The impurity concentration of the n-type impurity introduced into the gate electrode 11a is higher than the impurity concentration of the n-type impurity introduced into the dummy gate electrode 9a. In other words, the resistivity of the gate electrode 11a is lower than the resistivity of the dummy gate electrode 9a. This is because when the resistance value of the gate electrode 11a is high, the power MISFETs connected in parallel are difficult to operate uniformly. In other words, if the power MISFET does not operate uniformly, the electrostatic breakdown resistance of the gate insulating film and the avalanche resistance (when the power MOS is turned off with the inductive load connected, the sum of the power supply voltage and the induced electromotive force is instantaneously generated. When the voltage exceeds the withstand voltage, the avalanche breakdown state occurs, and the product of the maximum value of the avalanche current that can flow without destruction and the time (avalanche energy) is applied between the source region and the drain region. ))) And a switching speed becomes slow. In order to prevent such a problem, it is necessary to lower the resistance value of the gate electrode 11a. Therefore, a polysilicon film to which an impurity such as phosphorus or arsenic is added in advance at the time of formation is used for forming the gate electrode 11a. According to the polysilicon film to which impurities are added in advance, the resistance of the polysilicon film can be reduced as compared with the polysilicon film formed without adding impurities at the time of formation and then introduced with impurities by an ion implantation method. . For example, according to a polysilicon film having a thickness of 500 nm to which impurities are added in advance, the sheet resistance can be reduced to about 10 Ω / □. On the other hand, according to the polysilicon film having a thickness of 500 nm into which impurities are introduced by the ion implantation method, the sheet resistance can be reduced only to about 20Ω / □. Therefore, a polysilicon film to which impurities are added in advance is used for forming the gate electrode 11a.

  On the other hand, since the dummy gate electrode 9a is not the gate electrode 11a of the power MISFET, even if the resistivity is higher than that of the gate electrode 11a, the power MISFET connected in parallel does not become difficult to operate uniformly. Further, since the dummy gate electrode 9a has a structure covered with the insulating film 7 thicker than the gate insulating film 10, even if the resistance value is higher than that of the gate electrode 11a, it is easy to ensure the electrostatic breakdown resistance. Therefore, the dummy gate electrode 9a can be formed of a polysilicon film in which an intrinsic polysilicon film to which no impurity is added is formed, and then an impurity is introduced into the intrinsic polysilicon film using an ion implantation method. Here, the dummy gate electrode 9a can also be formed of a polysilicon film to which impurities are added in advance. However, in this embodiment, since the polysilicon film for the protective diode is simultaneously formed with the polysilicon film for the dummy gate electrode 9a, a polysilicon film to which impurities have been added in advance is used for forming the dummy gate electrode 9a. It is not possible. That is, since a high-concentration impurity is introduced into the polysilicon film to which impurities have been added in advance, it cannot be used for forming a protective diode. Therefore, the polysilicon film of the protective diode cannot be formed simultaneously with the formation of the gate electrode 11a using the polysilicon film to which impurities have been added in advance. On the other hand, since the intrinsic polysilicon film can be used to form the dummy gate electrode 9a, the polysilicon film of the protective diode can be formed at the same time. For this reason, in this embodiment, the polysilicon film for the dummy gate electrode 9a and the polysilicon film for the protection diode are formed simultaneously.

  Next, an insulating film (not shown) made of, for example, a silicon oxide film is formed on the semiconductor substrate 1 and then anisotropically etched to form a sidewall 12 as shown in FIG. Form. The sidewall 12 is formed to protect the corner portion at the top of the groove 6. Note that the sidewall 12 may not be formed.

FIG. 17 shows a plan view of the chip region CR in which the steps so far are performed. In FIG. 17, a p ⁻ type semiconductor region 8a is formed in the protection diode formation region, and a dummy gate electrode lead portion 9b is formed on the outer periphery of the power MISFET formation region. It can be seen that the gate electrode lead portion 11b is formed on the dummy gate electrode lead portion 9b.

  Next, a resist pattern in which the channel formation region is exposed on the main surface of the semiconductor substrate 1 is formed by photolithography. Then, using the formed resist pattern as a mask, a p-type impurity such as boron is introduced into the main surface of the semiconductor substrate 1 by an ion implantation method. Subsequently, after removing the resist pattern, a semiconductor region 13 for channel formation as shown in FIG. 18 is formed by subjecting the semiconductor substrate 1 to thermal diffusion treatment.

Next, a resist pattern in which the source formation region and the cathode formation region of the protective diode are exposed is formed on the main surface of the semiconductor substrate 1 by a photolithography technique. Then, using the formed resist pattern as a mask, an n-type impurity such as phosphorus or arsenic is introduced into the main surface of the semiconductor substrate 1 by ion implantation. Subsequently, after the formed resist pattern is removed, the semiconductor substrate 1 is subjected to a thermal diffusion process, so that the source region 14 and the n ⁺ type semiconductor region (cathode region) 15 of the protective diode as shown in FIG. Form. Thus, in this embodiment, the source region 14 of the power MISFET and the n ⁺ type semiconductor region 15 of the protection diode can be formed at the same time, so that the process can be simplified.

FIG. 20 shows a plan view of the chip region CR in which the steps so far are performed. In FIG. 20, a p ⁻ type semiconductor region 8a and an n ⁺ type semiconductor region 15 are formed in the protection diode formation region, and a protection diode with a pn junction is formed. On the other hand, it can be seen that the source region 14 is formed in the power MISFET formation region.

  Here, another reason for not forming the polysilicon film for the gate electrode 11a and the polysilicon film for the protection diode at the same time, but forming the polysilicon film for the dummy gate electrode 9a and the polysilicon film for the protection diode at the same time. Will be described.

  As shown in FIG. 19, the dummy gate electrode 9a fills a narrow groove sandwiched by the thick insulating film 7, whereas the gate electrode 11a of the power MISFET has a wide groove sandwiched by the thin gate insulating film 10. Need to be filled. That is, the dummy gate electrode 9 a and the gate electrode 11 a are formed in the same groove 6, but a thick insulating film 7 is formed between the dummy gate electrode 9 a and the groove 6. Therefore, the region where the dummy gate electrode 9a is filled becomes narrower as the thick insulating film 7 is formed. On the other hand, since the thin gate insulating film 10 is formed between the gate electrode 11a and the trench 6, the region filled with the gate electrode 11a is wider than the region filled with the dummy gate electrode 9a. Thus, the trench 6 can be filled even if the polysilicon film forming the dummy gate electrode 9a is thinner than the polysilicon film forming the gate electrode 11a. That is, the film thickness of the dummy gate electrode lead portion 9b is smaller than the film thickness of the gate electrode lead portion 11b.

  Specifically, when the width of the trench 6 is 0.8 μm, the thickness of the insulating film 7 is 200 nm, and the thickness of the gate insulating film 10 is 50 nm, the dummy gate electrode 9a fills the trench region having a width of 0.4 μm. As long as it is possible, at least a polysilicon film for the dummy gate electrode 9a may be deposited by 200 nm or more. On the other hand, since the gate electrode 11a needs to be filled in a trench region having a width of 0.7 μm, it is necessary to deposit a polysilicon film for the gate electrode 11a at 350 nm or more.

In the case where an n ⁺ p ⁻ junction protective diode is formed, the p ⁻ type semiconductor region 8a is formed by forming boron on the entire surface of the intrinsic polysilicon film and then forming boron on the entire surface of the intrinsic polysilicon film at 1 × 10 ¹³ / cm ² to 1 ×. It is formed by ion implantation with a dose of about 10 ¹⁴ / cm ² . On the other hand, it is necessary to selectively form the n ⁺ type semiconductor region 15. At the same time as the ion implantation step (a step of introducing about 1 × 10 ¹⁵ / cm ² to 1 × 10 ¹⁶ / cm ^{2 of} arsenic) for selectively forming the source region of the power MISFET, the n ⁺ type semiconductor region 15 of the protective diode is also formed. If formed, the protective diode can be formed without increasing the number of steps.

Here, the problem is the junction depth of the source region. In order to improve the performance of the power MISFET, it is important to make the source region and the channel region shallow junctions. When the source region is shallowly joined, the n ⁺ type semiconductor region 15 of the protection diode that is simultaneously formed also becomes a shallow junction. For this reason, when the n ⁺ type semiconductor region 15 of the protective diode is formed in the thick polysilicon film, the n ⁺ type semiconductor region 15 is difficult to reach the bottom surface of the polysilicon film. If the n ⁺ type semiconductor region 15 does not sufficiently reach the bottom surface of the polysilicon film, a large leakage current flows in the bidirectional diode such as n ⁺ p ⁻ n ⁺ p ⁻ n ⁺ . If the n ⁺ type semiconductor region 15 is formed in a thin polysilicon film, the bottom surface of the polysilicon film can be easily reached even if the n ⁺ type semiconductor region 15 is shallow, so that a protection diode with a small leakage current can be formed. Is possible.

Thus, even if the film thickness is small, the formation of the polysilicon film of the protective diode with the polysilicon film for the dummy gate electrode that can be filled in the groove 6 is more effective in the process of forming the source region of the power MISFET. It is easy to form the n ⁺ type semiconductor region 15 of the diode at the same time, which is advantageous for reducing the number of processes. In particular, the effect is large when it is desired to improve the performance of the power MISFET by shallowly forming the source region.

Next, as shown in FIG. 21, after forming an interlayer insulating film 16 made of, for example, a silicon oxide film on the main surface of the semiconductor substrate 1, a resist pattern in which a contact hole forming region is exposed on the interlayer insulating film 16. Are formed by photolithography. Subsequently, the interlayer insulating film 16 is etched using the formed resist pattern as an etching mask, and then the resist pattern is removed, thereby forming contact holes 17, 18, and 19 in the interlayer insulating film 16. The contact hole 17 reaches the gate electrode lead portion 11 b, and the contact hole 18 reaches the channel forming semiconductor region 13 formed in the main surface of the semiconductor substrate 1. Further, the contact hole 19 is formed in the protection diode formation region and reaches the n ⁺ type semiconductor region 15 which becomes the cathode region of the protection diode.

  Next, a groove is formed by etching a part of the semiconductor region 13 for channel formation exposed at the bottom surface of the contact hole 18. Thereafter, a p-type semiconductor region 20 is formed at the bottom of the trench by introducing a p-type impurity such as boron by ion implantation.

FIG. 22 shows a plan view of the chip region CR in which the steps so far are performed. In FIG. 22, a contact hole 17 is formed in the gate electrode lead portion 11b, and a contact hole 18 is formed in the active region. A contact hole 19 is formed in the n ⁺ type semiconductor region 15 of the protective diode region, and a contact hole 21 is formed in the dummy gate electrode lead portion 9b.

  Subsequently, after forming a titanium tungsten (TiW) film 22 serving as a barrier metal film on the main surface of the semiconductor substrate 1, an aluminum film 23 is further formed on the titanium tungsten film 22 by using, for example, a sputtering method. Form. Then, the titanium tungsten film 22 and the aluminum film 23 are patterned by using a photolithography technique and an etching technique. By this patterning, a source electrode 24, a gate wiring 25, and an electrode 26 made of a titanium tungsten film 22 and an aluminum film 23 are formed.

The source electrode 24 is formed so as to fill the contact hole 18 and is formed so as to be connected to the source region 14 and the p-type semiconductor region 20. The gate wiring 25 is connected to the gate electrode lead portion 11 b through the contact hole 17. Since the gate electrode lead portion 11b is connected to the gate electrode 11a, the gate wiring 25 is electrically connected to the gate electrode 11a. An electrode 26 is formed in the protection diode formation region, and this electrode 26 is connected to the n ⁺ type semiconductor region 15 through the contact hole 19. One of the electrodes 26 is connected to the source electrode 24, and the other of the electrodes 26 is connected to the gate wiring 25. By connecting the electrode 26 in this way, a protective diode is connected between the source electrode 24 and the gate wiring 25.

  Next, after forming a polyimide resin film (not shown) serving as a surface protective film on the main surface of the semiconductor substrate 1, the polyimide resin film is patterned using a photolithography technique. The patterning is performed so as to expose a part of the source electrode 24 and a part of the gate wiring 25 to form a source pad and a gate pad.

  Then, after grinding the back surface of the semiconductor substrate 1, a titanium film (not shown), a nickel film (not shown), and a gold film (not shown) are formed on the entire back surface of the semiconductor substrate 1 using, for example, a sputtering method. ) Is formed. Thereby, a drain electrode made of a laminated film of a titanium film, a nickel film and a gold film is formed.

  In this manner, the semiconductor device in this embodiment can be formed. According to the present embodiment, since the power MISFET having a trench gate configuration including the dummy gate electrode and the protection diode are formed on the same semiconductor substrate, electrostatic breakdown of the gate insulating film is prevented while improving the performance of the MISFET. Can be prevented.

  The protective diode polysilicon film constituting the protection diode and the dummy electrode polysilicon film constituting the dummy gate electrode are formed in the same process. In addition, the cathode of the protective diode and the source region of the power MISFET having a trench gate configuration including a dummy gate electrode are formed in the same process. As a result, it is possible to easily form a power MISFET and a protection diode having a trench gate configuration including a dummy gate electrode while suppressing the complexity of the processing process.

  Next, FIG. 24 illustrates an example of a layout configuration of the semiconductor device in this embodiment. FIG. 24 is a diagram showing a layout configuration in which a dummy gate electrode and a gate electrode are electrically connected. In FIG. 24, contact holes (second contact holes) 17 connected to the gate electrode lead portions and contact holes (first contact holes) 21 connected to the dummy gate electrode lead portions are arranged in a straight line. ing. A straight gate wiring 25 is formed on the contact hole 17 and the contact hole 21 arranged in a straight line. With this configuration, the dummy gate electrode and the gate electrode can be connected at the same potential. Furthermore, by arranging the contact holes 17 and 21 in a straight line, the effective area of the semiconductor chip CP (area of the cell formation region / area of the entire chip) can be increased. In FIG. 24, a part of the gate wiring 25 is omitted so that the contact hole 17 and the contact hole 21 existing below the gate wiring 25 can be seen.

  In FIG. 24, the contact holes 17 and the contact holes 21 are alternately formed, but it is not always necessary to arrange them alternately. For example, when it is desired to reduce the resistance of the gate electrode, it is desirable to increase the ratio of the contact hole 17.

FIG. 25 is a diagram showing a layout configuration in which the dummy gate electrode is connected to the source electrode 24 and the gate electrode is connected to the gate wiring 25. By connecting the dummy gate electrode to the source electrode 24, the parasitic capacitance (feedback capacitance) between the gate electrode and the drain region can be reduced, and there is an advantage that high-speed switching can be realized. That is, although parasitic capacitance is generated between the gate electrode and the drain region, a shielding effect can be obtained by connecting the dummy gate electrode formed between the gate electrode and the drain region to the source potential. Parasitic capacitance can be reduced by this shielding effect.

  In FIG. 25, the contact hole 17 connected to the gate electrode lead portion and the contact hole 21 connected to the dummy gate electrode lead portion are arranged in a straight line. The contact hole 17 is connected to the gate wiring 25, and the contact hole 21 is connected to the source electrode 24. A portion where the gate wiring 25 is connected to the contact hole 17 is a convex portion 40a. A concave portion 40b is formed in the portion of the source electrode 24 facing the convex portion 40a. That is, the gate wiring 25 formed on the contact hole 17 is formed in a convex shape at a location where the source electrode 24 formed on the contact hole 21 has a concave shape. On the other hand, a portion where the source electrode 24 is connected to the contact hole 21 is a convex portion 41a. A concave portion 41b is formed in the portion of the gate wiring 25 facing the convex portion 41a. That is, the gate wiring 25 is formed in a concave shape at a location where the source electrode 24 has a convex shape. With such a layout configuration, the effective area of the semiconductor chip CP can be increased. In FIG. 25, a part of the source electrode 24 and the gate wiring 25 is omitted so that the contact hole 17 and the contact hole 21 existing below the gate wiring 25 can be seen.

  In FIG. 25, the contact holes 17 and the contact holes 21 are alternately formed, but it is not always necessary to arrange them alternately. For example, when it is desired to reduce the resistance of the gate electrode, it is desirable to increase the ratio of the contact hole 17.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be widely used in the manufacturing industry of a semiconductor device having a power MISFET having a trench gate configuration.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 N type epitaxial layer 3 P type well 4 Element isolation region 5 Insulating film 6 Groove 7 Insulating film 8 Polysilicon film 8a p ⁻ type semiconductor region 8b n ⁺ type semiconductor region 9a Dummy gate electrode 9b Dummy gate electrode lead Part 10 Gate insulating film 11a Gate electrode 11b Lead part for gate electrode 12 Side wall 13 Semiconductor region 14 Source region 15 n ⁺ type semiconductor region 16 Interlayer insulating film 17 Contact hole 18 Contact hole 19 Contact hole 20 P-type semiconductor region 21 Contact hole 22 Titanium tungsten film 23 Aluminum film 24 Source electrode 25 Gate wiring 26 Electrode 27 Polyimide resin film 28a Titanium film 28b Nickel film 28c Gold film 29 Drain electrode 30 Gate drive circuit 31 Motor 32-35 Power M SFET
36 DC power supply 37-40 Protection diode 40a Convex part 40b Concave part 41a Convex part 41b Concave part 101 Power MISFET
102 Horizontal MISFET
103 Protection diode CP Semiconductor chip CR Chip area GP Gate pad SP Source pad

Claims (9)

A method of manufacturing a semiconductor device having a MISFET including a gate electrode formed in a groove of a semiconductor substrate,
(A) forming the groove in the semiconductor substrate;
(B) after the step (a), forming a first insulating film on the inner wall of the groove;
(C) after the step (b), a step of forming a first conductive film on the semiconductor substrate so as to fill the trench through the first insulating film;
(D) a step of selectively forming a first resist pattern on the first conductive film after the step (c);
(E) After the step (d), the first conductive film is etched using the first resist pattern as a mask, so that a part of the first conductive film is left in the trench, and the dummy gate electrode Forming a protective diode by patterning the first conductive film outside the groove,
(F) After the step (e), in a state where the first insulating film and the dummy gate electrode are formed below the groove, the gate insulating film of the MISFET is formed on the inner wall of the groove above the groove. Forming a process,
(G) after the step (f), a step of forming a second conductive film on the semiconductor substrate so as to fill the trench through the gate insulating film;
(H) after the step (g), a step of selectively forming a second resist pattern on the second conductive film;
(I) After the step (h), the second conductive film is etched using the second resist pattern as a mask, so that a part of the second conductive film is left in the groove and the MISFET is formed. Forming the gate electrode;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
In the step (e), by patterning the first conductive film outside the groove, a first gate lead portion integrated with the dummy gate electrode is also formed. Production method. In the manufacturing method of the semiconductor device according to claim 1 or 2,
In the step (i), by patterning the second conductive film outside the trench, a second gate lead portion integrated with the gate electrode of the MISFET is also formed. Device manufacturing method. In the manufacturing method of the semiconductor device of any one of Claims 1-3,
The method of manufacturing a semiconductor device, wherein an impurity concentration contained in the dummy gate electrode is lower than an impurity concentration contained in the gate electrode of the MISFET. In the manufacturing method of the semiconductor device given in any 1 paragraph of Claims 1-4,
The method of manufacturing a semiconductor device, wherein the film thickness of the first insulating film is larger than the film thickness of the gate insulating film of the MISFET. In the manufacturing method of the semiconductor device of any one of Claims 1-5,
The thickness of the first conductive film formed in the step (c) is smaller than the thickness of the second conductive film formed in the step (g). Manufacturing method. The method for manufacturing a semiconductor device according to claim 6 further comprises:
(J) forming a source region of the MISFET in the semiconductor substrate adjacent to the trench by selectively implanting ions into the semiconductor substrate;
Have
In the step (j), the ion implantation is also selectively performed on the protection diode. In the manufacturing method of the semiconductor device of any one of Claims 1-7,
The method of manufacturing a semiconductor device, wherein the first conductive film and the second conductive film are made of a polysilicon film. The method for manufacturing a semiconductor device according to any one of claims 1 to 8, further comprising:
(K) forming an element isolation region made of a second insulating film on the semiconductor substrate;
Have
The method of manufacturing a semiconductor device, wherein the protection diode is formed on the element isolation region.