KR20070052931A - Electrostatic discharge protection device for semiconductor integrated circuit - Google Patents

Abstract

The present invention discloses an electrostatic discharge protection device for a semiconductor integrated circuit, which makes it possible to more effectively protect an internal circuit from damage caused by electrostatic discharge. An electrostatic discharge protection device for a semiconductor integrated circuit according to the present invention includes a semiconductor substrate doped with a first conductive impurity, a gate of a second conductive type formed on the substrate and connected to ground, and a substrate surface on one side of the gate. A source of a first conductivity type formed in the substrate and connected to the ground, a drain of the first conductivity type formed in the substrate surface on the other side of the gate and connected to a pad, and formed in a substrate below the gate and one side of the drain adjacent thereto; A second conductive region comprising a first region of a second conductive type and a second region of a second conductive type formed in a substrate under the remaining drain portion while being in contact with the first region and having a greater doping concentration than the first region; And the drain, the second region, and the substrate region below the second region operate as a bipolar junction transistor.

Description

Electrostatic discharge protection device for semiconductor integrated circuits

1, 2A and 2B are diagrams for explaining an electrostatic discharge protection device for a semiconductor integrated circuit made of a conventional GGNMOS.

3 is a cross-sectional view illustrating an electrostatic discharge protection device for a semiconductor integrated circuit made of GGNMOS according to an embodiment of the present invention.

4 is a graph illustrating the characteristics of the electrostatic discharge protection device for a semiconductor integrated circuit according to the prior art and the present invention.

Explanation of symbols on the main parts of the drawings

300: semiconductor substrate 310: gate

320: N-type source 330: N-type drain

340: P type doping region 340a: P type first region

340b: P-type second region 400: pad

The present invention relates to an electrostatic discharge protection device for a semiconductor integrated circuit, and more particularly, to an electrostatic discharge protection device for a semiconductor integrated circuit that can more effectively protect the internal circuit from damage caused by electrostatic discharge.

Semiconductor integrated circuits are very sensitive to Electrostatic Discharge (ESD) pulses, and are also susceptible to physical damage by the high voltages and currents produced by ESD events.

In particular, as the size of semiconductor integrated circuits decreases and the size of ESD protection devices decreases, the size of secondary breakdown voltages also decreases, and in recent years, the operating speed of semiconductor integrated circuits has increased. Therefore, the ESD protection device must be designed to effectively protect the semiconductor integrated circuit from the damage of the ESD within a range that does not affect the operating speed of the semiconductor integrated circuit.

Hereinafter, a gate grounded NMOS (GGNMOS), which is one of the conventional ESD protection devices, will be briefly described with reference to FIGS. 1, 2A, and 2B.

Referring to FIG. 1, in the conventional ESD protection device made of GGNMOS, the drain 130 formed in the surface of the semiconductor substrate 100 is connected to the pad 200, and the gate 110 and the source 120 are grounded (VSS). ) Although not shown, a pick-up may be further formed on the outside of the device isolation layer in contact with the source 120. Here, the semiconductor substrate 100 is a substrate doped with P-type impurities, and the source 120 and drain 130 are N + regions doped with N-type impurities.

In the conventional ESD protection device made of GGNMOS, when an ESD event occurs in the pad 200, charges are collected in the drain 130 until the GGNMOS is turned on. . However, when the amount of charges collected in the drain 130 is greater than or equal to a certain amount, as shown in FIG. 2A, a strong electric field is applied to the depletion region of the drain 130. Is pulled toward the drain 130 and an avalanche breakdown occurs between the drain 130 and the substrate 100 by impact ionization.

When the avalanche breakdown occurs, the resistance of the substrate 100 is changed as a hole flows from the drain 130 to the substrate 100, and thus, the drain 130, the substrate 100, and A parasitic bipolar junction transistor (BJT) is operated between the sources 120 to move electrons from the source 120 to the drain 130. This is referred to as GGNMOS triggering (triggering), the voltage applied to the drain 130 when the triggering occurs is called the triggering voltage (Vt1).

When the parasitic BJT is turned on in the GGNMOS, in response to the flow of electrons flowing from the source 120 to the drain 130, the ESD current flows from the drain 130 to the ground VSS through the source 120. This protects the internal circuits from ESD currents coming from the pads. FIG. 2B is a schematic circuit diagram of a protection device including a GGNMOS, wherein the GGNMOS protection device is located between the pad and the internal circuit, and as described above, bypasses the ESD current flowing from the pad to ground to internally. It protects the circuit.

However, the ESD protection device made of the above-described conventional GGNMOS has a sidewall portion of the drain 130 adjacent to the gate 110 because the parasitic BJT has a horizontal direction with the substrate surface when the parasitic BJT is turned on. Most of the current flows through it. In this case, the sidewall portion of the drain 130 has a relatively narrow area compared to the bottom surface of the drain 130 and is curved to increase the local current concentration effect. In addition, heat generated by the current concentration is not properly discharged through the surface portion of the drain 130, so that the temperature of the surface portion of the drain 130 adjacent to the gate 110 (region A in FIG. 2A) increases. Accordingly, the surface portion of the drain 130 is deteriorated and the GGNMOS does not function properly as a protection device, causing damage to the device. The reason why heat dissipation is not properly performed through the surface portion of the drain 130 is that an interlayer insulating film of an oxide film formed on the substrate 100 to cover the drain 130 and the gate 110 is a substrate material such as silicon. This is because the thermal conductivity is relatively low.

In addition, in the operation of the ESD protection device made of GGNMOS described above, in order to effectively protect the internal circuit from ESD, it is necessary to turn on the parasitic BJT quickly. On the other hand, the conventional ESD protection device made of GGNMOS includes a lower gate 110. Since the substrate 100 region is used as the main path of the current flow, there is a limit in increasing the concentration of P-type impurities in the substrate region, which is the main path of the current flow, and thus, there is a difficulty in lowering the triggering voltage. Is difficult to turn on quickly, so there is a limit to protecting the internal circuits from ESD.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, it is possible to improve the problem of deterioration of the characteristics of the device due to the temperature rise of the drain surface portion in contact with the gate, and also to reduce the triggering voltage to improve the internal circuit It is an object of the present invention to provide an ESD protection device for a semiconductor integrated circuit that can be more effectively protected.

Electrostatic discharge protection device for a semiconductor integrated circuit of the present invention for achieving the above object, the semiconductor substrate doped with a first conductivity type impurities; A second conductive gate formed on the substrate and connected to the ground; A source of a first conductivity type formed in a substrate surface on one side of the gate and connected to ground; A drain of a first conductivity type formed in the substrate surface on the other side of the gate and connected to a pad; And a first region of a second conductivity type formed in a substrate under the gate and below one side of the drain, and a doping concentration greater than the first region in the substrate under the remaining drain portion while contacting the first region. And a second conductive region including a second conductive second region, wherein the drain, the second region, and the substrate region below the second region operate as a bipolar junction transistor.

Here, the semiconductor substrate is doped with a dose of 10E16 to 10E17 atoms / cm 3 as the first conductive impurity.

The first conductive source and drain are doped with a dose of 10E20 to 10E22 atoms / cm 3.

The second conductive type first region is doped with a dose of 10E15 to 10E16 atoms / cm 3.

The second conductive second region is doped with a dose of 10E18 to 10E19 atoms / cm 3.

The second conductive second region is formed to cover 50 to 100% of the bottom of the drain.

In addition, the corrector discharge protection device for a semiconductor integrated circuit of the present invention may further include a second conductive pick-up formed in the substrate surface spaced apart from the source.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view showing an ESD protection device for a semiconductor integrated circuit manufactured according to an embodiment of the present invention.

As shown in FIG. 3, the ESD protection device according to the present invention made of GGNMOS includes a semiconductor substrate 300 doped with N-type impurities and a P-type formed on the substrate 300 and connected to ground VSS. A gate 310, formed in a substrate surface on one side of the gate 310, an N-type source 320 connected to a ground VSS, and formed in a substrate surface on the other side of the gate 310, and a pad 400. The N-type drain 330 connected to the P-type first region 340a and the first region 340a formed in the substrate below the gate 310 and below one side of the drain 330 adjacent thereto. A P-type doped region 340 is formed in the substrate under the remaining drain 330 and is formed of a P-type second region 340b formed at a larger doping concentration than the first region 340a. In addition, although not shown, the semiconductor device may include a P-type pick-up formed in the substrate surface spaced apart from the source 320.

Here, the semiconductor substrate 300 is an N-substrate doped with a dose of 10E16 to 10E17 atoms / cm 3 with N-type impurities, and the N-type source 320 and the drain 330 are 10E20 to 10E22 atoms / cm 3. N + region doped with dose. Meanwhile, the P-type first region 340a is a P-region doped with a dose of 10E15 to 10E16 atoms / cm 3, and the P-type second region 340b is doped with a dose of 10E18 to 10E19 atoms / cm 3. P + region. Therefore, the regions having the highest impurity concentration among the regions are the source 320 and the drain 330, followed by the second region 340b, and then the semiconductor substrate under the second region 340b ( 300) followed by the first region 340a.

The P-type second region 340b is formed to have a thickness of the drain 330 so as to cover 50 to 100% of the bottom surface of the drain 330 to secure the performance of the ESD protection device.

In the case of the protection device including the GGNMOS having the above structure, the P-type first region 340a formed in the substrate under the gate 310 and one side of the drain 330 adjacent thereto is lower than the P-type second region 340b. Because of the doping concentration, the breakdown voltage between the drain 330 and the second region 340b is lower than the breakdown voltage between the drain 330 and the first region 340a. Therefore, when an ESD event occurs in the pad 400 and an avalanche breakdown occurs between the substrate 300 and the drain 330, the N-type drain 330, the P-type second region 340b, and the P-type The region of the N-substrate 300 under the second region 340b operates as a bipolar junction transistor (BJT), so that the ESD current is below the N-substrate 340b and the N-substrate at the N + drain 330. It passes through the (300) region to the N + source 320. That is, in the present invention, the parasitic BJT operates in a direction perpendicular to the substrate surface.

In this case, the current flow of parasitic BJT is mainly generated through the flat bottom of the drain 330. As such, when the bottom of the drain 330 becomes a main path of current flow, the phenomenon in which current is concentrated in a narrow portion of the drain sidewall does not occur as in the prior art. In addition, since the doped substrate portion corresponding to the drain bottom surface has a higher thermal conductivity than the drain surface portion, heat generated by the current flow is relatively easily released, thereby improving durability of the device.

In addition, the present invention forms a P + second region 340b having a higher doping concentration than the first region 340a in the lower portion of the drain 330, so that the collector (drain) and the base (base) are formed in the parasitic BJT. Since the breakdown voltage between the two regions can be lowered than before, the triggering voltage can be lowered so that the parasitic BJT can be turned on faster than before. Thus, the ESD protection range can be extended to more effectively protect the internal circuit from the ESD.

In addition, since the resistance between the pad and the internal circuit decreases as the triggering voltage decreases as described above, the present invention can increase the control speed of the internal circuit in the operating voltage state. Therefore, the ESD protection device of the present invention can effectively cope with the increasing speed of semiconductor integrated circuits.

4 is a current (I) -voltage (V) curve of the ESD protection device according to the prior art and the ESD protection device according to the present invention, which are curves corresponding to a case where a pick-up is formed.

Referring to FIG. 4, in the case of the ESD protection device according to the related art, the primary triggering voltage Vt1 is about 7 to 8V, and the current It2 during secondary triggering when the device is degraded by heat is 5.5 ( mA / μm) and the current If at the point where the drain melts due to heat is about 6 (mA / μm), whereas in the ESD protection device according to the present invention, the primary triggering voltage Vt1 'is about 3.9V. The current It2 'at the time of secondary triggering is about 6 (mA / µm), and the current If' at the point where the drain melts by heat is about 13.5 (mA / µm). Through the above results, it can be seen that the ESD protection device according to the present invention has a lower triggering voltage and excellent durability against heat than the ESD protection device according to the prior art.

Meanwhile, in the above-described embodiment of the present invention, the case of GGNMOS has been illustrated and described, but the method of the present invention may be equally applied to a case of a gate-powered PMOS (GPPMOS) in which a gate is connected to power. In the case of the GPPMOS, a semiconductor substrate doped with a P-type impurity, an N-type gate formed on the substrate and connected to a power to act as a ground, and a P formed in a substrate surface on one side of the gate and connected to a power to act as a ground. A source, a P-type drain formed in the substrate surface on the other side of the gate and connected to a pad, an N-type first region formed in the substrate under the gate and one side of the drain adjacent thereto, and in contact with the first region. An N-type doped region formed of an N-type second region formed in the substrate under the remaining drain portion with a larger doping concentration than the first region, wherein the drain, the second region, and the substrate region below the second region are bipolar. Act as a junction transistor.

Hereinbefore, the present invention has been illustrated and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications and variations can be made.

As described above, in the present invention, in forming an ESD protection device having a GGNMOS or GPPMOS structure, the parasitic bipolar junction transistor (BJT) operates in a direction perpendicular to the substrate, so that the bottom of the current flow is the main path of the current flow. In this case, it is possible to improve the durability of the device by preventing a phenomenon in which current and heat are concentrated on the drain side and the surface in the prior art using the drain side as the main path of the current flow.

In addition, the present invention provides a base region (second conductive type) having a higher doping concentration than the lower gate portion under a drain (first conductive type) serving as a collector of the parasitic bipolar junction transistor (BJT). By forming, it is possible to lower the triggering voltage, thereby enabling the ESD protection device to turn on quickly, thereby extending the ESD protection range to more effectively protect the internal circuits from damage of the ESD, and consequently, the semiconductor device. Can effectively cope with the trend of high integration and speed.

Claims (7)

An electrostatic discharge protection device for semiconductor integrated circuits that protects internal circuits from electrostatic discharge, A semiconductor substrate doped with a first conductive impurity; A second conductive gate formed on the substrate and connected to the ground; A source of a first conductivity type formed in a substrate surface on one side of the gate and connected to ground; A drain of a first conductivity type formed in the substrate surface on the other side of the gate and connected to a pad; And A first region of a second conductivity type formed in the substrate under the gate and below one side of the drain, and a second doping concentration greater than the first region in the substrate under the remaining drain portion while in contact with the first region; A second conductive region including a conductive second region; And said drain, said second region, and said substrate region under said second region act as bipolar junction transistors. The electrostatic discharge protection device for a semiconductor integrated circuit according to claim 1, wherein the semiconductor substrate is doped with a first conductive impurity at a dose of 10E16 to 10E17 atoms / cm 3. 2. The electrostatic discharge protection device for a semiconductor integrated circuit according to claim 1, wherein the first conductive source and drain are doped with a dose of 10E20 to 10E22 atoms / cm < 3 >. The electrostatic discharge protection device for a semiconductor integrated circuit according to claim 1, wherein the second conductive first region is doped with a dose of 10E15 to 10E16 atoms / cm3. The electrostatic discharge protection device for a semiconductor integrated circuit according to claim 1, wherein the second conductive second region is doped with a dose of 10E18 to 10E19 atoms / cm 3. The electrostatic discharge protection device for a semiconductor integrated circuit according to claim 1, wherein the second conductive second region is formed to cover 50 to 100% of the bottom surface of the drain. The electrostatic discharge protection device for a semiconductor integrated circuit according to claim 1, further comprising a pick-up of a second conductivity type formed in the substrate surface spaced apart from the source.

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