KR20070052912A - Electrostatic protection device for semiconductor circuit - Google Patents

Abstract

The present invention discloses an electrostatic protection device for a semiconductor circuit having a low triggering voltage. An electrostatic protection device for a semiconductor circuit according to the present invention, the semiconductor substrate of the first conductive type, the first conductive type gate formed on the substrate and connected to the ground, and formed in the surface of the substrate on one side of the gate, A second conductive type source connected to the source, a second conductive type drain formed in the substrate surface on the other side of the gate, and a drain of the second conductive type connected to the pad, and a drain side in the substrate surface below the gate, And a first conductive type doped region formed in a width and having a greater doping concentration than the substrate, and a first conductive type pick-up formed in the substrate surface spaced apart from the source.

Description

Electrostatic protection device for semiconductor circuits

1 is a cross-sectional view showing a static electricity protection device for a semiconductor circuit made of a conventional GGNMOS.

2 and 3 are cross-sectional views for explaining the operation of the electrostatic protection device for a conventional semiconductor circuit.

4 is a circuit diagram showing a conventional electrostatic protection element for a semiconductor circuit.

5, 6, 8 and 9 are cross-sectional views illustrating an electrostatic protection device for a semiconductor circuit composed of GGNMOS according to the present invention.

7 is an I / V comparison graph of an electrostatic protection device for semiconductor circuits made of GGNMOS according to the related art and the present invention.

Explanation of symbols on the main parts of the drawings

51: semiconductor substrate 52: gate

53: source 54: drain

55: pad 56: device isolation film

57: pick-up 60: P + doped region

70: N-drain

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electrostatic protection devices for semiconductor circuits, and more particularly, to static electricity protection devices for semiconductor circuits having a low triggering voltage.

As semiconductor circuits become increasingly integrated, highly integrated circuits operating at very low voltages are not only susceptible to very high voltages, but also sensitive. In particular, the inside of the semiconductor circuit is easily physically damaged by the very high voltage and current generated by the electrostatic discharge (ESD) pulse.

In other words, as the size of a semiconductor circuit decreases, an internal circuit becomes more vulnerable to electrostatic discharge because the thickness of a dielectric such as a gate insulating film becomes thinner, and the range of voltage for protecting the semiconductor circuit is also lowered. In a situation, there has been a need for improvement of the electrostatic protection device.

Hereinafter, an electrostatic protection device made of a gate grounded NMOS (GGNMOS), which has been widely used in the related art, will be described.

1 is a cross-sectional view showing an electrostatic protection device for a semiconductor circuit made of a conventional GGNMOS.

As shown, in the conventional electrostatic protection device made of GGNMOS, the drain 4 formed in the surface of the semiconductor substrate 1 is connected to the pad 5, and the gate 2 and the source 3 are connected to the ground 6. The pick-up 7 is connected to each other, and the pick-up 7 is formed to surround the device isolation layer 6 outside the device isolation layer 6 in contact with the source 3.

Here, the semiconductor substrate 1 is a P- substrate, the gate 2 is a P + gate, the source 3 and the drain 4 are N + junction regions doped with N-type impurities, and pick-up 7 ) Is a P + junction region.

In such a structure, when positive ESD occurs on the pad 5 side, impact ionization occurs between the drain 4 and the substrate 1 until there is an avalanche. Charges injected into the drain 4 accumulate in the drain 4.

In other words, when positive ESD occurs on the pad side, as shown in FIG. 2, a strong electric field is applied to the depletion region 8 of the drain 4, and the substrate 1 around the depletion region 8 is caused by this electric field. Impact ionization occurs as electrons are injected into the drain 4, and when avalanche breakdown occurs, as shown in FIG. 3, a hole current due to collision ionization (hole) is generated. The current 9 causes a current to flow from the drain to the pick-up through the substrate, which in turn causes a potential difference in the substrate resistance 10 to cause the parasitic bipolar junction transistor (BJT) to operate. As a result, GGNMOS, an electrostatic protection device, has a high current characteristic of BJP operation. In this case, the GGNMOS is triggered, and the voltage applied to the drain 4 at the time of the triggering is called a triggering voltage (Vt1).

However, as shown in FIG. 4, since the pad 5 is connected to the drain of the GGNMOS 20 having the static electricity protection function and is also connected to the internal operation circuit 30, ESD is prevented. When it occurs, the electrostatic protection device needs to be turned on faster than the internal circuit 30 that operates at high speed, so the triggering voltage of the protection device needs to be lowered. In particular, as semiconductor devices become more integrated and faster, a protection device having a lower triggering voltage is required. If the triggering voltage is high, the internal circuit is damaged by ESD because the operation speed of the protection device is slower than that of the internal circuit. Will wear.

However, since the ESD protection device made of the GGNMOS described above has difficulty in lowering the triggering voltage, it is difficult to cause the parasitic BJT to turn on quickly, and thus, there is a limit to protecting the internal circuit from the ESD.

Most of the existing methods proposed to solve this problem include inserting auxiliary circuits to assist the trigger in the electrostatic protection device, and these methods increase the area of the protection device.

In addition, in general, as a problem that the electrostatic protection device has on the internal circuit, the electrostatic protection device has a problem of causing an RC signal delay phenomenon by increasing input capacitance, thereby improving the problem and implementing an internal circuit that operates at high speed. In order to reduce the parasitic capacitance of the static protection device connected to the input and output pads.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, ESD protection for semiconductor integrated circuits to reduce the triggering voltage to more effectively protect the internal circuit without the problem of area increase due to the insertion of the auxiliary circuit. It is a first object to provide a device.

In addition, the present invention has a second object to provide an electrostatic protection device for a semiconductor circuit in which, in addition to the first object, the parasitic capacitance can be reduced to improve the operation speed.

Electrostatic protection device for a semiconductor circuit of the present invention for achieving the above object, the first conductive semiconductor substrate; A gate of a first conductivity type formed on the substrate and connected to ground; A second conductive source formed in a surface of the substrate on one side of the gate and connected to ground; A drain of a second conductivity type formed in the substrate surface on the other side of the gate and connected to a pad; A first conductive doped region formed in the substrate surface below the gate and having a width of 10 to 100% of the gate and having a greater doping concentration than the substrate; And a pick-up of a first conductivity type formed in the substrate surface spaced apart from the source.

Here, when the first conductivity type is P type and the second conductivity type is N type, the P type semiconductor substrate is doped with a dose of 10E15 to 10E16 atoms / cm 3, and the N type source and drain are 10E20 to 10E22 atoms. Doped with a dose of / cm < 3 >, and a P-type doped region is doped with a dose of 10E18-10E21 atoms / cm < 3 >.

On the other hand, when the first conductivity type is N type and the second conductivity type is P type, the N type semiconductor substrate is doped with a dose of 10E17 to 10E18 atoms / cm 3, and the P type source and drain are 10E20 to 10E22 atoms. Doped with a dose of / cm 3, and the N-type doped region is doped with a dose of 10E20-10E22 atoms / cm 3.

In addition, the electrostatic protection element for a semiconductor circuit of the present invention is formed in the remaining substrate region except the first conductive doping region among the substrate region adjacent to the drain, and further has a low concentration drain of the second conductive type having a lower doping concentration than the drain. It may include.

Here, the low concentration drain is doped with a dose of 10E13 to 10E15 atoms / cm 3 when the second conductivity type is N type.

On the other hand, the low concentration drain is doped with a dose of 10E17 to 10E19 atoms / cm 3 when the second conductivity type is P type.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, briefly describing the technical principle of the present invention, the present invention further forms a P + doped region in contact with the N + drain in the surface of the lower substrate of the electrostatic protection device having the GGNMOS structure.

In this case, since the P + doped region formed under the gate has a lower breakdown voltage from the N + drain than the conventional P-type substrate region, the triggering voltage at which the parasitic BJT is turned on due to the avalanche breakdown is reduced. Lower than conventional.

In detail, Figure 5 is a cross-sectional view for explaining an electrostatic protection device for a semiconductor circuit made of GGNMOS according to the present invention, as follows.

As shown, the electrostatic protection device for semiconductor circuits made of GGNMOS according to the present invention has a gate of P + on a P-type semiconductor substrate 51 doped with P-type impurities such as boron at a low concentration of 1E15 to 1E16 atoms / cm 3. 52 is formed, and N + source 53 and drain 54 doped with N-type impurities such as phosphorous or arsenic in one side of the gate 52 and the other side of the substrate surface at a high concentration of 1E20 to 1E22 atoms / cm 3. And P + doped regions 60 each having a width of 10 to 100% of the gate 52 and a greater doping concentration than the substrate while being in contact with the side surface of the drain 54 in the substrate surface below the gate 52. ) Is formed. The P + pick-up 57 is formed to surround the device isolation layer 56 on the outside of the device isolation layer 56 in contact with the source 53. Here, the P + doped region 60 is doped with a dose of 10E18 to 10E21 atoms / cm 3. In addition, the gate 52, the source 53, and the pick-up 57 are connected to the ground VSS, and the drain 54 is connected to the pad 55.

FIG. 5 is a cross-sectional view illustrating the case in which the P + doped region 60 is formed to have a smaller width than the gate 52, and FIG. 6 illustrates the case in which the P + doped region 60 is formed to have the same width as the gate 52. This is a cross-sectional view.

As described above, when the P + doped region 60 in contact with the drain 54 is further formed in the substrate region under the gate 52 in the GGNMOS structure, as described above, the breakdown between the drain 54 and the P + doped region 60 occurs. Since the voltage is lower than the breakdown voltage between the conventional drain and the P-type substrate, the triggering voltage at which the parasitic BJT is turned on is lower than before. The electrostatic protection device of the present invention has the advantage that the total area of the protection device does not increase because the P + doped region 60 is formed in the lower substrate of the gate 52 without inserting auxiliary circuits to assist the trigger.

On the other hand, as the area of the P + doped region 60 increases, the resistance of the substrate region including the P + doped region 60 decreases, so that the amount of current leaked when the device operates normally may be increased. .

FIG. 7 is a voltage (V) -current (I) curve for comparing and explaining the characteristics of the electrostatic protection device for semiconductor circuits according to the related art and the present invention (the protection device corresponding to FIG. 6). Although the triggering voltage Vt1 of the electrostatic protection device is about 7.9V, it can be seen that the triggering voltage Vt1 'of the protection device of the present invention is about 5.5V, which is about 2.4V smaller than that of the related art. That is, according to the method of the present invention, the triggering voltage can be reduced to about 70% of the conventional level.

In addition, the present invention provides a P + doped region 60 in the substrate region adjacent to the drain 54, as shown in Figs. An N-drain 70 having a lower doping concentration than the drain 54 may be further formed in the remaining substrate region except for. Here, the N-drain 70 is a low concentration junction region doped with a dose of 10E13 to 10E15 atoms / cm 3.

As described above, when the N-drain 70 is formed around the N + drain 54, the capacitance of the electrostatic protection device is increased because the thickness of the depletion region generated by the drain increases in the electrostatic protection device of the GGNMOS structure. This reduces the RC signal delay caused by the high capacitance of the electrostatic protection device and improves the operation speed of the device.

Meanwhile, in the above-described embodiment of the present invention, the electrostatic protection device of the GGNMOS structure has been shown and described, but the method of the present invention is also applied to the formation of the electrostatic protection device of the gate powered PMOS (GPPMOS) structure in which the gate is connected to power. can do.

In this case, in the electrostatic protection device of the GPPMOS structure, an N + gate is formed on an N-type semiconductor substrate doped with N-type impurities at a low concentration of 1E17 to 1E18 atoms / cm 3, and P-type impurities are formed on the substrate surfaces on both sides of the gate. A source and a drain of P + doped at a high concentration of ˜1E22 atoms / cm 3 are formed, having a width of 10 to 100% of the gate and a greater doping concentration than the substrate while contacting the side of the drain in the substrate surface below the gate. It has a structure in which an N + doped region is formed. The N + pick-up may be formed to surround the device isolation layer on the outside of the device isolation layer in contact with the source. Herein, the N + doped region is doped with a dose of 10E20 to 10E22 atoms / cm 3. Further, a P-type low concentration drain having a lower doping concentration than the drain may be further formed in the remaining substrate regions except for the N + doped region among the substrate regions adjacent to the drain. Here, the P-type low concentration drain is doped with a dose of 10E17 to 10E19 atoms / cm 3.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, in the present invention, in forming an electrostatic protection device for a semiconductor circuit having a GGNMOS or GPPMOS structure, a P + junction region (in the case of GNMOS) or an N + junction region (in the case of GPPMOS) is formed in contact with the drain in the lower substrate of the gate. By forming, the triggering voltage can be reduced without causing a problem of area increase, so that the electrostatic protection device can be turned on quickly, thereby effectively protecting the internal circuits from electrostatic damage, and consequently, the trend of high integration and high speed of semiconductor devices Can respond effectively to

In addition, in the present invention, in forming an electrostatic protection device for a semiconductor circuit having a GGNMOS or GPPMOS structure, a low concentration drain having a lower doping concentration than a drain may be formed in a substrate region adjacent to the drain, thereby reducing the capacitance of the electrostatic protection device. Therefore, the RC signal delay of the device can be suppressed and the operation speed of the device can be increased.

Claims (8)

An electrostatic discharge protection device for semiconductor circuits that protects internal circuits from static electricity, A first conductive semiconductor substrate; A gate of a first conductivity type formed on the substrate and connected to ground; A second conductive source formed in a surface of the substrate on one side of the gate and connected to ground; A drain of a second conductivity type formed in the substrate surface on the other side of the gate and connected to a pad; A first conductive doped region formed in the substrate surface below the gate and having a width of 10 to 100% of the gate and having a greater doping concentration than the substrate; And And a first conductive pick-up formed in the substrate surface spaced apart from the source. 2. The electrostatic protection device for semiconductor circuit according to claim 1, wherein the first conductive type is P type and the second conductive type is N type. The semiconductor device of claim 2, wherein the P-type semiconductor substrate is doped with a dose of 10E15 to 10E16 atoms / cm3, the N-type source and drain are doped with a dose of 10E20 to 10E22 atoms / cm3, and the P-type doped region is 10E18. A static electricity protection device for semiconductor circuits, characterized in that it is doped with a dose of ˜10E21 atoms / cm 3. 2. The electrostatic protection device for semiconductor circuit according to claim 1, wherein the first conductive type is N type and the second conductive type is P type. The N-type semiconductor substrate is doped with a dose of 10E17 to 10E18 atoms / cm 3, the P-type source and drain are doped with a dose of 10E20 to 10E22 atoms / cm 3, and the N-type doped region is 10E20. An electrostatic protection element for semiconductor circuits, characterized in that it is doped with a dose of ˜10E 22 atoms / cm 3. The method of claim 1, wherein the low concentration drain of the second conductivity type is formed in the remaining substrate region except for the first conductivity type doping region among the substrate region adjacent to the drain, and has a lower doping concentration than the drain. Electrostatic protection device for semiconductor circuits. 7. The electrostatic protection device of claim 6, wherein the low concentration drain is doped with a dose of 10E13 to 10E15 atoms / cm3 when the second conductivity type is N-type. 7. The electrostatic protection device of claim 6, wherein the low concentration drain is doped with a dose of 10E17 to 10E19 atoms / cm3 when the second conductivity type is P type.

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