KR100638455B1 - ESD protection circuit for high voltage device and semiconductor device comprising it - Google Patents

Abstract

The present invention relates to an ESD protection circuit for protecting an internal device of an integrated circuit from an electrostatic discharge (ESD) phenomenon.

An ESD protection circuit of the present invention includes: an MOS transistor having a ground voltage terminal connected to a gate and a source junction; And a PMOS transistor having a gate connected or floating to a ground voltage terminal and having one side junction thereof connected to the drain junction of the NMOS transistor and the other side junction thereof connected to the input / output pad of the device. The transistor is formed on a P-type substrate, and the PMOS transistor is formed on the N well to which the drain junction of the NMOS transistor is connected.

The ESD protection circuit of the above configuration can not only have good ESD characteristics even in a high voltage environment, but also has an advantage that the area occupied by the ESD protection circuit in the semiconductor device is small.

Integrated Circuits, ESD, High Voltage Interfaces, High Voltage Devices, Static Electricity

Description

ESD protection circuit for high voltage devices and a semiconductor device comprising the same             

1 is a cross-sectional view on a substrate of an ESD protection circuit according to the prior art;

2 is a cross-sectional view on a substrate of an ESD protection circuit according to the present invention;

3 is a top view of the ESD protection circuit of FIG. 2;

4 is a circuit diagram of the ESD protection circuit of FIG.

* Explanation of symbols for the main parts of the drawings

ENM: Enmotransistor EPM: Pymotransistor

101: P-type substrate 102: N well

121, 123: N drift region 122, 124: N active region

141, 143: P drift region 142, 144: P active region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to an ESD protection circuit for protecting internal elements of an integrated circuit from an electrostatic discharge (ESD) phenomenon.

There are two main types of electrostatic discharges. First, when the device is installed in any test equipment in the form of package, the static electricity generated by unstable ground state of the equipment is about 250V, but the impedance is small, so the amount of charge is relatively high (Machine Model). The second case is when the device touches the user's body and discharges the static electricity that has been induced in the human body, and discharges it through a high voltage of about 2000V or a large impedance (Human Body Model).

When exposed to such static electricity, MOS devices may experience gate oxide rupture, junction spiking, or the like, resulting in complete device destruction or minor damage, resulting in severe device reliability. affect.

Therefore, in order to protect the integrated circuit from destruction due to the inflow of static electricity, an ESD protection circuit is inserted at the connection portion between the inside and the outside of the integrated circuit. Electrostatic discharge is removed through the ground line or the Vcc line by the ESD protection circuit, and the internal circuit is safe.

On the other hand, in a ULSI / VLSI MOS device requiring high speed operation, a salicide (Salicide; Self-aligned Silicide) process is known as an efficient method for obtaining low contact resistance and capacitance, which is practically used.

However, when the salicide process is performed, the NMOS transistor drain of the ESD protection circuit is inevitably low in resistance, leading to deterioration in ESD characteristics, and thicker silicide layers are more susceptible to ESD.

Applicant of the present invention has proposed an improved prior art of the Republic of Korea Patent Application 2001-0016757 as a solution to the above problems. The improved conventional ESD protection circuit as shown in FIG. 1 includes a P-type substrate 301; An N well 302 formed in a portion of the P-type substrate; An NMOS transistor formed on the P-type substrate 301 and including an N + source junction, an N + drain junction, and a gate polysilicon to which a ground conductive line is contacted; A PMOS transistor formed on a substrate in the N well 302 region and including a P + drain junction, a P + source junction, and a gate polysilicon formed in contact with an N + source junction of the NMOS transistor; An N + junction formed in contact with the P + source junction of the PMOS transistor and having a pad conducting line contacted thereto; And a silicide layer formed on each gate polysilicon of the PMOS and NMOS transistors, and a source / drain junction and an N + junction.

According to the above-described improved conventional technique, the PMOS transistor is inserted into the drain region of the NMOS transistor, which is an ESD protection transistor, so that the ESD resistance of the PMOS transistor turned on under normal operation prevents deterioration of characteristics while preventing the deterioration of the characteristics. Good circuits and structures were obtained.

However, the improved prior art also has the following problems.

The ESD protection transistor should not be turned on during normal operation of the semiconductor device. When the ESD protection transistor of the prior art is applied to a device in a high voltage operating environment, the voltage during normal operation is large enough to turn on the ESD protection transistor. Thus, the ESD protection function is driven during normal operation. Therefore, the prior art ESD protection transistors cannot be used in high voltage devices.

In addition, the ground voltage is applied to the gate of the PMOS transistor constituting the ESD protection transistor of the prior art, such a structure to turn on the PMOS transistor, the resistance of the PMOS transistor is reduced, the flow path width of the current is It becomes wider. This structure also lowers the voltage at which the ESD protection transistor is turned on, which is a similar obstacle to application in high voltage devices.

The present invention has been made to solve the above problems, and an object thereof is to provide an ESD protection circuit having good ESD characteristics when applied to a high voltage device.

It is another object of the present invention to provide an ESD protection circuit which occupies a small area on the wafer substrate and has good ESD characteristics for high voltage devices.

An ESD protection circuit according to the present invention for achieving the above object, EnMOS transistor connected to the ground voltage terminal to the gate and source junction; And a PMOS transistor having a gate connected or floating to a ground voltage terminal and having one side junction thereof connected to the drain junction of the NMOS transistor and the other side junction thereof connected to the input / output pad of the device. The transistor is formed on a P-type substrate, and the PMOS transistor is formed on an N well to which the drain junction of the NMOS transistor is connected.

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Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

(Example)

The ESD protection circuit of this embodiment as shown in Figs. 2 and 3 includes a P-type substrate 101; An N well 102 formed in a portion of the P-type substrate 101; Source junction and drain having low concentration N + drift doped regions 121 and 123 formed in the P-type substrate 101 and high concentration N + active doped regions 122 and 124 formed in the N + drift doped region. Enmotransistors (ENMs) including junctions; And a low concentration of P + drift doped regions 141 and 143 formed in the N well 102, and a high concentration of P + active doped regions 142 and 144 formed in the P + drift doped regions. A PMOS transistor comprising an junction (EPM),

A ground voltage terminal is connected to a source and a gate of the ENMO transistor ENM, a drain of the ENMO transistor and a drain of the PMOS transistor EPM are conductively connected, and the PMOS transistor EPM is electrically connected. And an input / output pad of the device is connected to the source.

In the ESD protection circuit of this embodiment, a gate grounded NMOS (GGNMOS) is formed of an MOS transistor to function as an ESD protection device in a high voltage environment. That is, the breakdown voltage value itself is higher than that of the improved conventional MOS transistor in which the gate of the corresponding MOS transistor is floated, thereby making it suitable for a high voltage environment. In addition, it is preferable to apply a ground voltage to one gate terminal of the two MOS transistors ENM and EPM to increase the sensitivity of the ESD protection transistor to the voltage generated between the PAD terminal and the ground voltage terminal. However, in the illustrated structure, since the ground voltage is applied to the gate of the ENMO transistor ENM, the gate of the PMOS transistor EMP can be floated, which further increases the advantages for the high voltage device as described below.

The ESD protection circuit includes the MOS transistor between the ground and the pad to extract static electricity toward the ground, and for better ESD characteristics, the resistance from the drain region to the pad of the ESD protection enMOS transistor is increased. It is desirable to increase, because an improvement in ESD characteristics can be expected for the following reasons.

Firstly, by providing a uniform resistance across the drain, when the MOS transistor is turned on in an ESD situation, both ends of the MOS transistor are not first turned on and the transistor is uniformly Turn-on characteristic can be obtained. Second, when entering the Snap-Back mode in an ESD situation, in order to make the 2nd Breakdown voltage higher than the Snapback voltage, it is necessary to increase the drain's resistance component, so that several transistors simultaneously It can be turned on.

In the present invention, a PMOS transistor (EPM) is formed on the N well 102 positioned in the drain region of the ESD enMOS transistor (ENM) to impart a resistance of a required size. A ground voltage may be connected to or floated on the gate of the PMOS transistor EPM. In both cases, the carrier channel is allowed to be formed in contact with the gate insulating film of the PMOS transistor, but the case of applying the ground voltage forms a wider carrier channel. Therefore, in the case where the gate is floated, the resistance of the PMOS transistor EMP becomes larger in the normal operation, and therefore, the gate floating is more suitable for a high voltage environment.

As described above, the PMOS transistor (EPM) is turned on during normal operation to form a small resistance through the PMOS transistor, but the high voltage of a very high amount of charge at the source of the PMOS transistor (EPM). In this applied ESD situation, the turned-off PMOS transistor (EPM) has a very high resistance value, so the N well 102 at the bottom of the PMOS transistor (EPM) as an outflow path of the ESD current. A path through is formed. Therefore, in the ESD situation, since the current flowing from the outside passes through the N well 102, the necessary resistance is obtained through the N well. The obtained resistance value is large enough to increase the resistance from the drain region to the pad of the ESD protection enMOS transistor. Enhance the ESD characteristics of ENMOS transistors.

In FIG. 2 and FIG. 3, the PMOS transistors EMP and the ENMOS transistors ENM have a drift doping region 121 and 123 in which the source junction and the drain junction have a drift dopant region as compared with the prior art illustrated in FIG. 1. , 141, 143 and the active doped regions 122, 124, 142, and 144 have a dual structure. In the case of the high voltage device, a high voltage is applied between the pad and the ground voltage terminal even during normal operation, and this is to prevent the ESD ENMOS from operating at the normal operating voltage. That is, the junction breakdown of the source junction and the gate junction of the NMOS transistor ENM to which the normal operating voltage is applied are constituted by double junctions of the drift doping regions 121 and 123 and the active doping regions 122 and 124. By increasing the junction break-down voltage, the ENMO transistors do not operate at high voltages under normal operation, but operate at higher voltage stresses under ESD conditions. In order to utilize the characteristics of the higher-voltage ESD device, the source junction and the gate junction of not only the ESD enMOS transistor (ENM) but also the PMOS transistor (EPM) are the same as described above. It is preferable to configure a double junction of 142 and 144.

The ESD protection circuit according to the present embodiment is manufactured on a P-type substrate and can be applied to a semiconductor device having a high voltage interface having a large swing width of an input / output signal. In this case, the semiconductor device, the pad for inputting and outputting signals to an external device; An internal circuit that performs a predetermined processing function on a signal inputted and outputted to the outside through the pad; And the ESD protection circuit for protecting the internal circuit from ESD.

The circuit of Fig. 4 is a simplified circuit diagram of the ESD protection circuit of this embodiment, and the internal circuit is connected to the pad PAD on the circuit diagram via an input buffer and / or an output driver. The ESD protection circuit protects the internal circuitry and the buffer / driver circuit from static electricity in an ESD situation.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

By implementing the ESD protection circuit according to the present invention can not only have a good ESD characteristics in a high voltage environment, but also can reduce the area occupied by the ESD protection circuit in the semiconductor device.

Claims (8)

In an ESD protection circuit formed in a semiconductor device, An enMOS transistor having a ground voltage terminal connected to the gate and source junctions; And A gate connected to or floated at a ground voltage terminal, a drain junction of which is connected to a drain junction of the NMOS transistor, and a source junction of which is connected to an input / output pad of the device; And the NMOS transistor is formed on a P-type substrate, and the PMOS transistor is formed on an N well to which a drain junction of the NMOS transistor is connected. In an ESD protection circuit formed in a semiconductor device, P-type substrate; An N well formed in a portion of the P-type substrate; An MOS transistor comprising a source junction and a drain junction having a low concentration of N + drift doped region formed in the P-type substrate and a high concentration of N + active doped region formed in the N + drift doped region; And It includes a PMOS transistor formed in the N well, A ground voltage terminal is connected to a source and a gate of the MOS transistor, a drain of the MOS transistor and a drain of the PMOS transistor are conductively connected, and an input / output pad of the device is connected to the source of the PMOS transistor. ESD protection circuit. The method of claim 2, wherein the PMOS transistor, A source junction and a drain junction having a low concentration P + drift doped region formed in said N well, and a high concentration P + active doped region formed in said P + drift doped region. ESD protection circuit. The method of claim 2, The N + drift region of the drain junction of the NMOS transistor is formed in contact with the N well. The method of claim 2, The gate of the PMOS transistor is floating ESD protection circuit. The method of claim 2, An ESD protection circuit having a gate of the PMOS transistor connected to a ground voltage terminal. The method according to any one of claims 1 to 6, The ESD protection circuit is formed in a semiconductor device having a high voltage interface. A semiconductor device having a high voltage interface and manufactured on a P-type substrate, A pad for inputting and outputting a signal to and from an external device; An internal circuit that performs a predetermined processing function on a signal inputted and outputted to the outside through the pad; And The ESD protection circuit according to any one of claims 1 to 6, for protecting the internal circuit from ESD. Semiconductor device comprising a.

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