KR100713923B1 - Electrostatic protection device for semiconductor circuit - Google Patents

Abstract

The present invention discloses an electrostatic protection device for a semiconductor circuit. The electrostatic protection device for semiconductor circuits according to the present invention, which is disposed between a pad and an internal device, is constituted by a transistor and a pick-up, and is connected to a ground line and connected to a ground line, and between the main protection element and the sub protection element. In the electrostatic protection device for a semiconductor circuit comprising a first resistor formed in the, wherein the main protection device has a structure in which at least two transistors are connected in series, the secondary protection device has a second resistance between the source and the pick-up of the transistor The gate of each transistor of the primary protection device is connected to the source of the secondary protection device, the drain of the secondary protection device is connected to the pad, and the gate, source, pick-up and second of the secondary protection device. The resistor is characterized in that connected to the ground wire.

Description

Electrostatic protection device for semiconductor circuits

1 is a circuit diagram of a conventional electrostatic protection element for a semiconductor circuit.

2 is a cross-sectional view of a semiconductor device for explaining a GGNMOS structure.

3 is a circuit diagram of an electrostatic protection element for a semiconductor circuit according to an embodiment of the present invention.

4 is a cross-sectional view of an electrostatic protection device for a semiconductor circuit according to an embodiment of the present invention.

5 is a circuit diagram of an electrostatic protection element for a semiconductor circuit according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

21: semiconductor substrate 22a: deep-well

22b: P type well 23: gate

24: source 25: drain

26: pick-up 27: device isolation film

R1: first resistor R2: second resistor

VSS: Ground Wire VCC: Power Supply Voltage

PAD: Pad

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection device for semiconductor circuits, and more particularly, to an electrostatic protection device for semiconductor circuits having low input capacitance and advantageous for high speed operation.

In general, electrostatic discharge (ESD) is one of the important factors that determine the reliability of the semiconductor chip, the electrostatic discharge is generated when handling the semiconductor chip or mounted in the system to damage the semiconductor chip. Therefore, in order to protect the semiconductor chip from static electricity, the data input / output area of the semiconductor device is essentially provided with an electrostatic protection device. When a semiconductor chip contacts a charged human body or machine, the static electricity charged on the human body or machine is discharged into the semiconductor device through an input / output terminal through an external pin of the semiconductor chip. It can cause great damage. Most semiconductor devices have an electrostatic protection device between the input and output terminals and the semiconductor internal elements to protect the internal main circuit from such damage caused by static electricity.

On the other hand, as the integration of semiconductor devices increases, the thickness of the gate insulating film of the transistor is further reduced and the width of the wiring is also reduced, so that the internal devices of the semiconductor device can be more easily damaged by static electricity. That is, when the thickness of the gate insulating film of the transistor is reduced, the voltage for destroying the gate insulating film is lowered, and when the electrostatic protection device is used according to the conventional method, the gate insulating film of the transistor is destroyed by the static electricity of the lower voltage.

Therefore, as high integration proceeds, the electrostatic protection device also needs to be improved to more effectively prevent damage of the circuit due to static electricity, and much research has been made.

1 is a circuit diagram of a semiconductor device including an electrostatic protection device having a gate grounded NMOS (GGNMOS) structure, which is generally used.

Referring to FIG. 1, an electrostatic protection device for a semiconductor device may include an input / output pad PAD for receiving an external signal and a main connected between the input / output pad PAD and an internal device and connected to a ground line VSS. A protection element and a secondary protection element, and a resistor R located between the main protection element and the secondary protection element. In this case, the secondary protection device is an additional device for more efficiently and quickly performing the electrostatic discharge. Since the transistor has a shorter length than the main protection device, the secondary protection device operates faster than the main protection device when static electricity is introduced.

In the semiconductor device having such a structure, when static electricity flows into the input / output pad PAD, the secondary protection device is first turned on to discharge some of the static current to the ground line VSS. When current flows through the negative protection device, a voltage drop due to the resistor R occurs, and the drain voltage of the main protection device increases, thus inducing turn-on of the main protection device. That is, the turn-on of the main protection device is performed quickly by the operation of the sub protection device. As a result, the static electricity escapes to the ground line VSS through the main protection device and the sub protection device, thereby protecting the internal device.

Here, the main protection element and the sub protection element have a GGNMOS structure. Hereinafter, the GGNMOS structure will be described in more detail.

2 is a cross-sectional view of an electrostatic protection device for a semiconductor circuit made of a conventional GGNMOS.

As shown in FIG. 2, in the electrostatic protection device made of the conventional GGNMOS, the drain 5 formed in the surface of the well 2 of the semiconductor substrate 1 is connected to the pad PAD, and the gate 3 and the source are connected. 4 is connected to the ground line VSS, and the pick-up 6 formed on the outside of the device isolation layer 7 in contact with the source 4 is connected to the ground line VSS.

Here, the well 2 is P-type, the gate 2 is an N + gate, the source 3 and the drain 4 are N + junction regions, and the pick-up 7 is a P + junction region.

In such a structure, when positive ESD occurs on the pad PAD, impact ionization occurs between the drain 5 and the well 2 until the avalanche is formed. Charges injected into the drain 5 accumulate in the drain 5.

In other words, when positive ESD occurs on the pad PAD, a strong electric field is applied to the depletion region of the drain 5, and electrons in the well 2 around the depletion region are injected into the drain 5 by the electric field. Collision ionization occurs as a result of this, and when avalanche breakdown occurs, a pick-up through the well 2 in the drain 5 is performed by a hole current caused by collision ionization. 6) Current flows, and the current eventually increases the potential of the well 2 so that the parasitic bipolar junction transistor (BJT) is operated. As a result, the GGNMOS, an electrostatic protection device, is a BJT. It has a high current characteristic of operation. This is called GGNMOS triggering. As described above, the electrostatic protection device of the GGNMOS structure protects the internal device by flowing the static electricity introduced into the drain by the ground line VSS by the BJT operation.

However, as the integration of semiconductor devices progresses, the operating frequency of the chip increases, so that the capacitance of the electrostatic protection device increases, which causes the high-speed operation of the semiconductor device to be hindered. This is because the size of the electrostatic protection device is difficult to reduce even if the semiconductor device is highly integrated, and therefore, the parasitic capacitance due to the electrostatic protection device is very large in the total input capacitance. Therefore, it is essential to reduce the capacitance of the electrostatic protection device for high speed operation of the device.

On the other hand, as a method for improving the input capacitance increase problem due to the electrostatic protection device, a diode (Diode) or a protective device of the silicon coltrol rectifier (SCR) structure of the junction area is smaller than the MOS transistor, but the In the case of diodes, there is a problem in that the characteristics of the protection device deteriorate during reverse operation, and in the case of SCR devices, the triggering voltage corresponding to the turn-on voltage is high to protect the internal devices from electrostatic damage. The disadvantage is that it is difficult to do.

Accordingly, the present invention has been made to solve the conventional problems as described above, it is possible to lower the input capacitance without the problem of deterioration of the characteristics of the protection device or high triggering voltage, electrostatic protection device for semiconductor circuits advantageous for high speed operation The purpose is to provide.

The electrostatic protection device for semiconductor circuits of the present invention for achieving the above object, the main protection device and the secondary protection device is disposed between the pad and the internal device, and composed of a transistor and pick-up connected to the ground line, and the main protection In the electrostatic protection device for a semiconductor circuit comprising a first resistor formed between the device and the secondary protection device, the main protection device is a structure in which at least two transistors are connected in series, the secondary protection device is a source and pick-up of the transistor The second resistor is formed therebetween, the gates of the transistors of the primary protection device are connected to the source of the secondary protection device, the drain of the secondary protection device is connected to the pad, the gate, source, Pick-up and the second resistor is characterized in that connected to the ground line.

The main protection element may include a first well type deep well formed in a semiconductor substrate, at least two second conductive wells formed spaced apart from each other in the deep well, and each of the second conductive wells. A transistor formed in the region and including a gate of the first conductive type, a source of the first conductive type, and a drain of the first conductive type, and a pick-up of the second conductive type spaced apart from the source of each transistor; The gate of each transistor is connected to a source of a sub protection device, a drain of a transistor adjacent to a pad of the transistor is connected to a pad, and a source and pick-up of a transistor adjacent to a ground line are connected to a ground line, and other sources And the pickup is connected to the drain of an adjacent transistor.

The sub protection device may include a second conductive well formed in a semiconductor substrate, a second conductive well formed in the second conductive well region, and including a gate of a first conductive type, a source of a first conductive type, and a drain of a first conductive type. A transistor, a second resistor formed on a substrate spaced apart from the source of the transistor, and a second conductive pick-up formed in the substrate outside the second resistor, wherein the source comprises a gate of each transistor of the main protection element. And a drain are connected to a pad, and the gate, source, pick-up, and second resistor are connected to a ground line.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be briefly described.

The present invention is disposed between the pad and the internal element, and comprises a main protection element and a secondary protection element connected to the ground line and composed of a transistor and a pick-up, and a first resistor formed between the main protection element and the secondary protection element. In the electrostatic protection device for semiconductor circuits, the main protection device is formed in a structure in which at least two transistors are connected in series.

In this case, since the transistors of the main protection element are connected in series, the capacitance caused by the main protection element is reduced.

For example, when two transistors having the same capacitance C are connected in series, the total capacitance Ct becomes C / 2 by Equation (1) below.

1 / Ct = (1 / C) + (1 / C) Equation (1)

Therefore, when n transistors having the same capacitance C are connected in series, the total capacitance Ct is reduced to C / n.

Accordingly, the present invention can reduce the capacitance attributable to the electrostatic protection element to less than half the conventional one, and can improve the operation speed of the element.

However, as in the present invention, when the main protection device is formed in a structure in which two or more transistors are connected in series, the structure of the main protection device triggers the voltage since the multiple bipolar transistors must be turned on in succession for electrostatic discharge. There is a problem that increases. Accordingly, in the present invention, in order to prevent the above-mentioned triggering voltage increase problem, a second resistor is formed between the source and the pick-up of the sub protection device, and the source of the sub protection device is connected to the gate of each transistor of the main protection device. Let's do it.

As such, when a second resistor is formed between the source and the pick-up of the sub protection device, and the source of the sub protection device and the gate of each transistor of the main protection device are connected, the negative current is initially introduced into the pad. As the current flows through the protection element, a voltage drop due to the second resistor occurs, thereby increasing the gate voltage of the main protection element and easily turning on the MOS channel of the main protection element, thereby reducing the triggering voltage reduction problem of the main protection element. I can solve it.

Therefore, the present invention can improve the characteristics such as the operation speed of the device by reducing the input capacitance due to the electrostatic protection element to less than half without the problem of increasing the triggering voltage.

In detail, Figure 3 is a circuit diagram for explaining the electrostatic protection device for a semiconductor circuit according to the present invention, as follows.

Referring to FIG. 3, an electrostatic protection device for a semiconductor circuit having a protection device having a GGNMOS structure according to the present invention is disposed between a pad PAD and an internal device and is connected to a ground line PAD while being composed of a transistor and a pick-up. An electrostatic protection device for a semiconductor circuit comprising a main protection device and a sub protection device, and a first resistor (R1) formed between the main protection device and the sub protection device, wherein the main protection device has a structure in which two transistors are connected in series. The secondary protection device has a structure in which a second resistor R2 is formed between a source and a pick-up of a transistor, the gates of each transistor of the primary protection device are connected to a source of the secondary protection device, and the drain of the secondary protection device. Is connected to the pad PAD via the first resistor R1, and the gate, source, pick-up, and second resistor R2 of the sub protection device are connected to the ground line VSS.

Hereinafter, a cross-sectional structure of an electrostatic protection device for a semiconductor circuit having a protection device having a GGNMOS structure according to the present invention will be described with reference to FIG. 4.

Referring to FIG. 4, the main protection element of the electrostatic protection element for semiconductor circuits having the protection element of the GGNMOS structure of the present invention is an N-type deep-well 22a formed in the semiconductor substrate 21, and the N-type deep-well 22a. At least two P-type wells 22b spaced apart from each other, and formed in each of the P-type wells 22b, respectively, with a gate 23 of N +, a source 24 of N + and a drain 25 of N +, respectively. And a pick-up 26 of P + formed to be spaced apart from the source 24 of each transistor, the gate 23 of each transistor being connected to the source 24 of the secondary protection element, The drain 25 of the transistor adjacent to the pad PAD is connected to the pad PAD, and the source 24 and the pick-up 26 of the transistor adjacent to the ground line VSS are connected to the ground line VSS. The other source 24 and pick-up 26 are connected to the drain 25 of the adjacent transistor. . Here, the deep-well 22a prevents mutual interference between the transistors of the main protection element through the inside of the substrate to block the effect of connecting the transistors in parallel. On the other hand, reference numeral 27 that is not described indicates an isolation layer.

On the other hand, the secondary protection element of the electrostatic protection element for semiconductor circuits having the protection element of the GGNMOS structure of the present invention is a P-type well 22b formed in the semiconductor substrate 21, and formed in the region of the P-type well 22b and formed of N +. A transistor including a gate 23 and a source 24 of N + and a drain 25 of N +, a second resistor R2 formed on the substrate 21 spaced apart from the source 24 of the transistor, and the second resistor; A pick-up 26 of P + formed in the substrate 21 outside the two resistors R2, wherein the source 23 is connected to the gate 23 of each transistor of the main protection element, and the drain 25 ) Is connected to the pad PAD, and the gate 23, the source 24, the pick-up 26, and the second resistor R2 are connected to the ground line VSS.

Hereinafter will be described the operation characteristics of the electrostatic protection element for a semiconductor circuit of the present invention having the above-described structure.

In the normal operation of the semiconductor circuit having the above structure, since the gate 23 of the main protection element is connected to the ground line VSS through the source 24 of the sub protection element, the electrostatic protection element does not operate.

However, when a high voltage is applied through the pad PAD to the drain 25 of the sub protection device through the first resistor R1, avalanche breakdown occurs and a slight current flows to the ground line VSS due to parasitic bipolar operation. do.

As such, when a current flows through the sub protection device, a voltage drop occurs due to the second resistor R2, and the potential difference is applied to the gate 23 of the main protection device, and the applied potential difference is a threshold voltage. Above Vt), the MOS transistor of the main protection device is turned on.

As such, the turn-on of the MOS transistor of the main protection element serves to lower the triggering voltage at which the parasitic bipolar operation of the main protection element occurs. Therefore, as a result, the main protection device causes parasitic bipolar operation to discharge static electricity at a somewhat lower triggering voltage than conventionally.

Meanwhile, in the electrostatic protection device of the present invention shown and described with reference to FIGS. 3 and 4, since two transistors are connected in series to form a main protection device, as described above, the capacitance attributable to the main protection device is 1 Decrease to / 2. Here, the number of transistors connected in series in the main protection element may be increased to two or more. If n transistors are connected in series, the capacitance due to the main protection element is reduced to 1 / n of the related art. .

Therefore, the present invention can reduce the input capacitance caused by the electrostatic protection element to less than half without improving the triggering voltage to improve its characteristics such as the operating speed of the device.

On the other hand, the embodiment of the present invention described and described with respect to the electrostatic protection device having a GGNMOS structure, the method of the present invention can be applied to the electrostatic protection device having a GPPMOS (Gate Powered PMOS) structure as well. That is, as shown in FIG. 5, in the electrostatic protection device of the GPPMOS structure, the main protection device is composed of two or more transistors connected in series, and a second resistor R2 is disposed between the source and pick-up of the sub protection device. And the gate of the transistor of the main protection device is connected to the source of the sub protection device, whereby the same effect as in the above-described GGNMOS device can be obtained. In FIG. 5, the non-described VCC denotes a power supply voltage supply line, and R1 denotes a first resistor, respectively.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention implements an electrostatic protection device including a main protection device and a secondary protection device of a GGNMOS or GPPMOS structure, the main protection device is formed of a structure in which two or more transistors are connected in series, the secondary protection device By additionally forming a resistor between the source and the pick-up of the transistor, and by connecting the gate of the transistor of the main protection element and the source of the secondary protection element, the input capacitance caused by the electrostatic protection element is halved without increasing the triggering voltage. It can be reduced below to improve the operation speed of the device.

Therefore, according to the method of the present invention, it is possible to implement an electrostatic protection device capable of satisfying the low input capacitance characteristic required in the next generation high integration high speed product.

Claims (3)

A static electricity for a semiconductor circuit disposed between a pad and an internal device, the main circuit including a transistor and a pick-up, and including a main protection element and a sub protection element connected to a ground line, and a first resistor formed between the main protection element and the sub protection element; In the protective element, The main protection device comprising at least two series connected transistors between the pad and the ground line; Said secondary protection element comprising a transistor and a second resistor formed between the source and the pick-up thereof, Each gate of the transistors of the primary protection device is connected to a source of a transistor of the secondary protection device, a gate of the transistor of the secondary protection device is connected to the ground line, and a source of the transistor of the secondary protection device is the second resistor. Electrostatic protection device for a semiconductor circuit, characterized in that connected to the ground line through. The method of claim 1, The main protective element A first conductive type deep-well formed in the semiconductor substrate, at least two or more second conductive wells formed spaced apart from each other in the deep-well, and formed in each of the second conductive well regions, A transistor comprising a gate, a source of the first conductive type and a drain of the first conductive type, and a pick-up of the second conductive type spaced apart from the source of each transistor; The gate of each transistor is connected to the source of the secondary protection element, the drain of the transistor adjacent to the pad of the transistor is connected to the pad, the source and pick-up of the transistor adjacent to the ground line is connected to the ground line, and the other source and pickup The electrostatic protection device for a semiconductor circuit, characterized in that connected to the drain of the adjacent transistor. The method of claim 1, The secondary protection device A second conductive well formed in a semiconductor substrate, a transistor formed in the second conductive well region and including a gate of a first conductive type, a source of a first conductive type, and a drain of a first conductive type; A second resistor formed on the substrate and spaced apart from the source, and a second conductive type pick-up formed in the substrate outside the second resistor, And the source is connected to a gate of each transistor of a main protection device, the drain is connected to a pad, and the gate, source, pick-up, and second resistor are connected to a ground line.

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