CN117937404A - Electrostatic discharge protection circuit and electronic circuit - Google Patents

Abstract

The application discloses an electrostatic discharge protection circuit and an electronic circuit; the electrostatic discharge protection circuit comprises a first transistor, a second transistor, a third transistor and a discharge circuit. The drain of the first transistor is coupled to the bonding pad, and the source thereof is coupled to the first node. The gate of the second transistor is coupled to the power source, the drain thereof is coupled to the gate of the first transistor, and the source thereof is coupled to ground. The gate of the third transistor is coupled to the power source, the drain thereof is coupled to the first node, and the source thereof is coupled to ground. The discharging circuit is coupled between the bonding pad and the ground and controls the driving voltage on the first node. When an electrostatic discharge event occurs on the bonding pad, the discharge circuit provides a discharge path between the bonding pad and ground according to the driving voltage.

Description

Electrostatic discharge protection circuit and electronic circuit

Technical Field

The present invention relates to an electronic circuit, and more particularly, to an electrostatic discharge protection circuit.

Background

With the development of semiconductor processes of integrated circuits, the semiconductor device size has been reduced to submicron to increase the performance and operation speed of the integrated circuits, but the reduction of device size has raised some reliability problems, especially the greatest influence of the integrated circuits on the protection capability against electrostatic discharge (Electrostatic Discharge, ESD). Generally, the esd protection circuit and the protected circuit are coupled to the bonding pad for output or input. When an esd event occurs on the bonding pad, the gate voltage of the mosfet in the protected circuit is coupled to the bonding pad, and due to the effect of the gate coupling charge (gate coupling charge), the gate voltage in the protected circuit is turned on in advance with the voltage of the bonding pad, which results in a large current flowing through the mosfet, so that the mosfet and other devices in the protected circuit are damaged.

Disclosure of Invention

In view of the above, the present invention provides an esd protection circuit. The ESD protection circuit is coupled to a bonding pad for protecting the device. The ESD protection circuit includes a first transistor, a second transistor, a third transistor, and a discharge circuit. The first transistor has a first gate, a first drain coupled to the bonding pad, and a first source coupled to a first node. The second transistor has a first gate coupled to a power source, a second drain coupled to the first gate, and a second source coupled to a ground. The third transistor has a third gate coupled to the power source, a third drain coupled to the first node, and a third source coupled to ground. The discharging circuit is coupled between the bonding pad and the ground, and controls a driving voltage on the first node. When an electrostatic discharge event occurs on the bonding pad, the discharge circuit provides a discharge path between the bonding pad and ground according to the driving voltage.

The invention further provides an electronic circuit, which comprises a protected element, a first transistor, a second transistor, a third transistor and a discharge circuit. The protected element is coupled between a bonding pad and a ground. The first transistor has a first gate, a first drain coupled to the bonding pad, and a first source coupled to a first node. The second transistor has a first gate coupled to a power source, a second drain coupled to the first gate, and a second source coupled to a ground. The third transistor has a third gate coupled to the power source, a third drain coupled to the first node, and a third source coupled to ground. The discharging circuit is coupled between the bonding pad and the ground, and controls a driving voltage on the first node. When an electrostatic discharge event occurs on the bonding pad, the discharge circuit is triggered by the driving voltage to provide a discharge path between the bonding pad and ground.

Drawings

Fig. 1 shows an electronic circuit with an electronic circuit electrostatic discharge protection circuit according to an embodiment of the invention.

Fig. 2 is a schematic diagram of a discharge circuit in the electronic circuit of fig. 1 having a first circuit architecture according to an embodiment of the present invention.

Fig. 3A is a schematic diagram illustrating the operation of the electronic circuit of fig. 2 during normal operation.

FIG. 3B is a schematic diagram illustrating the operation of the electronic circuit of FIG. 2 when an ESD event is encountered.

Fig. 4 is a schematic diagram of a discharge circuit in the electronic circuit of fig. 1 having a second circuit architecture according to an embodiment of the present invention.

Fig. 5A is a schematic diagram illustrating the operation of the electronic circuit of fig. 4 during normal operation.

FIG. 5B is a schematic diagram illustrating the operation of the electronic circuit of FIG. 4 when an ESD event is encountered.

Fig. 6 is a top view of the protected device of fig. 1 and an NMOS transistor coupled to a bond pad in an esd protection circuit according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view taken along line A-A' of FIG. 1, in accordance with an embodiment of the present invention.

Reference numerals

1 Electronic circuit

10 Electrostatic discharge protection circuit

11 Protected element

12 Bonding pad

13. 14, 15, 16,20,40:Mos transistors

60P-type substrate 60

61P-doped region

70. 71, 72P-doped regions (P+)

73. 74, 75, 76, 77, 78: N-type doped regions (N +)

100 Drive circuit

101 Discharge circuit

DHVNW deep high pressure N-well region

GND, ground

HVNW, HVNW70, HVNW71 high voltage N-well

HVPW high voltage P-well region

N10 node

NBL N buried layer

P30, P50 current path

P31, P32, P51, P52 discharge path

PS70, PS71, PS72, PS73 polysilicon layer

PW, PW70, PW71, PW72, P-well region

S30, S50 drive Signal

T10 power supply terminal

T13A, T14A, T15A, T16A, T20A, T40A: grid electrode

T13B, T14B, T15B, T16B, T20B, T40B drain electrode

T13C, T14C, T15C, T16C, T20C, T40C, source electrode

T13D, T14D, T15D, T16D, T20D, T40D base

V10 drive Voltage

VDD: operating voltage

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Fig. 1 is a diagram illustrating an electronic circuit according to an embodiment of the invention. Referring to fig. 1, an electronic circuit 1 includes an electrostatic discharge protection circuit 10, a protected element 11, and a bonding pad 12. The esd protection circuit 10 is used to provide a discharging path between the bonding pad 12 and the ground GND when an esd event occurs on the bonding pad 12, so as to protect the protected device 11 from being damaged by a large current caused by the esd event.

Referring to fig. 1, the esd protection circuit 10 includes a driving circuit 100 and a discharging circuit 101. The driving circuit 100 includes Metal-Oxide-Semiconductor (MOS) transistors 13, 14, 15, and the protected device 11 includes at least one MOS transistor 16. In this embodiment, the MOS transistors 13, 14, 15, 16 are N-type in conductivity type, having a gate (gate), a drain (drain), a source (source), and a base (bulk). In the present specification, the N-type MOS transistor is simply referred to as an NMOS transistor.

As shown in fig. 1, the drain T16B of the NMOS transistor 16 of the protected device 11 is coupled to the bonding pad 12, and the source T16C and the base T16D thereof are coupled to the ground GND. The drain T13B of the NMOS transistor 13 of the driving circuit 100 is coupled to the pad 12, the source T16C is coupled to the node N10, and the base T13D is coupled to the ground GND. The gate T14A of the NMOS transistor 14 of the driving circuit 100 is coupled to the power terminal T10, the drain T14B thereof is coupled to the gate T13A of the NMOS transistor 13, and the source T14C and the base T14D thereof are coupled to the ground GND. The gate T15A of the NMOS transistor 15 of the driving circuit 100 is coupled to the power source terminal T10, the drain T15B thereof is coupled to the node N10, and the source T15C thereof is coupled to the base T15D thereof to the ground GND. The discharging circuit 101 is coupled between the bonding pad 12 and the ground GND, and is controlled by the driving voltage V10 at the node N10 to provide or not to provide a discharging path between the bonding pad 12 and the ground GND.

When an esd event occurs on the bonding pad 12, the discharging circuit 101 provides a discharging path between the bonding pad 12 and the ground GND according to the driving voltage V10 on the node N10. In one embodiment, the discharge circuit 101 includes a transistor. When an esd event occurs on the bond pad 12, the transistor of the discharge circuit 101 is turned on by the substrate or gate trigger to provide a discharge path.

Fig. 2 is a schematic diagram of a discharge circuit 101 in the electronic circuit 1 according to an embodiment of the invention. In the embodiment of fig. 2, the circuit configuration of the driving circuit 100 and the protected element 11 is the same as that of the embodiment of fig. 1, and the description thereof is omitted. Referring to fig. 2, the discharge circuit 101 includes an NMOS transistor 20. The gate T20A of the NMOS transistor 20 is coupled to the ground GND, the drain T20B thereof is coupled to the bonding pad 12, the source T20C thereof is coupled to the ground GND, and the base T20D thereof is coupled to the node N10. According to the circuit structure of the discharging circuit 101, when an esd event occurs on the bonding pad 12, the transistor of the discharging circuit 101 is triggered by the substrate to be turned on to provide a discharging path.

In the embodiment of fig. 2, the detailed operation of the esd protection of the electronic circuit 1 will be described below and related drawings.

Referring to fig. 3A, when the electronic circuit 1 is operating normally, the power terminal T10 receives the operating voltage VDD, and the gate T16A of the NMOS transistor 16 receives a driving signal S30. In this embodiment, the operating voltage VDD is, for example, 5 volts (V). The driving signal S30 is a device or circuit from the front end of the electronic circuit 1, so that the NMOS transistor 16 is turned ON (ON) or OFF (OFF) according to the driving signal S30. Since the gates T14A and T15A of the NMOS transistors 14 and 15 are coupled to the power terminal T10, the NMOS transistors 14 and 15 are turned ON (ON) according to the operation voltage VDD of 5V. The gate T13A of the NMOS transistor 13 is coupled to the ground GND through the turned-on NMOS transistor 14, which turns the NMOS transistor 13 OFF (OFF). Since the NMOS transistor 15 is turned on, the driving voltage V10 on the node N10 is close to or equal to the potential of the ground GND (e.g., 0V). At this time, the base T20D of the NMOS transistor 20 has a potential close to or equal to the ground GND, and the gate T20A and the source T20C are coupled to the ground GND, so that the NMOS transistor 20 is turned OFF (OFF).

According to the above, when the electronic circuit 1 is operating normally (no esd event occurs), the NMOS transistor 20 is turned off according to the driving voltage V10 on the node N10. In this way, the discharging circuit 101 does not provide any discharging path between the bonding pad 12 and the ground GND, so that the electronic circuit 1 can operate according to the driving signal S30.

Referring to fig. 3B, in the case that the electronic circuit 1 is not in the operation mode, the operation voltage VDD is not provided to the power terminal T10, and the gate T16A of the NMOS transistor 16 does not receive any driving signal or is at a voltage level of 0V. At this time, the power supply terminal T10 and the gate T16A of the NMOS transistor 16 are in a floating (floating) state. Since the power supply terminal T10 is in a floating state, the gate T14A of the NMOS transistor 14 is also in a floating state and the potential of the gate T14A is unknown (unknown). In this case, the drain T14B of the NMOS transistor 14 is also in a floating state, that is, the gate T13A of the NMOS transistor 13 is in a floating state.

When an electrostatic discharge event occurs on the bonding pad 12 of the electronic circuit 1, the potential of the bonding pad 12 increases instantaneously. Based ON the gate coupling effect, some of the charge is coupled by the bond pad 12 to the gate T13A of the NMOS transistor 13, which makes the NMOS transistor 13 slightly conductive (i.e., not fully conductive) to provide a current path P30. Since the NMOS transistor 13 is in the on state, the driving voltage V10 on the node N10 increases instantaneously as the voltage on the bonding pad 12 changes (or the driving voltage V10 on the node N10 is equal to the voltage on the bonding pad 12 at this time). At this time, the base T20D and the drain T20B of the NMOS transistor 20 have high potential, and the gate T20A and the source T20C are coupled to the ground GND, so the NMOS transistor 20 is turned ON (ON), which realizes substrate triggering. The turned-on NMOS transistor 20 provides a discharge path P31. The electrostatic charge on the bonding pad 12 is conducted to the ground GND through the NMOS transistor 20 and along the discharging path P31.

As described above, in the case where the electronic circuit 1 is not in the operation mode, the gate T16A of the NMOS transistor 16 is in the floating state. When an esd event occurs ON the bond pad 12, some of the charge is also coupled by the bond pad 12 to the gate T63A of the NMOS transistor 16 due to the gate coupling effect, which renders the NMOS transistor 16 slightly conductive (i.e., non-fully conductive) to provide a current path P32. In this embodiment, the turned-on NMOS transistor 20 has a smaller equivalent on-resistance than the equivalent on-resistance of the slightly turned-on NMOS transistor 16. Based on the shunting law, most of the electrostatic charge from the bond pad 12 is conducted to ground GND through the discharge path P31, and only a small portion of the electrostatic charge is conducted to ground GND through the discharge path P32. Therefore, when an esd event occurs on the bonding pad 12, even if the NMOS transistor 16 is turned on due to the gate coupling effect, the current flowing through the NMOS transistor 16 is small, which does not cause the NMOS transistor 16 to be damaged.

According to the embodiment of fig. 2 and fig. 3A and 3B, the esd protection circuit 10 provided in the present application can keep the NMOS transistor 20 of the discharging circuit 101 in an off state by providing the driving voltage V10 when the electronic circuit 1 is operating normally, so that the electronic circuit 1 can operate according to the driving signal S30. In the case that the electronic circuit 1 is not in the operation mode, when an esd event occurs on the bonding pad 12, the esd protection circuit 10 turns on the NMOS transistor 20 by the driving voltage V10 in a substrate-triggered manner to provide the discharging path P31. Even if the NMOS transistor 16 of the protected element 11 is turned on based on the gate coupling effect, since most of the electrostatic charge is conducted to the ground GND through the discharging path P31, a small amount of charge (i.e., a minute amount of current) flowing through the NMOS transistor 16 does not damage the NMOS transistor 16.

Fig. 4 is a schematic diagram of a discharge circuit 101 in the electronic circuit 1 according to an embodiment of the invention. In the embodiment of fig. 4, the circuit configuration of the driving circuit 100 and the protected element 11 is the same as that of the embodiment of fig. 1, and the description thereof is omitted. Referring to fig. 4, the discharge circuit 101 includes an NMOS transistor 40. The gate T40A of the NMOS transistor 40 is coupled to the node N10, the drain T40B is coupled to the pad 12, and the source T40C and the base T40D are coupled to the ground GND. According to the circuit structure of the discharging circuit 101, when an esd event occurs on the bonding pad 12, the transistor of the discharging circuit 101 is triggered to turn on by the gate to provide a discharging path.

In the embodiment of fig. 4, the detailed operation of the esd protection of the electronic circuit 1 will be described below and related drawings.

Referring to fig. 5A, when the electronic circuit 1 is operating normally, the power terminal T10 receives the operating voltage VDD, and the gate T16A of the NMOS transistor 16 receives a driving signal S50. In this embodiment, the operating voltage VDD is, for example, 5 volts (V). The driving signal S50 is a device or circuit from the front end of the electronic circuit 1, so that the NMOS transistor 16 is turned ON (ON) or OFF (OFF) according to the driving signal S50. Since the gates T14A and T15A of the NMOS transistors 14 and 15 are coupled to the power terminal T10, the NMOS transistors 14 and 15 are turned ON (ON) according to the operation voltage VDD of 5V. The gate T13A of the NMOS transistor 13 is coupled to the ground GND through the turned-on NMOS transistor 14, which turns the NMOS transistor 13 OFF (OFF). Since the NMOS transistor 15 is turned on, the driving voltage V10 on the node N10 is close to or equal to the potential of the ground GND (e.g., 0V). At this time, the gate T40A of the NMOS transistor 40 has a potential close to or equal to the ground GND, and thus the NMOS transistor 40 is turned OFF (OFF).

According to the above, when the electronic circuit 1 is operating normally (no esd event occurs), the NMOS transistor 40 is turned off according to the driving voltage V10 on the node N10. In this way, the discharging circuit 101 does not provide any discharging path between the bonding pad 12 and the ground GND, so that the electronic circuit 1 can operate according to the driving signal S50.

Referring to fig. 5B, in the case that the electronic circuit 1 is not in the operation mode, the operation voltage VDD is not provided to the power terminal T10, and the gate T16A of the NMOS transistor 16 does not receive any driving signal or is at a voltage level of 0V. At this time, the power terminal T10 and the gate T16A of the NMOS transistor 16 are in a floating state. Since the power supply terminal T10 is in a floating state, the gate T14A of the NMOS transistor 14 is also in a floating state and the potential of the gate T14A is unknown. In this case, the drain T14B of the NMOS transistor 14 is also in a floating state, that is, the gate T13A of the NMOS transistor 13 is in a floating state.

When an electrostatic discharge event occurs on the bonding pad 12 of the electronic circuit 1, the potential of the bonding pad 12 increases instantaneously. Based ON the gate coupling effect, some of the charge is coupled by the bond pad 12 to the gate T13A of the NMOS transistor 13, which makes the NMOS transistor 13 slightly turned ON (i.e., not fully turned ON) to provide a current path P50. Since the NMOS transistor 13 is in the on state, the driving voltage V10 on the node N10 increases instantaneously as the voltage on the bonding pad 12 changes (or the driving voltage V10 on the node N10 is equal to the voltage on the bonding pad 12 at this time). At this time, the gate T40A of the NMOS transistor 40 has a high potential, and thus the NMOS transistor 40 is turned ON (ON), which realizes gate triggering. The turned-on NMOS transistor 40 provides a discharge path P51 along which electrostatic charges on the bond pad 12 are conducted to the ground GND via the NMOS transistor 40.

As described above, in the case where the electronic circuit 1 is not in the operation mode, the gate T16A of the NMOS transistor 16 is in the floating state. When an esd event occurs ON the bond pad 12, some of the charge is also coupled by the bond pad 12 to the gate T63A of the NMOS transistor 16 due to the gate coupling effect, which renders the NMOS transistor 16 slightly conductive (i.e., non-fully conductive) to provide a current path P52. In this embodiment, the turned-on NMOS transistor 40 has a smaller equivalent on-resistance than the equivalent on-resistance of the slightly turned-on NMOS transistor 16. Based on the shunting law, most of the electrostatic charge from the bond pad 12 is conducted to ground GND through the discharge path P51, and only a small portion of the electrostatic charge is conducted to ground GND through the discharge path P52. Therefore, when an esd event occurs on the bonding pad 12, even if the NMOS transistor 16 is turned on due to the gate coupling effect, the current flowing through the NMOS transistor 16 is small, which does not cause the NMOS transistor 16 to be damaged.

According to the embodiment of fig. 4 and fig. 5A and 5B, the esd protection circuit 10 provided in the present application can keep the NMOS transistor 50 of the discharging circuit 101 in an off state by providing the driving voltage V10 when the electronic circuit 1 is operating normally, so that the electronic circuit 1 can operate according to the driving signal S50. In the case that the electronic circuit 1 is not in the operation mode, when an esd event occurs on the bonding pad 12, the esd protection circuit 10 turns on the NMOS transistor 50 by the driving voltage V10 in a gate-triggered manner to provide the discharging path P51. Even if the NMOS transistor 16 of the protected element 11 is turned on based on the gate coupling effect, since most of the electrostatic charge is conducted to the ground GND through the discharging path P51, a small amount of charge (i.e., a minute amount of current) flowing through the NMOS transistor 16 does not damage the NMOS transistor 16.

In the above embodiment, at least one of the NMOS transistors 13 and 16 and the NMOS transistors 20 and 40 in the discharging circuit 101 is a high voltage device, but not limited thereto. For example, at least one of NMOS transistors 13 and 16 and NMOS transistors 20 and 40 is implemented as a high voltage tolerant Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor.

Fig. 6 is a top view showing the structure of NMOS transistors 13 and 16 according to an embodiment of the present invention. For clarity of illustration of the connection of the NMOS transistors 13 and 16 to other components in the electronic circuit 1, fig. 6 also shows the bond pad 12, the power terminal T10, the ground GND, and the NMOS transistors 14, 15, and 20, and the associated connection wires. Referring to fig. 6, nmos transistors 13 and 16 are formed as a multi-finger structure in a common doped region on a P-type substrate 60 (shown in fig. 7) and surrounded by deep high voltage N-well DHVNW. In the multi-finger structure, a plurality of finger-shaped N-type doped regions (N+) are formed in a plurality of P-type well regions PW. Of these finger-shaped N-doped regions in the P-well PW, one part serves as the source region of the NMOS transistor 13 and the other part serves as the source region of the NMOS transistor 16. In one embodiment, the number of the finger-shaped N-doped regions in the P-well PW that are the source regions of the NMOS transistor 16 is greater than the number of the finger-shaped N-doped regions that are the source regions of the NMOS transistor 13. For example, there are 10 finger-shaped N-doped regions in the P-well PW, wherein 6 finger-shaped N-doped regions are used as the source region of the NMOS transistor 16 and 4 finger-shaped N-doped regions are used as the source region of the NMOS transistor 13, but not limited thereto.

Fig. 7 is a sectional view taken along line A-A' in fig. 6. Referring to fig. 7, an N-buried layer NBL, a deep high voltage N-well DHVNW, and a P-doped region 61 are formed on a P-substrate 60. In this embodiment, the P-type doped region 61 is used as the common doped region where the NMOS transistors 13 and 16 are formed together.

A high-voltage P-well HVPW and a plurality of high-voltage N-well HVNW are formed in the P-doped region (common doped region) 61. A plurality of P-well regions PW are formed in the high-voltage P-well region HVPW. In the cross-sectional view of FIG. 7, two high voltage N-well regions HVNW70 and HVNW71 and three P-well regions PW 70-PW 72 are shown. P-type doped regions (P+) 70-72 are formed in the P-type well regions PW 70-PW 72, respectively. An N-type doped region (N+) 73 is formed in the P-well PW 70. N-type doped regions 74 and 75 are formed in the P-type well PW71 and are located on opposite sides of the P-type doped region 71. An N-type doped region 76 is formed in the P-type well PW72. An N-type doped region 77 is formed in the N-type well region HVNW70. An N-type doped region 78 is formed in the N-well region HVNW71.

Referring to FIG. 6, a plurality of polysilicon layers PS are formed over the high voltage P-well region HVPW, the high voltage N-well region HVNW, and the P-well region PW. Referring to fig. 7, four polysilicon layers PS70, PS71, PS72, PS73 are shown in a cross-sectional view along line A-A'. A polysilicon layer PS70 is formed over the high voltage P-well HVPW, the high voltage N-well HVNW70, and the P-well PW70 between N-doped regions 73 and 77. A polysilicon layer PS71 is formed over the high voltage P-well HVPW, high voltage N-well HVNW70, and P-well PW71 between N-doped regions 74 and 77. A polysilicon layer PS72 is formed over the high voltage P-well HVPW, the high voltage N-well HVNW71, and the P-well PW71 between N-doped regions 75 and 78. A polysilicon layer PS73 is formed over the high voltage P-well HVPW, high voltage N-well HVNW71, and P-well PW72 between N-doped regions 76 and 78.

Referring to fig. 7, for the NMOS transistor 13, a contact electrode electrically connected to the polysilicon layers PS70 and PS73N serves as the gate T13A, a contact electrode electrically connected to the N-type doped regions 73 and 76 serves as the source T13C, and a contact electrode electrically connected to the P-type doped regions 70 and 72 serves as the base T13D. For the NMOS transistor 16, a contact electrode electrically connected to the polysilicon layers PS71 and PS72N serves as the gate T16A, a contact electrode electrically connected to the N-type doped regions 74 and 75 serves as the source T16C, and a contact electrode electrically connected to the P-type doped region 71 serves as the base T16D. The contact electrode electrically connected to the N-doped regions 77 and 78 serves as the drain T13B of the NMOS transistor 13 and also serves as the drain T16B of the NMOS transistor 16. Referring to fig. 1,2, 3A, 3B, 4, 5A, and 5B, the drain T13B of the NMOS transistor 13 and the drain T16B of the NMOS transistor 16 are coupled together and simultaneously coupled to the bonding pad 12.

The cross-sectional views of the semiconductor structures of the NMOS transistors 13 and 16 in fig. 7 are only examples, and are not limited thereto.

Although the invention has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that the foregoing and various other changes, modifications and variations may be made therein without departing from the spirit and scope of the invention as defined by the following claims.

Claims (20)

1. An electrostatic discharge protection circuit, coupled to a bonding pad, for protecting a protected device, comprising:

a first transistor having a first gate, a first drain coupled to the bond pad, and a first source coupled to a first node;

A second transistor having a first gate coupled to a power source, a second drain coupled to the first gate, and a second source coupled to a ground;

a third transistor having a third gate coupled to the power supply terminal, a third drain coupled to the first node, and a third source coupled to the ground; and

A discharging circuit coupled between the bonding pad and the ground, and controlling a driving voltage on the first node;

When an electrostatic discharge event occurs on the bonding pad, the discharge circuit provides a discharge path between the bonding pad and the ground according to the driving voltage.

2. The esd protection circuit of claim 1 wherein the discharge circuit comprises:

a fourth transistor having a fourth gate and a fourth source coupled to the ground, a fourth drain coupled to the bond pad, and a first base coupled to the first node.

3. The esd protection circuit of claim 2 wherein the fourth transistor is turned on according to the driving voltage to provide the discharge path when the esd event occurs on the bonding pad.

4. The esd protection circuit of claim 2 wherein the fourth transistor is turned off according to the driving voltage when the power supply terminal receives an operating voltage.

5. The esd protection circuit of claim 2 wherein the first transistor and the fourth transistor are ldmos transistors.

6. The esd protection circuit of claim 1 wherein the discharge circuit comprises:

a fourth transistor having a fourth gate coupled to the first node, a fourth drain coupled to the bond pad, and a fourth source coupled to the ground.

7. The ESD protection circuit of claim 6 wherein the fourth transistor is turned on according to the driving voltage to provide the discharge path when the ESD event occurs on the pad.

8. The ESD protection circuit of claim 6 wherein the fourth transistor is turned off according to the driving voltage when the power supply terminal receives an operating voltage.

9. The esd protection circuit of claim 6 wherein the first transistor and the fourth transistor are ldmos transistors.

10. The esd protection circuit of claim 1 wherein the first transistor further comprises a first base, the second transistor further comprises a second base, the third transistor further comprises a third base, and the first base, the second base, and the third base are all coupled to the ground.

11. The ESD protection circuit of claim 1 wherein the first transistor and the third transistor are N-type transistors.

12. The esd protection circuit of claim 1 wherein the protected device is coupled to the bond pad and comprises a fourth transistor, and the first transistor and the fourth transistor are formed in a common doped region on a substrate.

13. The esd protection circuit of claim 12 wherein the first transistor and the fourth transistor are ldmos transistors.

14. The esd protection circuit of claim 12 wherein the first transistor and the fourth transistor are formed in the common doped region in a multi-fingered configuration.

15. The ESD protection circuit of claim 14 wherein,

The common doped region has a first conductive type, and a first well region having the first conductive type is formed in the common doped region;

the multi-finger structure is provided with a plurality of finger-shaped doped regions in the first well region; and

The number of the plurality of finger doped regions forming the fourth transistor is greater than the number of the plurality of finger doped regions forming the first transistor.

16. An electronic circuit, comprising:

A protected element coupled between a bonding pad and a ground;

a first transistor having a first gate, a first drain coupled to the bond pad, and a first source coupled to a first node;

A second transistor having a first gate coupled to a power source, a second drain coupled to the first gate, and a second source coupled to a ground;

a third transistor having a third gate coupled to the power supply terminal, a third drain coupled to the first node, and a third source coupled to the ground; and

A discharging circuit coupled between the bonding pad and the ground, and controlling a driving voltage on the first node;

When an electrostatic discharge event occurs on the bonding pad, the discharge circuit is triggered by the driving voltage to provide a discharge path between the bonding pad and the ground.

17. The electronic circuit of claim 16, wherein the first transistor and the protected element are formed in a common doped region on a substrate.

18. The electronic circuit of claim 16, wherein the discharge circuit comprises:

a fourth transistor having a fourth gate and a fourth source coupled to the ground, a fourth drain coupled to the bond pad, and a first base coupled to the first node.

19. The electronic circuit of claim 16, wherein the discharge circuit comprises:

a fourth transistor having a fourth gate coupled to the first node, a fourth drain coupled to the bond pad, and a fourth source coupled to the ground.

20. The electronic circuit of claim 16, wherein the protected element comprises:

A fourth transistor having a fourth gate, a fourth drain coupled to the bonding pad, and a fourth source coupled to the ground;

Wherein the first transistor and the fourth transistor are formed in a multi-finger structure in a common doped region.