JP2021114722A - IC for voltage control piezoelectric element oscillator - Google Patents

IC for voltage control piezoelectric element oscillator Download PDF

Info

Publication number
JP2021114722A
JP2021114722A JP2020007182A JP2020007182A JP2021114722A JP 2021114722 A JP2021114722 A JP 2021114722A JP 2020007182 A JP2020007182 A JP 2020007182A JP 2020007182 A JP2020007182 A JP 2020007182A JP 2021114722 A JP2021114722 A JP 2021114722A
Authority
JP
Japan
Prior art keywords
voltage
piezoelectric element
nmos transistor
electrostatic protection
threshold voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2020007182A
Other languages
Japanese (ja)
Inventor
昌明 神谷
Masaaki Kamiya
昌明 神谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
INTERCHIP KK
Original Assignee
INTERCHIP KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by INTERCHIP KK filed Critical INTERCHIP KK
Priority to JP2020007182A priority Critical patent/JP2021114722A/en
Priority to PCT/JP2021/001736 priority patent/WO2021149693A1/en
Publication of JP2021114722A publication Critical patent/JP2021114722A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Oscillators With Electromechanical Resonators (AREA)

Abstract

To improve the control voltage of an oscillator circuit for a voltage control piezoelectric element, and the linearity of the oscillation frequency.SOLUTION: An integrated circuit 2 for a voltage control piezoelectric element oscillator includes voltage variable capacitance diodes 15 and 16, electrodes 3 and 4, resistor elements 17 and 18, and gate-grounded NMOS transistors 19 and 20 for protection from static electricity. The resistor elements 17 and 18 bias the control voltage to the voltage variable capacitance diodes 15 and 16. To the electrodes 3 and 4, a piezoelectric element vibrator 1 is connected. The NMOS transistors 19 and 20 for protection from static electricity have drains connected to the electrodes 3 and 4, and sources grounded. The threshold voltage of the gate-grounded NMOS transistors 19 and 20 for protection from static electricity is higher than the threshold voltage of the NMOS transistor used inside the IC.SELECTED DRAWING: Figure 1

Description

本発明は、制御電圧と発振周波数の線形性を向上させた電圧制御圧電素子発振用ＩＣに関する。 The present invention relates to a voltage-controlled piezoelectric element oscillation IC in which the linearity of the control voltage and the oscillation frequency is improved.

図１は、従来の電圧制御圧電素子発振器（ＶＣＸＯ：Voltage-Controlled Crystal Oscillator）の一例を示す回路図である。従来のＶＣＸＯは、水晶振動子（圧電素子）１と集積回路（ＩＣ）２を備えており、集積回路（ＩＣ）２は、水晶振動子１の一端に接続するＸ１端子３と、他端に接続するＸ２端子４と、制御電圧６が入力されるＶＣ端子５とを備えている。ＩＣ２の発振回路において、インバータ１１の入力側がコンデンサ１２を介してＸ１端子３側に接続され、インバータ１１の出力側が制御抵抗１３およびコンデンサ１４を介してＸ２端子４側に接続されている。また、帰還抵抗１０がインバータ１１に並列して接続している。尚、インバータ１１の出力にさらに増幅回路等を含む別のＩＣが接続されても良い。 FIG. 1 is a circuit diagram showing an example of a conventional voltage controlled piezoelectric element oscillator (VCXO: Voltage-Controlled Crystal Oscillator). The conventional VCXO includes a crystal oscillator (piezoelectric element) 1 and an integrated circuit (IC) 2, and the integrated circuit (IC) 2 has an X1 terminal 3 connected to one end of the crystal oscillator 1 and an integrated circuit (IC) 2 at the other end. It includes an X2 terminal 4 to be connected and a VC terminal 5 to which a control voltage 6 is input. In the oscillation circuit of IC2, the input side of the inverter 11 is connected to the X1 terminal 3 side via the capacitor 12, and the output side of the inverter 11 is connected to the X2 terminal 4 side via the control resistor 13 and the capacitor 14. Further, the feedback resistor 10 is connected in parallel with the inverter 11. In addition, another IC including an amplifier circuit or the like may be further connected to the output of the inverter 11.

さらに、Ｘ１端子３とＸ２端子４は、それぞれ、バリキャップダイオード（varicap diode、またはvariable capacitance diode（可変容量ダイオード））１５、１６を介して接地されている。Ｘ１端子３およびバリキャップダイオード１５が、抵抗１７を介してＶＣ端子５に接続され、Ｘ２端子４およびバリキャップダイオード１６が、抵抗１８を介してＶＣ端子５に接続されて、それぞれ制御電圧６が印加されている。また、Ｘ１端子３とバリキャップダイオード１５との間に、外部からの静電気による破壊を防ぐために静電気保護素子１９が接続しており、Ｘ２端子４とバリキャップダイオード１６との間にも、外部からの静電気による破壊を防ぐために静電気保護素子２０が接続している。静電気保護素子１９および２０として、ダイオードやゲート接地ＮＭＯＳトランジスタ（GGNMOSトランジスタ：Gate Grounded N-type MOSFET）などが使用されている。図１ではGGＮMOSが接続している。GGNMOS１９のドレインはＸ１端子３とバリキャップダイオード１５との間に接続し、GGNMOS１９のゲートとソースは接地している。GGNMOS２０のドレインはＸ２端子４とバリキャップダイオード１６との間に接続し、GGNMOS２０のゲートとソースは接地している。 Further, the X1 terminal 3 and the X2 terminal 4 are grounded via varicap diodes (varicap diodes or variable capacitance diodes) 15 and 16, respectively. The X1 terminal 3 and the varicap diode 15 are connected to the VC terminal 5 via the resistor 17, and the X2 terminal 4 and the varicap diode 16 are connected to the VC terminal 5 via the resistor 18, respectively, and the control voltage 6 is set. It has been applied. Further, an electrostatic protection element 19 is connected between the X1 terminal 3 and the varicap diode 15 in order to prevent damage due to static electricity from the outside, and the X2 terminal 4 and the varicap diode 16 are also connected from the outside. The electrostatic protection element 20 is connected in order to prevent the destruction due to static electricity. As the electrostatic protection elements 19 and 20, diodes, gate grounded NMOS transistors (GGNMOS transistors: Gate Grounded N-type MOSFETs), and the like are used. In FIG. 1, GGNMOS is connected. The drain of GGNMOS 19 is connected between the X1 terminal 3 and the varicap diode 15, and the gate and source of GGNMOS 19 are grounded. The drain of GGNMOS 20 is connected between the X2 terminal 4 and the varicap diode 16, and the gate and source of GGNMOS 20 are grounded.

ＧＧＭＯＳは、単純な構造で静電気対策を図れるという簡便性のため多数のＩＣにおいて静電気保護素子として多く使用されている。図２は、ＧＧＮＭＯＳを使用した静電気保護機能を説明する図である。図２に示すように、ＧＧＮＭＯＳ３１のドレインはＮＭＯＳトランジスタ３１に付随してダイオード３２が接続された構成となっている。これにより、ＧＧＮＭＯＳは、正の静電気に対してはＮＭＯＳトランジスタ３１のドレインブレイクダウンによりＭＯＳ電流Ａが流れ、また負の静電気に対してはダイオードの順方向電流Ｂが流れて、静電気を逃がす機能を担っている。 GGMOS is often used as an electrostatic protection element in many ICs because of its simplicity of being able to take measures against static electricity with a simple structure. FIG. 2 is a diagram illustrating an electrostatic protection function using GGNMOS. As shown in FIG. 2, the drain of the GGNMOS 31 has a configuration in which a diode 32 is connected to the NMOS transistor 31. As a result, the GGNMOS has a function of allowing the MOS current A to flow due to the drain breakdown of the NMOS transistor 31 for positive static electricity and the forward current B of the diode for negative static electricity to release the static electricity. I am in charge.

図３は、負のドレイン電圧に対するＧＧＮＭＯＳ（ＥＳＤＭＯＳ）のドレイン電流を示す図である。ＧＧＮＭＯＳはＥＳＤ保護用ＭＯＳトランジスタであるからＥＳＤＭＯＳとも呼ばれる。図１に示すＧＧＮＭＯＳとして、ＩＣ内部に使われるＮＭＯＳトランジスタと同じ閾値電圧のものが標準的に使用されている。ＩＣ内部回路に使われるＮＭＯＳトランジスタの閾値は約０．６Ｖであるから、図３に示すように、ＧＧＮＭＯＳのドレインに負の電圧（ＶＤ）を上げていくと、負電圧が約０．４Ｖ以上でＭＯＳ動作によるサブスレッショルド電流（ＭＯＳ電流とも言う）（Ｃ）が流れ始めて、さらに負電圧が約０．６Ｖ以上になるとダイオードと基板間にダイオードの順方向電流（Ｄ）が流れる。 FIG. 3 is a diagram showing the drain current of GGNMOS (ESDMOS) with respect to a negative drain voltage. Since GGNMOS is a MOS transistor for ESD protection, it is also called ESD MOS. As the GGNMOS shown in FIG. 1, one having the same threshold voltage as the NMOS transistor used inside the IC is used as standard. Since the threshold value of the NMOS transistor used in the IC internal circuit is about 0.6V, as shown in FIG. 3, when the negative voltage (VD) is increased to the drain of the GGMOS, the negative voltage becomes about 0.4V or more. When the sub-voltage current (also referred to as MOS current) (C) due to the MOS operation starts to flow and the negative voltage becomes about 0.6 V or more, the forward current (D) of the diode flows between the diode and the substrate.

特開２００２−２６６６０JP-A-2002-266660

図４は、図１に示したＸ１端子およびＸ２端子におけるバイアス電圧（Ｖbias）と制御電圧（ＶＣ）との関係を示すグラフであり、図１に示した電圧制御圧電素子発振器が発振していてＸ１端子およびＸ２端子における発振振幅（ＭＡＸ）電圧Ｖｍが約０．６Ｖの場合を示している。制御電圧ＶＣが０Ｖに近づくと、ＧＧＮＭＯＳトランジスタのドレインに０．４Ｖ以上の負電圧がかかるために、図３から分かるように、Ｘ１端子およびＸ２端子には接地側からＭＯＳ電流が流れ込み、バイアス電圧Ｖbiasは制御電圧ＶＣより高くなる。 FIG. 4 is a graph showing the relationship between the bias voltage (Vbias) and the control voltage (VC) at the X1 terminal and the X2 terminal shown in FIG. 1, and the voltage-controlled piezoelectric element oscillator shown in FIG. 1 is oscillating. The case where the oscillation amplitude (MAX) voltage Vm at the X1 terminal and the X2 terminal is about 0.6V is shown. When the control voltage VC approaches 0V, a negative voltage of 0.4V or more is applied to the drain of the GGNMOS transistor. Therefore, as can be seen from FIG. 3, MOS current flows into the X1 and X2 terminals from the ground side, and the bias voltage. Vbias is higher than the control voltage VC.

その結果、図５（制御電圧ＶＣに対する発振周波数変動を示す図）に示すように、制御電圧ＶＣを低くしても発振周波数はＶＣ電圧に比例して低下せず飽和特性を示す。電圧制御発振回路においては、制御電圧と発振周波数の線形性を良好にして（理想形は、破線で示す状態）、発振周波数を制御電圧で調整しやすくすることが要求されているので、このような飽和特性は問題となる。 As a result, as shown in FIG. 5 (a diagram showing the oscillation frequency fluctuation with respect to the control voltage VC), even if the control voltage VC is lowered, the oscillation frequency does not decrease in proportion to the VC voltage and shows saturation characteristics. In the voltage control oscillation circuit, it is required to improve the linearity of the control voltage and the oscillation frequency (the ideal form is shown by the broken line) and to make it easy to adjust the oscillation frequency with the control voltage. Saturation characteristics are a problem.

本発明は、上記課題を解決するために、電圧制御圧電素子発振器用ＩＣで使用されるゲート接地ＮＭＯＳトランジスタ（ＧＧＮＭＯＳトランジスタ）の閾値電圧を従来のＩＣ内部で使用されるＮＭＯＳトランジスタの閾値電圧よりも高くする。具体的には以下の特徴を有する。
（１）本発明は、電圧可変容量ダイオードと、前記電圧可変容量ダイオードに制御電圧をバイアスする抵抗素子と、圧電素子振動子と接続するための電極と、前記電極に接続された静電気保護用ＮＭＯＳトランジスタを有する電圧制御圧電素子発振器用集積回路（ＩＣ）において、前記静電気保護用ＮＭＯＳトランジスタの閾値電圧をＩＣ内部に用いられるＮＭＯＳトランジスタの閾値電圧より高くしたことを特徴とする電圧制御圧電素子発振器用ＩＣであり、ＩＣ内部に用いられる前記ＮＭＯＳトランジスタの閾値電圧が約０．６Vであるとき、前記静電気保護用ＮＭＯＳトランジスタの閾値電圧を約０．７V以上にし、またＩＣ内部に用いられる前記ＮＭＯＳトランジスタの閾値電圧がＹＶであるとき、前記静電気保護用ＮＭＯＳトランジスタの閾値電圧を（Ｙ＋０．１）Ｖ以上にすることを特徴とする。 In order to solve the above problems, the present invention sets the threshold voltage of the gate-grounded NMOS transistor (GGNMOS transistor) used in the voltage-controlled piezoelectric element oscillator IC to be higher than the threshold voltage of the NMOS transistor used inside the conventional IC. Make it high. Specifically, it has the following features.
(1) In the present invention, a voltage variable capacitance diode, a resistance element that biases a control voltage to the voltage variable capacitance diode, an electrode for connecting to a piezoelectric element transducer, and an electrostatic protection NMOS connected to the electrode. In an integrated circuit (IC) for a voltage-controlled piezoelectric element oscillator having a transistor, the threshold voltage of the electrostatic protection NMOS transistor is made higher than the threshold voltage of the NMOS transistor used inside the IC. When the threshold voltage of the NMOS transistor which is an IC and is used inside the IC is about 0.6V, the threshold voltage of the IPsec transistor for electrostatic protection is set to about 0.7V or more, and the NMOS transistor used inside the IC is set to about 0.7V or more. When the threshold voltage of the above is YV, the threshold voltage of the electrostatic protection NMOS transistor is set to (Y + 0.1) V or more.

（２）本発明は、電圧可変容量ダイオードと、前記電圧可変容量ダイオードに制御電圧をバイアスする抵抗素子と、圧電素子振動子と接続するための電極と、前記電極に接続された静電気保護用ＮＭＯＳトランジスタを有する電圧制御圧電素子発振器用集積回路（ＩＣ）において、静電気保護用ＮＭＯＳトランジスタのドレインに０．６Ｖ以上の負電圧が印加されたときに、ＭＯＳ動作によるドレイン電流がドレインと基板間のダイオード電流よりも小さくなるように、前記静電気保護用ＮＭＯＳトランジスタの閾値電圧を高くしたことを特徴とする電圧制御圧電素子発振器用ＩＣであり、前記静電気保護用ＮＭＯＳトランジスタの閾値電圧は、ドレインと基板間のダイオードの順方向電圧より高いことを特徴とする。 (2) In the present invention, a voltage variable capacitance diode, a resistance element that biases a control voltage to the voltage variable capacitance diode, an electrode for connecting to a piezoelectric element transducer, and an electrostatic protection NMOS connected to the electrode. In an integrated circuit (IC) for a voltage-controlled piezoelectric element oscillator having a transistor, when a negative voltage of 0.6 V or more is applied to the drain of an IPsec transistor for electrostatic protection, the drain current due to MOS operation is a diode between the drain and the substrate. A voltage-controlled piezoelectric element oscillator IC characterized in that the threshold voltage of the electrostatic protection NMOS transistor is increased so as to be smaller than the current. The threshold voltage of the electrostatic protection NMOS transistor is between the drain and the substrate. It is characterized in that it is higher than the forward voltage of the transistor.

（３）本発明は、電圧可変容量ダイオードと、前記電圧可変容量ダイオードに制御電圧をバイアスする抵抗素子と、圧電素子振動子と接続するための電極と、前記電極に接続された静電気保護用ＮＭＯＳトランジスタを有する電圧制御圧電素子発振器用集積回路（ＩＣ）の製造方法であって、前記ＩＣ内部に用いられるＰＭＯＳトランジスタの領域に打ち込むＰ型不純物イオンのイオン注入時に、前記静電気保護用ＮＭＯＳトランジスタを形成する領域にも同種で同量のＰ型不純物イオンのイオン注入を行ない、前記静電気保護用ＮＭＯＳトランジスタの閾値電圧をＩＣ内部に用いられるＮＭＯＳトランジスタの閾値電圧より高くしたことを特徴とする電圧制御圧電素子発振器用ＩＣの製造方法であり、前記イオン注入工程の前に、前記ＩＣ内部に用いられるＰＭＯＳトランジスタの領域および前記静電気保護用ＮＭＯＳトランジスタを形成する領域を同時に窓開けするフォトリソ工程を行なうことを特徴とする。 (3) In the present invention, a voltage variable capacitance diode, a resistance element that biases a control voltage to the voltage variable capacitance diode, an electrode for connecting to a piezoelectric element transducer, and an electrostatic protection NMOS connected to the electrode. This is a method for manufacturing an integrated circuit (IC) for a voltage-controlled piezoelectric element oscillator having a transistor, and forms the electrostatic protection NMOS transistor when ion injection of P-type impurity ions to be driven into the region of the epitaxial transistor used inside the IC. The voltage-controlled piezoelectricity is characterized in that the same amount of P-type impurity ions are injected into the region to be used, and the threshold voltage of the NMOS transistor for electrostatic protection is made higher than the threshold voltage of the NMOS transistor used inside the IC. It is a method of manufacturing an IC for an element oscillator, and before the ion injection step, a photolitho step of simultaneously opening a window of a region of a epitaxial transistor used inside the IC and a region of forming the electrostatic protection NMOS transistor is performed. It is a feature.

電圧制御発振回路において、ＧＧＮＭＯＳトランジスタの閾値電圧をＩＣ内部のＮＭＯＳトランジスタの閾値電圧より高くすることにより、制御電圧ＶＣを小さくしても制御電圧ＶＣと発振周波数の線形性を改善できる。特に制御電圧ＶＣが０Ｖに近づいても、バイアス電圧Ｖbiasと制御電圧ＶＣの線形性を維持し、理想特性に近くすることが可能となる。本発明の電圧制御発振器の周波数特性に関して、Ｘ１端子およびＸ２端子の発振振幅が約０．６Ｖ以下であれば、ほぼ理想の特性を得ることができる。また、ＧＧＮＭＯＳトランジスタの閾値電圧をＩＣ内部のＮＭＯＳトランジスタの閾値電圧より上げるためのイオン注入をＩＣ内部のＰＭＯＳトランジスタの閾値電圧調整用イオン注入と同時に行なうことにより、ＩＣのプロセスコストを増大することもなく実現できる。 In the voltage control oscillation circuit, by making the threshold voltage of the GGNMOS transistor higher than the threshold voltage of the NMOS transistor inside the IC, the linearity of the control voltage VC and the oscillation frequency can be improved even if the control voltage VC is reduced. In particular, even when the control voltage VC approaches 0 V, the linearity of the bias voltage V bias and the control voltage VC can be maintained, and the characteristics can be approached to the ideal characteristics. Regarding the frequency characteristics of the voltage controlled oscillator of the present invention, if the oscillation amplitudes of the X1 terminal and the X2 terminal are about 0.6 V or less, almost ideal characteristics can be obtained. Further, the process cost of the IC can be increased by simultaneously injecting ions to raise the threshold voltage of the GGMOS transistor to be higher than the threshold voltage of the NMOS transistor inside the IC at the same time as ion injection for adjusting the threshold voltage of the epitaxial transistor inside the IC. Can be realized without.

図１は、電圧制御圧電素子発振器の一例を示す回路図である。FIG. 1 is a circuit diagram showing an example of a voltage-controlled piezoelectric element oscillator. 図２は、ＧＧＮＭＯＳを使用した静電気保護機能を説明する図である。FIG. 2 is a diagram illustrating an electrostatic protection function using GGNMOS. 図３は、負のドレイン電圧に対するＧＧＮＭＯＳ（ＥＳＤＭＯＳ）のドレイン電流を示す図である。FIG. 3 is a diagram showing the drain current of GGNMOS (ESDMOS) with respect to a negative drain voltage. 図４は、図１に示したＸ１端子およびＸ２端子におけるバイアス電圧（Ｖbias）と制御電圧（ＶＣ）との関係を示す図である。FIG. 4 is a diagram showing the relationship between the bias voltage (Vbias) and the control voltage (VC) at the X1 terminal and the X2 terminal shown in FIG. 図５は、制御電圧ＶＣに対する発振周波数変動を示す図である。FIG. 5 is a diagram showing oscillation frequency fluctuation with respect to the control voltage VC. 図６は、本発明を適用した効果を示す図で、ＧＧＮＭＯＳトランジスタの閾値電圧をＩＣ内部のＮＭＯＳトランジスタ閾値電圧より高くしたときのバイアス電圧Ｖbiasと制御電圧ＶＣの関係を示す図である。FIG. 6 is a diagram showing the effect of applying the present invention, and is a diagram showing the relationship between the bias voltage Vbias and the control voltage VC when the threshold voltage of the GGNMOS transistor is made higher than the threshold voltage of the NMOS transistor inside the IC.

本発明は、制御電圧と発振周波数線形性を改善して発振周波数制御の精度を向上させる手段を提供する。図５に示されるように、制御電圧ＶＣが小さくなると発振周波数変動が飽和して発振周波数変動と制御電圧との線形性が悪くなる。これを改善するには、図４に示されるように、制御電圧ＶＣが小さくなってもバイアス電圧Ｖbiasと制御電圧ＶＣの線形性を維持して、図４に破線で示す理想形に近づくようにすることである。そのためには、図３から分かるように、ＧＧＮＭＯＳのドレインに印加される負電圧が０．４Ｖ以上で流れるサブスレッショルド（サブスレッショルドリーク）電流を小さくすれば良い。理想的には、ダイオードの順方向電流が流れる０．７Ｖ程度まではサブスレッショルド電流が流れないようにすれば良い。（ＧＧＮＭＯＳトランジスタでは、ゲートとソースが接地しているので、ドレイン電圧に負電圧が印加されると、ゲート電圧はドレイン電圧に対して正電圧側となるので、図３におけるドレイン電圧ＶＤはゲート電圧（正）と置き換えても良い。） The present invention provides means for improving the control voltage and oscillation frequency linearity to improve the accuracy of oscillation frequency control. As shown in FIG. 5, when the control voltage VC becomes small, the oscillation frequency fluctuation becomes saturated and the linearity between the oscillation frequency fluctuation and the control voltage deteriorates. To improve this, as shown in FIG. 4, maintain the linearity of the bias voltage Vbias and the control voltage VC even when the control voltage VC becomes small, and approach the ideal shape shown by the broken line in FIG. It is to be. For that purpose, as can be seen from FIG. 3, the subthreshold (subthreshold leakage) current in which the negative voltage applied to the drain of the GGNMOS flows at 0.4 V or more may be reduced. Ideally, the subthreshold current should not flow up to about 0.7V, where the forward current of the diode flows. (In the GGNMOS transistor, since the gate and the source are grounded, when a negative voltage is applied to the drain voltage, the gate voltage is on the positive voltage side with respect to the drain voltage. Therefore, the drain voltage VD in FIG. 3 is the gate voltage. It may be replaced with (correct).)

そこで、本発明はＧＧＮＭＯＳトランジスタの閾値電圧（Ｖth(ＧＧＮＭＯＳ)）を従来の閾値電圧、すなわちＩＣ内部のＮＭＯＳトランジスタの閾値電圧（Ｖth(IｎＮＭＯＳ)）より高くする（すなわち、Ｖth(ＧＧＮＭＯＳ)＞Ｖth(ＩｎＮＭＯＳ)）ことにより、制御電圧ＶＣを小さくしても制御電圧ＶＣと発振周波数の線形性が良くなる。たとえば、Ｖth(ＩＮＮＭＯＳ)＝約０．６Ｖのときに、Ｖth(ＧＧＮＭＯＳ)＝約０．７Ｖにすれば、サブスレッショルド電流はかなり小さくなる（図３からドレイン電圧ＶＤ＝−０．６Ｖで２Ｅ−３Ａ減少））。また、Ｖth(ＩＮＮＭＯＳ)＝約０．８Ｖ以上のときには、サブスレッショルド電流（ＧＧＮＭＯＳトランジスタのドレイン電流）はドレインと基板間のダイオードの順方向電流より小さくなる。尚、ＩＣ内部のＮＭＯＳトランジスタの閾値電圧は回路や目的・用途により変動するが、通常は約０５Ｖ〜約０．６５Ｖ程度であるから、これを基準にしてＧＧＮＭＯＳトランジスタの閾値電圧を設定すれば良い。たとえば、ＧＧＮＭＯＳトランジスタの閾値電圧をこれより約０．１Ｖ〜約０．４Ｖ高くする。 Therefore, in the present invention, the threshold voltage (Vth (GGNMOS)) of the GGNMOS transistor is made higher than the conventional threshold voltage, that is, the threshold voltage (Vth (InNMOS)) of the NMOS transistor inside the IC (that is, Vth (GGNMOS)> Vth (that is,). By InNMOS)), the linearity between the control voltage VC and the oscillation frequency is improved even if the control voltage VC is reduced. For example, when Vth (INNMOS) = about 0.6V and Vth (GGNMOS) = about 0.7V, the subthreshold current becomes considerably small (from FIG. 3 when the drain voltage VD = -0.6V, 2E- 3A decrease)). When Vth (INNMOS) = about 0.8 V or more, the subthreshold current (drain current of the GGNMOS transistor) becomes smaller than the forward current of the diode between the drain and the substrate. The threshold voltage of the NMOS transistor inside the IC varies depending on the circuit, purpose, and application, but it is usually about 05V to about 0.65V, so the threshold voltage of the GGMOS transistor may be set based on this. .. For example, the threshold voltage of the GGNMOS transistor is increased by about 0.1V to about 0.4V.

図６は、本発明を適用した結果（効果）を示す図で、ＧＧＮＭＯＳトランジスタの閾値電圧をＩＣ内部のＮＭＯＳトランジスタの閾値電圧（約０．６Ｖ）より高く（約０．８Ｖ）したときのバイアス電圧Ｖbiasと制御電圧ＶＣの関係を示す図である。発振振幅（ＭＡＸ）電圧Ｖｍは約０．６Ｖである。制御電圧ＶＣが０Ｖに近づいても、バイアス電圧Ｖbiasと制御電圧ＶＣの線形性を維持し、破線で示す理想特性に近くなっていることが分かる。すなわち、本発明による電圧制御発振器の周波数可変特性で、Ｘ１、Ｘ２の発振振幅が約０．６Ｖ以下であればほぼ理想の特性を得ることができる。このように、静電気保護用ＮＭＯＳトランジスタの閾値電圧をＩＣ回路内部で使用されるＮＭＯＳトランジスタの閾値電圧より高くすることによって、制御電圧ＶＣとバイアス電圧Ｖbiasと制御電圧ＶＣの線形性を維持でき、さらに制御電圧ＶＣと発振周波数の線形性を改善することができる。 FIG. 6 is a diagram showing the result (effect) of applying the present invention, and is a bias when the threshold voltage of the GGMOS transistor is higher (about 0.8V) than the threshold voltage (about 0.6V) of the NMOS transistor inside the IC. It is a figure which shows the relationship between the voltage V bias and the control voltage VC. The oscillation amplitude (MAX) voltage Vm is about 0.6V. It can be seen that even when the control voltage VC approaches 0V, the linearity of the bias voltage Vbias and the control voltage VC is maintained, and the characteristics are close to the ideal characteristics shown by the broken line. That is, in the frequency variable characteristics of the voltage controlled oscillator according to the present invention, if the oscillation amplitudes of X1 and X2 are about 0.6 V or less, almost ideal characteristics can be obtained. In this way, by making the threshold voltage of the IPsec transistor for electrostatic protection higher than the threshold voltage of the NMOS transistor used inside the IC circuit, the linearity of the control voltage VC, the bias voltage Vbias, and the control voltage VC can be maintained, and further. The linearity of the control voltage VC and the oscillation frequency can be improved.

また、別の角度からとらえれば、本発明は，電圧制御発振回路用集積回路（ＩＣ）において、静電気保護用ＮＭＯＳトランジスタ（ＧＧＮＭＯＳ）にＩＣ内のＮＭＯＳ閾値電圧（約０．６Ｖ）以上の負電圧が印加されたときに、ＧＧＮＭＯＳトランジスタのＭＯＳ動作によるドレイン電流がドレインと基板間のダイオードの順方向電流より小さくなるように、ＧＧＮＭＯＳトランジスタの閾値電圧を高くすることにより、制御電圧ＶＣとバイアス電圧Ｖbiasと制御電圧ＶＣの線形性が維持され、さらに制御電圧ＶＣと発振周波数の線形性を改善することができる。図３によれば、Ｃで示されるＭＯＳ電流がＤで示されるダイオード電流よりも小さくなるようにすれば良いので、ＧＧＮＭＯＳトランジスタの閾値電圧を約０．７Ｖ〜０．８Ｖ以上にすれば良い。一般には、ダイオードの順方向電圧よりＧＧＮＭＯＳトランジスタの閾値電圧を高くすれば良い。図３では、ダイオードの順方向電圧は約０．７Ｖであるから、ＧＧＮＭＯＳトランジスタの閾値電圧を約０．７Ｖを越える電圧とすれば良い。 From another angle, the present invention presents a voltage-controlled oscillating circuit integrated circuit (IC) with a negative voltage equal to or higher than the NMOS threshold voltage (about 0.6V) in the IC on the electrostatic protection NMOS transistor (GGNMOS). By increasing the threshold voltage of the GGNMOS transistor so that the drain current due to the MOS operation of the GGNMOS transistor becomes smaller than the forward current of the diode between the drain and the substrate when is applied, the control voltage VC and the bias voltage Vbias And the linearity of the control voltage VC is maintained, and the linearity of the control voltage VC and the oscillation frequency can be further improved. According to FIG. 3, since the MOS current indicated by C may be smaller than the diode current indicated by D, the threshold voltage of the GGNMOS transistor may be set to about 0.7V to 0.8V or more. Generally, the threshold voltage of the GGNMOS transistor may be higher than the forward voltage of the diode. In FIG. 3, since the forward voltage of the diode is about 0.7V, the threshold voltage of the GGNMOS transistor may be set to a voltage exceeding about 0.7V.

次に、ＧＧＮＭＯＳトランジスタの閾値電圧を高くする方法を提供する。ＧＧＮＭＯＳトランジスタの閾値電圧を高くするには、ＧＧＮＭＯＳトランジスタを形成している基板濃度を上げれば良い。ＮＭＯＳトランジスタはＰ型基板またはＰウエルの表面上に作成される。すなわち、Ｐ型基板またはＰウエルの表面近傍のＰ型不純物濃度を上げる。その方法として、ＧＧＮＭＯＳトランジスタが形成される基板表面近傍にホウ素（Ｂ）等のＰ型不純物イオンのイオン注入を行なう。ＩＣ内部回路に使用されるＮＭＯＳトランジスタ（閾値電圧：約０．６Ｖ）を形成するときも通常はホウ素（Ｂ）等のＰ型不純物イオンのイオン注入を行ない閾値電圧を調整する。
本発明のＧＧＮＭＯＳトランジスタでは、このＩＣ内部回路に使用される（内部）ＮＭＯＳトランジスタの閾値電圧（約０．６Ｖ）をさらに上げるので、ＧＧＮＭＯＳトランジスタ を形成する領域だけにイオン注入を行なう必要がある。すなわち、内部ＮＭＯＳトランジスタの領域はフォトレジストでマスキング（被覆）して、ＧＧＮＭＯＳトランジスタ領域を窓開けした状態でイオン注入を行なうことになり、マスク工程およびイオン注入工程が追加されるので、プロセスが増加し製品（ＩＣ）のコストアップとなる。 Next, a method of increasing the threshold voltage of the GGNMOS transistor is provided. In order to increase the threshold voltage of the GGNMOS transistor, the density of the substrate forming the GGNMOS transistor may be increased. MOSFET transistors are made on the surface of a P-type substrate or P-well. That is, the concentration of P-type impurities near the surface of the P-type substrate or P-well is increased. As a method for this, ion implantation of P-type impurity ions such as boron (B) is performed near the surface of the substrate on which the GGNMOS transistor is formed. When forming an NMOS transistor (threshold voltage: about 0.6 V) used in an IC internal circuit, ion implantation of P-type impurity ions such as boron (B) is usually performed to adjust the threshold voltage.
In the GGMOS transistor of the present invention, since the threshold voltage (about 0.6V) of the (internal) NMOS transistor used in the IC internal circuit is further increased, it is necessary to implant ions only in the region where the GGMOS transistor is formed. That is, the region of the internal NMOS transistor is masked (coated) with a photoresist, and the ion implantation is performed with the GGNMOS transistor region opened, and the masking step and the ion implantation step are added, so that the process is increased. The cost of the product (IC) will increase.

そこで、本発明では、プロセスを増加させない方法を提案する。ＩＣ内部回路にはＰＭＯＳトランジスタも使用するが、ＰＭＯＳトランジスタの閾値電圧を調整するときにホウ素（Ｂ）等のＰ型不純物イオンを行なう場合がある。（たとえば、ＰＭＯＳトランジスタの形成領域の基板またはＮウエルの表面不純物濃度が高い場合である。）この時ＰＭＯＳトランジスタの領域を窓開けする（ＰＭＯＳトランジスタ窓開け工程（マスクまたはフォトリソ工程とも言う）が、この工程時にＧＧＮＭＯＳトランジスタ領域も窓開けしておく。このＰＭＯＳトランジスタフォトリソ工程の後のＰ型イオン注入工程において、ＰＭＯＳトランジスタ領域だけでなくＧＧＮＭＯＳトランジスタ領域にもホウ素（Ｂ）等のＰ型不純物イオンを同時に行なうことによって、ＧＧＮＭＯＳトランジスタ領域の基板表面のＰ型不純物濃度を上げることができるので、ＧＧＮＭＯＳトランジスタの閾値電圧を上げることができる。このプロセスは、マスク工程もイオン注入工程等のプロセスは何ら増大しないので、製品（ＩＣ）のコストアップとはならない。このようなＰＭＯＳトランジスタの閾値電圧調整用の工程によるＰＭＯＳトランジスタの閾値電圧の調整は約０．１Ｖ〜約０．４Ｖであるから、ＮＭＯＳトランジスタの閾値電圧も約０．１Ｖ〜約０．４Ｖ上がるので、本発明のＮＭＯＳトランジスタの閾値電圧増大によって制御電圧ＶＣとバイアス電圧Ｖbiasの線形性を維持でき、さらに制御電圧ＶＣと発振周波数の線形性を改善することができる。 Therefore, the present invention proposes a method that does not increase the process. A epitaxial transistor is also used in the IC internal circuit, but P-type impurity ions such as boron (B) may be generated when adjusting the threshold voltage of the epitaxial transistor. (For example, when the surface impurity concentration of the substrate or N-well in the region where the epitaxial transistor is formed is high.) At this time, the region of the epitaxial transistor is opened (also referred to as a mask or photolithography step). In this step, the window of the GGNMOS transistor region is also opened. In the P-type ion injection step after this epitaxial transistor photolithography step, P-type impurity ions such as boron (B) are applied not only to the epitaxial transistor region but also to the GGNMOS transistor region. By performing this process at the same time, the concentration of P-type impurities on the substrate surface in the GGNMOS transistor region can be increased, so that the threshold voltage of the GGNMOS transistor can be increased. This process increases the masking process and the ion injection process. Therefore, the cost of the product (IC) is not increased. Since the adjustment of the threshold voltage of the epitaxial transistor by the step for adjusting the threshold voltage of the epitaxial transistor is about 0.1V to about 0.4V, the NMOS transistor is not used. Since the threshold voltage of No. Can be improved.

以上詳細に説明した様に、電圧制御圧電素子発振器に使用される静電気保護素子であるＧＧＮＭＯＳトランジスタの閾値電圧を高くすることにより、制御電圧ＶＣとバイアス電圧Ｖbiasと制御電圧ＶＣの線形性が維持され、に制御電圧ＶＣと発振周波数の線形性を改善することができる。尚、ＧＧＮＭＯＳトランジスタの閾値電圧を上げても対静電気特性には殆ど影響しない。本明細書において、明細書のある部分に記載し説明した内容について記載しなかった他の部分においても矛盾なく適用できることに関しては、当該他の部分に当該内容を適用できることは言うまでもない。さらに、前記実施形態は一例であり、要旨を逸脱しない範囲内で種々変更して実施でき、本発明の権利範囲が前記実施形態に限定されないことも言うまでもない。 As described in detail above, by increasing the threshold voltage of the GGNMOS transistor, which is an electrostatic protection element used in the voltage-controlled piezoelectric element oscillator, the linearity of the control voltage VC, the bias voltage Vbias, and the control voltage VC is maintained. , The linearity of the control voltage VC and the oscillation frequency can be improved. It should be noted that increasing the threshold voltage of the GGNMOS transistor has almost no effect on the antistatic characteristics. It goes without saying that the contents can be applied to the other parts of the present specification without any contradiction as to the fact that the contents described and explained in a certain part of the specification can be applied without contradiction. Furthermore, it goes without saying that the embodiment is an example and can be modified in various ways without departing from the gist, and the scope of rights of the present invention is not limited to the embodiment.

本発明のＧＧＮＭＯＳトランジスタの閾値電圧を高くした静電気保護素子はリーク電流も減少するので、特に低消費電力用ＩＣの入力保護回路にも使用できる。 Since the electrostatic protection element in which the threshold voltage of the GGNMOS transistor of the present invention is increased also reduces the leakage current, it can be used particularly for an input protection circuit of a low power consumption IC.

１・・・水晶振動子、２・・・集積回路（ＩＣ）、３・・・Ｘ１端子、４・・・Ｘ２端子、
５・・・ＶＣ端子、６・・・制御電圧、１０・・・帰還抵抗、１１・・・インバータ、
１２・・・コンデンサ、１３・・・制御抵抗、１４・・・コンデンサ、１５・・・バリキャップダイオード、
１６・・・バリキャップダイオード、１７・・・抵抗、１８・・・抵抗、
１９・・・ＧＧＮＭＯＳトランジスタ、２０・・・ＧＧＮＭＯＳトランジスタ、 1 ... Crystal oscillator, 2 ... Integrated circuit (IC), 3 ... X1 terminal, 4 ... X2 terminal,
5 ... VC terminal, 6 ... control voltage, 10 ... feedback resistor, 11 ... inverter,
12 ... Capacitor, 13 ... Control resistor, 14 ... Capacitor, 15 ... Varicap diode,
16 ... Varicap diode, 17 ... Resistance, 18 ... Resistance,
19 ... GGNMOS transistor, 20 ... GGNMOS transistor,

Claims (6)

電圧可変容量ダイオードと、前記電圧可変容量ダイオードに制御電圧をバイアスする抵抗素子と、圧電素子振動子と接続するための電極と、前記電極に接続された静電気保護用ＮＭＯＳトランジスタを有する電圧制御圧電素子発振器用集積回路（ＩＣ）において、
前記静電気保護用ＮＭＯＳトランジスタの閾値電圧をＩＣ内部に用いられるＮＭＯＳトランジスタの閾値電圧より高くしたことを特徴とする電圧制御圧電素子発振器用ＩＣ。 A voltage-controlled piezoelectric element having a voltage-variable capacitance diode, a resistance element that biases the control voltage to the voltage-variable capacitance diode, an electrode for connecting to the piezoelectric element transducer, and an electrostatic protection NMOS transistor connected to the electrode. In an integrated circuit (IC) for an oscillator
An IC for a voltage-controlled piezoelectric element oscillator, wherein the threshold voltage of the MOSFET for electrostatic protection is made higher than the threshold voltage of the NMOS transistor used inside the IC. ＩＣ内部に用いられる前記ＮＭＯＳトランジスタの閾値電圧がＹＶであるとき、前記静電気保護用ＮＭＯＳトランジスタの閾値電圧を（Ｙ＋０．１）Ｖ以上にすることを特徴とする、請求項１に記載の電圧制御圧電素子発振器用ＩＣ。 The voltage control according to claim 1, wherein when the threshold voltage of the NMOS transistor used inside the IC is YV, the threshold voltage of the MOSFET for electrostatic protection is set to (Y + 0.1) V or more. IC for piezoelectric element oscillator. 電圧可変容量ダイオードと、前記電圧可変容量ダイオードに制御電圧をバイアスする抵抗素子と、圧電素子振動子と接続するための電極と、前記電極に接続された静電気保護用ＮＭＯＳトランジスタを有する電圧制御圧電素子発振器用集積回路（ＩＣ）において、
静電気保護用ＮＭＯＳトランジスタのドレインに０．６Ｖ以上の負電圧が印加されたときに、ＭＯＳ動作によるドレイン電流がドレインと基板間のダイオード電流よりも小さくなるように、
前記静電気保護用ＮＭＯＳトランジスタの閾値電圧を高くしたことを特徴とする電圧制御圧電素子発振器用ＩＣ。 A voltage-controlled piezoelectric element having a voltage-variable capacitance diode, a resistance element that biases the control voltage to the voltage-variable capacitance diode, an electrode for connecting to the piezoelectric element transducer, and an electrostatic protection NMOS transistor connected to the electrode. In an integrated circuit (IC) for an oscillator
When a negative voltage of 0.6V or more is applied to the drain of the MOSFET for electrostatic protection, the drain current due to MOS operation is smaller than the diode current between the drain and the substrate.
An IC for a voltage-controlled piezoelectric element oscillator, characterized in that the threshold voltage of the electrostatic protection NMOS transistor is increased. 前記静電気保護用ＮＭＯＳトランジスタの閾値電圧は、ドレインと基板間のダイオードの順方向電圧より高いことを特徴とする、請求項３に記載の電圧制御圧電素子発振器用ＩＣ。 The IC for a voltage-controlled piezoelectric element oscillator according to claim 3, wherein the threshold voltage of the electrostatic protection NMOS transistor is higher than the forward voltage of the diode between the drain and the substrate. 電圧可変容量ダイオードと、前記電圧可変容量ダイオードに制御電圧をバイアスする抵抗素子と、圧電素子振動子と接続するための電極と、前記電極に接続された静電気保護用ＮＭＯＳトランジスタを有する電圧制御圧電素子発振器用集積回路（ＩＣ）の製造方法であって、
前記ＩＣ内部に用いられるＰＭＯＳトランジスタの領域に打ち込むＰ型不純物イオンのイオン注入時に、前記静電気保護用ＮＭＯＳトランジスタを形成する領域にも同種で同量のＰ型不純物イオンのイオン注入を行ない、前記静電気保護用ＮＭＯＳトランジスタの閾値電圧をＩＣ内部に用いられるＮＭＯＳトランジスタの閾値電圧より高くしたことを特徴とする電圧制御圧電素子発振器用ＩＣの製造方法。 A voltage-controlled piezoelectric element having a voltage-variable capacitance diode, a resistance element that biases the control voltage to the voltage-variable capacitance diode, an electrode for connecting to the piezoelectric element transducer, and an electrostatic protection NMOS transistor connected to the electrode. A method for manufacturing an integrated circuit (IC) for an oscillator.
At the time of ion injection of P-type impurity ions to be driven into the region of the MOSFET transistor used inside the IC, the same type and the same amount of P-type impurity ions are injected into the region forming the electrostatic protection NMOS transistor to generate the static electricity. A method for manufacturing a voltage-controlled piezoelectric element oscillator IC, characterized in that the threshold voltage of the protective NMOS transistor is made higher than the threshold voltage of the NMOS transistor used inside the IC. 前記イオン注入工程の前に、前記ＩＣ内部に用いられるＰＭＯＳトランジスタの領域および前記静電気保護用ＮＭＯＳトランジスタを形成する領域を同時に窓開けするフォトリソ工程を行なうことを特徴とする電圧制御圧電素子発振器用ＩＣの製造方法。 Prior to the ion implantation step, an IC for a voltage-controlled piezoelectric element oscillator is characterized in that a photolithography step is performed at the same time to open a window in a region of a MOSFET transistor used inside the IC and a region of forming the electrostatic protection NMOS transistor. Manufacturing method.
JP2020007182A 2020-01-20 2020-01-20 IC for voltage control piezoelectric element oscillator Pending JP2021114722A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2020007182A JP2021114722A (en) 2020-01-20 2020-01-20 IC for voltage control piezoelectric element oscillator
PCT/JP2021/001736 WO2021149693A1 (en) 2020-01-20 2021-01-19 Ic for voltage-controlled piezoelectric element oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2020007182A JP2021114722A (en) 2020-01-20 2020-01-20 IC for voltage control piezoelectric element oscillator

Publications (1)

Publication Number Publication Date
JP2021114722A true JP2021114722A (en) 2021-08-05

Family

ID=76992983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020007182A Pending JP2021114722A (en) 2020-01-20 2020-01-20 IC for voltage control piezoelectric element oscillator

Country Status (2)

Country Link
JP (1) JP2021114722A (en)
WO (1) WO2021149693A1 (en)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3371769B2 (en) * 1997-09-01 2003-01-27 セイコーエプソン株式会社 Voltage controlled piezoelectric oscillation IC
JP2001102867A (en) * 1999-07-23 2001-04-13 Interchip Kk Oscillation control circuit
JP2002026660A (en) * 2000-07-11 2002-01-25 Citizen Watch Co Ltd Voltage controlled quartz oscillator
JP2009038189A (en) * 2007-08-01 2009-02-19 Sharp Corp Semiconductor device, voltage supply system, and manufacturing method of semiconductor device
JP2009060081A (en) * 2007-08-06 2009-03-19 Seiko Instruments Inc Semiconductor device
JP2012039348A (en) * 2010-08-06 2012-02-23 Seiko Epson Corp Semiconductor integrated circuit device
WO2013011911A1 (en) * 2011-07-19 2013-01-24 シャープ株式会社 Method for manufacturing element substrate

Also Published As

Publication number Publication date
WO2021149693A1 (en) 2021-07-29

Similar Documents

Publication Publication Date Title
US9490759B2 (en) Neutralization of parasitic capacitance using MOS device
US7279998B2 (en) Voltage-controlled oscillator
JPS6033314B2 (en) Substrate bias voltage generation circuit
TWI746823B (en) Reference voltage generating device
US7705571B2 (en) Reverse-connect protection circuit with a low voltage drop
US5539327A (en) Protection circuit which prevents avalanche breakdown in a fet by having a floating substrate and a voltage controlled gate
TWI654757B (en) Compensation of temperature effects in semiconductor device structures
US10585447B1 (en) Voltage generator
EP2419995A1 (en) Resistorless feedback biasing for ultra low power crystal oscillator
JP2004086750A (en) Band gap circuit
WO2021149693A1 (en) Ic for voltage-controlled piezoelectric element oscillator
US3444397A (en) Voltage adjustable breakdown diode employing metal oxide silicon field effect transistor
US9236466B1 (en) Analog circuits having improved insulated gate transistors, and methods therefor
US4383224A (en) NMOS Crystal oscillator
JPS6153860B2 (en)
US20090201081A1 (en) Method and Apparatus for MOSFET Drain-Source Leakage Reduction
TWI791707B (en) Reference voltage generator
EP0657994A1 (en) Oscillation circuit oscillating even on low power voltage
JP4643838B2 (en) Integrated circuit for voltage controlled oscillator
US20230155498A1 (en) Current source circuit
JP4360830B2 (en) Semiconductor reference voltage generator
US20090201075A1 (en) Method and Apparatus for MOSFET Drain-Source Leakage Reduction
JP4391862B2 (en) Temperature compensated crystal oscillator
KR0165384B1 (en) Electrostatic protection structure for semiconductor device
Jain et al. Novel Hybrid SiGe-Silicon 5V pLDMOS on 28nm HKMG technology