JP2012039348A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extend an adjustable oscillation frequency range by reducing a parasitic capacitance and to prevent an oscillation frequency from changing depending on an externally-supplied power supply voltage value in an semiconductor integrated circuit device with an oscillator connected between a first pad and a second pad for performing oscillating operation.SOLUTION: The device includes: a voltage regulator to which the first power supply potential or the second power supply potential is supplied from a third pad or a fourth pad respectively to output a regulated power supply potential; an inverting amplifier operates with the regulated power supply potential supplied; two diodes having anodes connected to the first or second pad and cathodes connected to an output terminal of the voltage regulator through a resistor; two diodes having cathodes connected to the first or second pad and anodes connected to the fourth pad; a transistor connected between the third pad and the fourth pad; and a transistor connected between the resistor and the fourth pad.

Description

  The present invention relates to a semiconductor integrated circuit device having a built-in oscillation circuit connected to a resonator such as a crystal resonator to perform an oscillation operation.

  2. Description of the Related Art Generally, in an apparatus that handles a digital signal, a semiconductor integrated circuit device that incorporates an oscillation circuit that is connected to an oscillator such as a crystal oscillator and performs an oscillation operation is used to generate a clock signal. The clock signal generated by the oscillation circuit is supplied to another circuit that operates in synchronization with the clock signal.

  FIG. 5 is a diagram showing a configuration example of a conventional semiconductor integrated circuit device incorporating an oscillation circuit. In this semiconductor integrated circuit device, the vibrator 22 is connected between the pad P1 and the pad P2 to perform an oscillation operation.

As shown in FIG. 5, the oscillation circuit inverts and amplifies the signal input to the input terminal (node N1) and outputs the amplified signal from the output terminal (node N2), the pad P1 and the node N1. A resistor R1 connected between the node N1, a resistor R2 connected between the pad P2 and the node N2, a variable capacitor C1 connected between the node N1 and the power supply potential V _SS (ground potential), and a variable capacitance C2 connected between the node N2 and the power supply potential V _SS.

  The inverting amplifier circuit 21 includes an inverter constituted by a P-channel MOS transistor QP1 and an N-channel MOS transistor QN1, and a feedback resistor R3 connected between the node N2 and the node N1. Is inverted and amplified and output from the node N2 to the pad P2. The feedback resistor R3 determines the DC bias level of the transistors QP1 and QN1 and obtains an appropriate amplification function.

The vibrator 22 is connected between the pad P1 and the pad P2. The oscillation circuit oscillates when the power supply potential V _DD and the power supply potential _VSS are supplied. The oscillation frequency is adjusted by changing the capacitance values of the variable capacitors C1 and C2.

Here, in order to protect the internal circuit of the semiconductor integrated circuit device from static electricity applied to the pad P1, a GCD (gate controlled diode) is used as an electrostatic protection element between the pad P1 and the pad P4 (power supply potential V _SS ). Or N-channel MOS transistor QN2 called GGNMOS (gate grounded nMOS). Similarly, in order to protect the internal circuit from static electricity applied to the pad P2, an N-channel MOS transistor QN3 is connected between the pad P2 and the pad P4, and the internal circuit is protected from static electricity applied to the pad P3. N channel MOS transistor QN4 is connected between pad P3 and pad P4.

  Each of the transistors QN2 to QN4 includes a first terminal (source / drain) connected to each one of the pads P1 to P3, and a gate and a second terminal (drain / source) connected to the pad P4. When the gate potential becomes higher than the threshold voltage with respect to the potential of the first terminal, a forward current flows from the second terminal toward the first terminal, and the potential of the first terminal Is higher than the breakdown voltage with respect to the potential of the second terminal, a reverse current flows from the first terminal toward the second terminal.

  For example, when positive static electricity is applied to the pad P1 with respect to the pad P4, a reverse current flows from the first terminal to the second terminal of the transistor QN2. In this case, in order to prevent the electrostatic protection transistor from being destroyed, it is necessary to sufficiently increase the distance between the gate electrode and the contact of the first terminal (source / drain) in the electrostatic protection transistor. . As a result, the area of the source / drain region is increased, the parasitic capacitance formed between the source / drain region and the semiconductor substrate is increased, and the capacitance between the terminals of the electrostatic protection transistor is increased. And there is a disadvantage that the range of the oscillation frequency that can be adjusted is narrowed by changing the capacitance value of C2 and C2.

As a related technique, FIG. 1 of Patent Document 1 shows that in an oscillation circuit having an external crystal resonator, the inverter is protected against a sudden rise in surge voltage entering from a crystal input terminal, and the oscillation circuit is destroyed. A configuration for preventing this is described. The oscillation circuit 1 is provided with a protection circuit 10 that prevents the inverter 5 from being destroyed by a surge voltage entering from the crystal input terminal 2 on a signal path extending from the crystal input terminal 2 to the input terminal of the inverter 5. An input resistor 14 having a resistance value of 50Ω or more is provided on the signal path between the inverter 10 and the inverter 5. In the protection circuit 10, a diode 8 is connected between the signal path and the negative power supply terminal (V _SS ), and a diode 9 is connected between the signal path and the positive power supply terminal (V _DD ).

Japanese Patent Laying-Open No. 2007-243457 (first page, FIG. 1)

  Since the capacitance between the terminals of the diodes 8 and 9 described in Patent Document 1 is smaller than the capacitance between the terminals of the electrostatic protection transistor, Patent Document 1 describes the oscillation circuit shown in FIG. 5 instead of the electrostatic protection transistor. By using the described diodes 8 and 9, the range of the oscillation frequency that can be adjusted by the variable capacitors C1 and C2 can be widened.

However, as shown in FIG. 1 of Patent Document 1, the diodes 8 and 9 are connected between the power supply potential V _DD and the power supply potential _VSS, and the capacitance between the terminals of the diodes 8 and 9 is external. The oscillation frequency varies depending on the value of the power supply voltage supplied from the outside because it varies depending on the value of the power supply voltage (V _DD −V _SS ) (eg, 1.6 V to 5.5 V) supplied from the outside. There is.

  In order to solve the above problems, a semiconductor integrated circuit device according to one aspect of the present invention is a semiconductor integrated circuit device that performs an oscillation operation by connecting a vibrator between a first pad and a second pad. A voltage regulator that supplies the first power supply potential from the third pad and the second power supply potential from the fourth pad, stabilizes the first power supply potential, and outputs a stabilized power supply potential. And an inverting amplifier circuit that is supplied with the stabilized power supply potential and the second power supply potential, and inverts and amplifies a signal input from the first pad to the input terminal and outputs an amplified signal from the output terminal to the second pad. A first resistor connected between the first pad and the input terminal of the inverting amplifier circuit, a second resistor connected between the second pad and the output terminal of the inverting amplifier circuit, and a voltage First end connected to the output terminal of the regulator A first diode having an anode connected to the first pad, a cathode connected to the second terminal of the third resistor, and a cathode connected to the first pad And a second diode having an anode connected to the fourth pad, a third diode having an anode connected to the second pad and a cathode connected to the second terminal of the third resistor And a fourth diode having a cathode connected to the second pad and an anode connected to the fourth pad, and connected between the third pad and the fourth pad, and between them A first transistor that conducts a current when a voltage exceeding a predetermined value is applied, and is connected between the second terminal of the third resistor and the fourth pad, and a predetermined value is set between them. Current is applied when a voltage exceeding Comprising a second transistor.

  Here, the first transistor is an N-channel MOS transistor having a source / drain connected to the third pad and a gate and drain / source connected to the fourth pad, and the second transistor is An N-channel MOS transistor having a source / drain connected to the second terminal of the third resistor and a gate and drain / source connected to the fourth pad may be used.

  Alternatively, the first transistor is an NPN bipolar transistor having an emitter / collector connected to the third pad and a base and collector / emitter connected to the fourth pad, and the second transistor is Or an NPN bipolar transistor having an emitter / collector connected to the second terminal of the resistor 3 and a base and collector / emitter connected to the fourth pad. When a bipolar transistor is used as the electrostatic protection transistor, unlike the GCD or GGNMOS, it is not necessary to form a gate electrode, so that the width of the base region can be made smaller, and the snapback characteristics than the GCD or GGNMOS. Can be improved.

  In the layout of the semiconductor integrated circuit device, the first pad, the second transistor, and the second pad are arranged at a predetermined interval along one side of the semiconductor substrate. The first and second diodes may be disposed between the two transistors, and the third and fourth diodes may be disposed between the second transistor and the second pad. According to such a layout, when negative static electricity is applied to the first pad or the second pad with reference to the semiconductor substrate, the negative charge passes through the second or fourth diode in a short wiring path. When positive static electricity is applied to the first pad or the second pad with reference to the semiconductor substrate, positive charges are passed through the first or third diode and the second transistor. Since the semiconductor substrate passes through a short wiring path, the reverse current of the diode can be reduced and the internal circuit of the semiconductor integrated circuit device can be safely protected.

  According to one aspect of the present invention, in a semiconductor integrated circuit device that performs an oscillating operation with a vibrator connected between a first pad and a second pad, it is applied to the first or second pad. In order to protect the internal circuit from static electricity, by providing the third resistor, the first to fourth diodes, and the second transistor, the range of the oscillation frequency that can be adjusted by reducing the parasitic capacitance is widened. In addition, the oscillation frequency can be prevented from changing depending on the value of the power supply voltage supplied from the outside.

1 is a diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. The figure which shows the structure of the semiconductor integrated circuit device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows a part of semiconductor integrated circuit device based on the 2nd Embodiment of this invention. FIG. 5 is a plan view showing a layout of a part of a semiconductor integrated circuit device according to a second embodiment. FIG. 10 is a diagram illustrating a configuration example of a conventional semiconductor integrated circuit device including an oscillation circuit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and the overlapping description is abbreviate | omitted.
FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit device according to the first embodiment of the present invention. As shown in FIG. 1, this semiconductor integrated circuit device includes a voltage regulator 10, an oscillation circuit 20, a temperature sensor 30, an A / D converter 40, a control unit 50, and a storage unit 60. The vibrator 22 is connected between the pads (connection terminals to the outside) P1 and P2 to perform an oscillation operation. Further, the pad P3 is supplied first power supply potential _{V DD,} the pad P4 is supplied second power supply potential _{V SS.} In the present embodiment, the power supply potential _{V DD} is 1.6V～5.5V, shall supply potential _{V SS} is a ground potential.

The voltage regulator 10 is supplied with the power supply potential V _DD from the pad P3 and is supplied with the power supply potential V _SS from the pad P4, and stabilizes the power supply potential V _DD based on the reference potential V _REF to stabilize the power supply potential V _REG. And the stabilized power supply potential V _REG is output from the output terminal (node N3).

The voltage regulator 10 amplifies the error between the stabilized power supply potential V _REG and the reference potential V _REF, and receives the amplified signal output from the operational amplifier 11 and outputs the stabilized power supply potential V _REG. A channel MOS transistor QP2 and a bypass capacitor C3 for smoothing the stabilized power supply potential _VREG are included.

The operational amplifier 11 has a non-inverting input terminal to which the stabilized power supply potential V _REG is applied, an inverting input terminal to which the reference potential V _REF is applied, and an output terminal that outputs an amplified signal. Transistor QP2 has a gate connected to the output terminal of operational amplifier 11, a source connected to power supply potential _VDD , and a drain connected to the output terminal (node N3) of voltage regulator 10.

The operational amplifier 11 amplifies the error between the stabilized power supply potential V _REG and the reference potential V _REF, and adjusts the on-resistance of the transistor QP2 so that they match. In order to stabilize the output potential of the transistor QP2, bypass capacitor C3 is connected between the drain and the source potential V _SS of the transistor QP2.

The oscillation circuit 20 performs the oscillation operation stabilized power supply potential _{V REG} and a power supply potential _{V SS} is supplied. The oscillation circuit 20 is connected between an inverting amplifier circuit 21 that inverts and amplifies a signal input to the input terminal (node N1) and outputs an amplified signal from the output terminal (node N2), and between the pad P1 and the node N1. and a resistor R1, between the resistor connected between the pad P2 and the node N2 R2, a variable capacitor C1 connected between the node N1 and the power supply potential V _SS, and the node N2 and the power supply potential V _SS And a variable capacitor C2 connected to. Note that the variable capacitors C1 and C2 may be externally attached to the semiconductor integrated circuit device.

  The inverting amplifier circuit 21 includes an inverter constituted by a P-channel MOS transistor QP1 and an N-channel MOS transistor QN1, and a feedback resistor R3 connected between the node N2 and the node N1. The signal input to (node N1) is inverted and amplified, and the amplified signal is output from the output terminal (node N2) to pad P2.

The transistor QP1 has a gate connected to the node N1, a source connected to the stabilized power supply potential _VREG , and a drain connected to the node N2, and a voltage change of the node N1 with respect to the stabilized power supply potential _VREG . Amplify. Transistor QN1 has a gate connected to the node N1, a drain connected to the node N2, and a source connected to a power supply potential V _SS, amplifies the voltage change of the node N1 with respect to the power supply potential V _SS. The feedback resistor R3 determines the DC bias level of the transistors QP1 and QN1 and obtains an appropriate amplification function.

  The two terminals of the vibrator 22 are connected between the pad P1 and the pad P2 via a wiring pattern formed on a printed wiring board or the like on which the semiconductor integrated circuit device is mounted. The vibrator 22 is a vibrator such as a crystal vibrator or a ceramic vibrator. In particular, in order to generate an oscillation signal having a high frequency of 100 MHz or more, a SAW (surface acoustic wave) resonator is used. The oscillation frequency is adjusted by changing the capacitance values of the variable capacitors C1 and C2. The resistors R1 and R2 are resistors having a small resistance value for protecting the internal circuit of the semiconductor integrated circuit device from static electricity.

  Here, in order to protect the internal circuit from static electricity applied to the pad P1 or P2, in addition to the resistors R1 and R2, the resistor R4, the diodes D1 to D4, and the GCD (gate controlled diode) are used as electrostatic protection elements. Alternatively, an N channel MOS transistor QN5 called GGNMOS (gate grounded nMOS) is provided. In order to protect the internal circuit from static electricity applied to the pad P3, an N-channel MOS transistor QN4 called GCD or GGNMOS is connected as an electrostatic protection element between the pad P3 and the pad P4.

  Resistor R4 has a first terminal connected to the output terminal (node N3) of voltage regulator 10, and a second terminal connected to node N4. The node N4 is a dedicated node for connecting the electrostatic protection element, and is not connected to a pad or an external circuit. The resistors R1, R2, and R4 have a resistance value of about 50Ω to 500Ω, for example.

  In a MOS transistor, which of the two impurity diffusion regions is the source and which is the drain depends on the bias condition. In the present application, one of the two impurity diffusion regions is designated as “first terminal”. ”Or“ source / drain ”, and the other is expressed as“ second terminal ”or“ drain / source ”.

  The transistor QN4 has a first terminal (source / drain) connected to the pad P3, and a gate and a second terminal (drain / source) connected to the pad P4. The transistor QN5 has a first terminal (source / drain) connected to the node N4, and a gate and a second terminal (drain / source) connected to the pad P4. Note that the back gates of the transistors QN4 and QN5 are also connected to the pad P4.

  Each of the transistors QN4 and QN5 causes a current to flow when a voltage exceeding a predetermined value is applied between the first terminal, the gate, and the second terminal. That is, each of the transistors QN4 and QN5 has a forward current from the second terminal toward the first terminal when the potential of the gate and the second terminal becomes higher than the threshold voltage with respect to the potential of the first terminal. When the potential of the first terminal becomes higher than the breakdown voltage with respect to the potential of the gate and the second terminal, a reverse current flows from the first terminal to the second terminal.

  For example, when negative static electricity is applied to the pad P3 with respect to the pad P4, a forward current flows from the second terminal of the transistor QN4 toward the first terminal. On the other hand, when positive static electricity is applied to the pad P3 with respect to the pad P4, a reverse current flows from the first terminal to the second terminal of the transistor QN4.

Diode D1 has an anode connected to pad P1 and a cathode connected to node N4. The diode D2 has a cathode connected to the pad P1 and an anode connected to the pad P4 (power supply potential V _SS ). Diode D3 has an anode connected to pad P2 and a cathode connected to node N4. The diode D4 has a cathode connected to the pad P2 and an anode connected to the pad P4 (power supply potential V _SS ).

  Since the capacitance between the terminals of the diodes D1 and D2 is smaller than the capacitance between the terminals of the electrostatic protection transistor, the diodes D1 and D2 are used instead of the electrostatic protection transistor in order to protect the internal circuit from static electricity applied to the pad P1. By using this, the range of the oscillation frequency that can be adjusted by the variable capacitor C1 can be widened. The diodes D3 and D4 are the same as the diodes D1 and D2.

  Each of the diodes D1 to D4 causes a forward current to flow from the anode toward the cathode when the anode potential becomes higher than the threshold voltage with respect to the cathode potential. For example, when negative static electricity is applied to the pad P1 with respect to the pad P4, a forward current flows from the anode to the cathode of the diode D2, and negative charge is released from the pad P1 to the pad P4.

  On the other hand, when positive static electricity is applied to the pad P1 with respect to the pad P4, a forward current flows from the anode to the cathode of the diode D1. As a result, the potential of the node N4 rises, so that a reverse current flows from the first terminal (source / drain) to the second terminal (drain / source) of the transistor QN5, and the positive current flows from the pad P1 to the pad P4. Loses its charge. When positive static electricity is applied to the pad P1 with the pad P4 as a reference, a slight reverse current flows through the diode D2 at first, but thereafter, most of the current flows due to the snapback characteristics of the transistor QN5. A current flows through the transistor QN5. Therefore, the size of the diodes D1 to D4 may be small.

  Further, when negative static electricity is applied to the pad P1 with respect to the pad P3, a current flows from the pad P3 to the pad P1 via the transistor QN4 and the diode D2, and a negative current flows from the pad P1 to the pad P3. Charge is lost. Here, if the resistor R4 is not provided, a current flows from the pad P3 to the pad P1 via the transistor QP2 and the diode D1, so that the transistor QP2 that is an internal circuit is destroyed.

  On the other hand, when positive static electricity is applied to the pad P1 with respect to the pad P3, a current flows from the pad P1 to the pad P3 via the diode D1 and the transistors QN5 and QN4, and the pad P1 to the pad P3. Positive charge is lost. Here, if the resistor R4 is not provided, a current flows from the pad P1 to the pad P3 via the diode D1 and the transistor QP2, so that the transistor QP2 that is an internal circuit is destroyed.

In the above, the diode D1 and D2 is connected between the power supply voltage _{V SS} of the stabilized power supply potential _{V REG} and the pad P4 of node N4, the value of the regulated supply voltage _(V REG _{-V SS)} is Since the power supply voltage (V _DD −V _SS ) supplied from the outside is constant regardless of the value (1.6 V to 5.5 V), the capacitance between the terminals of the diodes D1 and D2 is also constant. The diodes D3 and D4 are the same as the diodes D1 and D2. Therefore, according to the present embodiment, it is possible to prevent the oscillation frequency of the oscillation circuit 20 from changing depending on the value of the power supply voltage supplied from the outside.

On the other hand, in order to reduce the change of the oscillation frequency due to temperature, a temperature sensor 30 to a storage unit 60 are provided. The temperature sensor 30 detects the temperature in the semiconductor integrated circuit device using a thermistor or the like, and outputs a detection signal representing the detected temperature. The A / D converter 40 converts the analog detection signal output from the temperature sensor 30 into a digital detection signal. Based on the digital detection signal output from the A / D converter 40, the control unit 50 searches the storage unit 60 for capacity data corresponding to the value of the detection signal. The storage unit 60 includes a non-volatile memory such as an E ² PROM (Electrically Erasable Programmable ROM), and a variable set in advance for the value of the detection signal and the value of the detection signal to obtain a constant oscillation frequency. A table in which capacity data representing the states of the capacities C1 and C2 is associated is stored.

  Each of the variable capacitors C1 and C2 includes, for example, a plurality of capacitors and a plurality of switch circuits connected in series to the capacitors. The control unit 50 is read from the storage unit 60. Some of the switch circuits are turned on according to the capacitance data. By performing such control, even if the temperature in the semiconductor integrated circuit device changes, the oscillation frequency of the oscillation circuit 20 can be brought close to a constant value.

Next, a second embodiment of the present invention will be described.
FIG. 2 is a diagram showing a configuration of a semiconductor integrated circuit device according to the second embodiment of the present invention. In the second embodiment, NPN bipolar transistors QB1 and QB2 are used as electrostatic protection elements in place of the N-channel MOS transistors QN4 and QN5 in the first embodiment shown in FIG. The other points are the same as in the first embodiment.

  As shown in FIG. 2, in order to protect the internal circuit from static electricity applied to the pad P1 or P2, in addition to the resistors R1 and R2, the resistor R4, the diodes D1 to D4, and the NPN bipolar are used as electrostatic protection elements. Transistor QB2 is provided. In order to protect the internal circuit from static electricity applied to the pad P3, an NPN bipolar transistor QB1 is connected as an electrostatic protection element between the pad P3 and the pad P4.

  Transistor QB1 has an emitter connected to pad P3, and a base and a collector connected to pad P4. Transistor QB2 has an emitter connected to node N4, and a base and a collector connected to pad P4.

  Each of the transistors QB1 and QB2 conducts a current when a voltage exceeding a predetermined value is applied between the emitter, the base, and the collector. That is, each of the transistors QB1 and QB2 causes a forward current to flow from the base and the collector toward the emitter when the base and collector potentials are higher than the threshold voltage with respect to the emitter potential, and the emitter potential is increased between the base and collector. When the breakdown voltage is higher than the breakdown voltage, a reverse current flows from the emitter toward the base and collector.

  For example, when negative static electricity is applied to the pad P3 with respect to the pad P4, a forward current flows from the base and collector of the transistor QB1 toward the emitter. On the other hand, when positive static electricity is applied to the pad P3 with respect to the pad P4, a reverse current flows from the emitter of the transistor QB1 toward the base and collector.

  Thus, when a bipolar transistor is used as the electrostatic protection transistor, it is not necessary to form a gate electrode unlike GCD or GGNMOS. Therefore, the width of the base region can be reduced, and the snapback characteristics can be improved as compared with GCD or GGNMOS.

  Each of the diodes D1 to D4 causes a forward current to flow from the anode toward the cathode when the anode potential becomes higher than the threshold voltage with respect to the cathode potential. For example, when negative static electricity is applied to the pad P1 with respect to the pad P4, a forward current flows from the anode to the cathode of the diode D2, and negative charge is released from the pad P1 to the pad P4.

  On the other hand, when positive static electricity is applied to the pad P1 with respect to the pad P4, a forward current flows from the anode to the cathode of the diode D1. As a result, the potential of the node N4 rises, so that a reverse current flows from the emitter of the transistor QB2 toward the base and collector, and positive charge is released from the pad P1 to the pad P4. When positive static electricity is applied to the pad P1 with the pad P4 as a reference, a slight reverse current flows through the diode D2 at first, but thereafter, most of the current flows due to the snapback characteristics of the transistor QB2. A current flows through the transistor QB2. Therefore, the size of the diodes D1 to D4 may be small.

  Further, when negative static electricity is applied to the pad P1 with respect to the pad P3, a current flows from the pad P3 to the pad P1 via the transistor QB1 and the diode D2, and a negative current flows from the pad P1 to the pad P3. Charge is lost. Here, if the resistor R4 is not provided, a current flows from the pad P3 to the pad P1 via the transistor QP2 and the diode D1, so that the transistor QP2 that is an internal circuit is destroyed.

  On the other hand, when positive static electricity is applied to the pad P1 with respect to the pad P3, a current flows from the pad P1 to the pad P3 via the diode D1 and the transistors QB2 and QB1, and the pad P1 to the pad P3. Positive charge is lost. Here, if the resistor R4 is not provided, a current flows from the pad P1 to the pad P3 via the diode D1 and the transistor QP2, so that the transistor QP2 that is an internal circuit is destroyed.

  FIG. 3 is a cross-sectional view showing a part of a semiconductor integrated circuit device according to the second embodiment of the present invention. As shown in FIG. 3, an N well 110 is formed in a P type semiconductor substrate 100. In the N-well 110, a P-type impurity diffusion region 111 serving as an anode of the diode D1 and an N-type impurity diffusion region (contact) 112 for connection to the N-well 110 serving as a cathode of the diode D1 and 113 is formed. Impurity diffusion region 111 is electrically connected to pad P1, and contacts 112 and 113 are electrically connected from node N4 to node N3 via resistor 4.

  In addition, in the P-type semiconductor substrate 100, an N-type impurity diffusion region 121 that functions as a cathode of the diode D2 and a P-type semiconductor substrate 100 that functions as an anode of the diode D2 are connected to form a P-type semiconductor substrate 100. Impurity diffusion regions (contacts) 122 and 123 are formed. The impurity diffusion region 121 is electrically connected to the pad P1, and the contacts 122 and 123 are electrically connected to the pad P4.

  Further, in the P-type semiconductor substrate 100, an N-type impurity diffusion region 131 that functions as an emitter of the NPN bipolar transistor QB2 and N-type impurity diffusion regions 132 and 133 that function as a collector of the transistor QB2 are formed. . In the semiconductor substrate 100 electrically connected to the pad P4 by the contacts 122 and 123, etc., the peripheral region 134 of the impurity diffusion regions 131 to 133 serves as the base of the transistor QB2. Impurity diffusion region 131 is electrically connected from node N4 to node N3 via resistor 4, and impurity diffusion regions 132 and 133 are electrically connected to pad P4.

  In the NPN bipolar transistor, the emitter and the collector are both constituted by an N-type impurity diffusion region, so that the emitter and the collector may be connected in reverse. In that case, in FIG. 2, the collector of the transistor QB1 is connected to the pad P3, and the base and emitter are connected to the pad P4. The collector of transistor QB2 is connected to node N4, and the base and emitter are connected to pad P4.

  FIG. 4 is a plan view showing a partial layout of a semiconductor integrated circuit device according to the second embodiment of the present invention. A pad P1, a transistor QB2, and a pad P2 are arranged at a predetermined interval from the left side of FIG. 4 along one side 100a of the semiconductor substrate 100, and diodes D1 and D2 are disposed between the pad P1 and the transistor QB2. Are arranged, and diodes D3 and D4 are arranged between the transistor QB2 and the pad P2.

  The pad P1 is connected to the anode of the diode D1 and the cathode of the diode D2, and the pad P2 is connected to the anode of the diode D3 and the cathode of the diode D4. The cathodes of the diodes D1 and D3 are connected to the emitter of the transistor QB2, and the anodes of the diodes D2 and D4 are connected to the pad P4 (not shown). The base and collector of the transistor QB2 are connected to the pad P4.

  Furthermore, a variable capacitor C1, an inverting amplifier circuit 21, and a variable capacitor C2 are arranged in parallel with the pads P1 and P2. The pad P1 is connected to the input terminal of the variable capacitor C1 and the inverting amplifier circuit 21 through the resistor R1, and the pad P2 is connected to the input terminal of the variable capacitor C2 and the inverting amplifier circuit 21 through the resistor R2. . The emitter of the transistor QB2 is connected to the stabilized power supply potential supplied to the inverting amplifier circuit 21 via the resistor R4.

  The layout shown in FIG. 4 shortens the wiring path from the pads P1 and P2 to the diodes D2 and D4, and shortens the wiring path from the pads P1 and P2 to the transistor QB2 via the diodes D1 and D3, respectively. It has been taken into account. According to such a layout, when negative static electricity is applied to the pad P1 or P2 with respect to the semiconductor substrate 100, negative charges are released to the semiconductor substrate 100 through a short wiring path via the diode D2 or D4. In addition, the amount of charge passing through the diode D1 or D3 in the reverse direction and the amount of charge passing through the internal circuit of the semiconductor integrated circuit device can be minimized, and the diodes D1, D3 and the internal circuit can be safely protected. Further, when positive static electricity is applied to the pad P1 or P2 with respect to the semiconductor substrate 100, positive charge is released to the semiconductor substrate 100 through a short wiring path via the diode D1 or D3 and the transistor QB2, and thus the diode D2 Alternatively, the amount of charge passing through D4 in the reverse direction and the amount of charge passing through the internal circuit of the semiconductor integrated circuit device can be minimized, and the diodes D2, D4 and the internal circuit can be safely protected.

  The layout shown in FIG. 4 can also be applied to the first embodiment. In that case, transistor QN5 shown in FIG. 1 is arranged at the position of transistor QB2 shown in FIG.

  10 voltage regulators, 11 operational amplifiers, 20 oscillation circuits, 21 inverting amplifier circuits, 22 transducers, 30 temperature sensors, 40 A / D converters, 50 control units, 60 storage units, P1-P4 pads, R1-R4 resistors, C1, C2 variable capacitance, C3 bypass capacitor, QP1-QP2 P-channel MOS transistor, QN1-QN5 N-channel MOS transistor, QB1-QB2 NPN bipolar transistor, D1-D4 diode

Claims (4)

A semiconductor integrated circuit device that performs an oscillation operation by connecting a vibrator between a first pad and a second pad,
A voltage regulator that supplies a first power supply potential from a third pad and a second power supply potential from a fourth pad, stabilizes the first power supply potential, and outputs a stabilized power supply potential;
Inverted amplification that is supplied with the stabilized power supply potential and the second power supply potential, and inverts and amplifies a signal input from the first pad to the input terminal and outputs an amplified signal from the output terminal to the second pad. Circuit,
A first resistor connected between the first pad and an input terminal of the inverting amplifier circuit;
A second resistor connected between the second pad and an output terminal of the inverting amplifier circuit;
A third resistor having a first terminal connected to the output terminal of the voltage regulator;
A first diode having an anode connected to the first pad and a cathode connected to a second terminal of the third resistor;
A second diode having a cathode connected to the first pad and an anode connected to the fourth pad;
A third diode having an anode connected to the second pad and a cathode connected to a second terminal of the third resistor;
A fourth diode having a cathode connected to the second pad and an anode connected to the fourth pad;
A first transistor that is connected between the third pad and the fourth pad, and causes a current to flow when a voltage exceeding a predetermined value is applied between the third pad and the fourth pad;
A second transistor connected between the second terminal of the third resistor and the fourth pad, and causing a current to flow when a voltage exceeding a predetermined value is applied between them;
A semiconductor integrated circuit device comprising: The first transistor is an N-channel MOS transistor having a source / drain connected to the third pad and a gate and drain / source connected to the fourth pad;
The second transistor is an N-channel MOS transistor having a source / drain connected to a second terminal of the third resistor and a gate and a drain / source connected to the fourth pad;
The semiconductor integrated circuit device according to claim 1. The first transistor is an NPN bipolar transistor having an emitter / collector connected to the third pad and a base and a collector / emitter connected to the fourth pad;
The second transistor is an NPN bipolar transistor having an emitter / collector connected to a second terminal of the third resistor and a base and a collector / emitter connected to the fourth pad;
The semiconductor integrated circuit device according to claim 1.   The first pad, the second transistor, and the second pad are arranged at a predetermined interval along one side of the semiconductor substrate, and the first pad and the second transistor The first and second diodes are disposed between the first transistor and the third diode, and the third and fourth diodes are disposed between the second transistor and the second pad. The semiconductor integrated circuit device according to any one of the above.

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