JP3221437B2 - Input protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input protection circuit, and more particularly, to a gate oxide film of a metal oxide semiconductor (MOS) FET (Field Effect Transistor), which is protected from an excessive input voltage. Input protection circuit.

[0002]

2. Description of the Related Art In a circuit using a MOSFET,
An input protection circuit is provided to prevent the gate oxide film of the first transistor from being destroyed by an external electrostatic shock (high voltage). This type of input protection circuit is designed to break down when a voltage lower than the voltage at which the gate oxide film is destroyed is input. Also, in the case of a semiconductor manufacturer, when a power supply is opened at a development stage or the like, a ground (GN)
Set conditions such as when D) is open and set the input terminal V
The product is evaluated by applying an excessive voltage to in and testing whether each part of the input protection circuit operates as expected.

FIG. 10 shows a conventional input protection circuit. This input protection circuit is a pMOSFE formed on a semiconductor substrate.
It comprises a T (p-type MOSFET) 201 and an nMOSFET (n-type MOSFET) 202. nMOSFET 202
Is connected to the input terminal Vin. n
Source (S) and gate (G) of MOSFET 202
Are commonly connected and further connected to GND (ground). Also, a semiconductor substrate (SB) of the nMOSFET 202
Are also connected to GND. The drain (D) of the pMOSFET 201 is connected to the input terminal Vin, and its source (S)
And the gate (G) are connected to a power supply Vdd in a state of being commonly connected, and the semiconductor substrate (SB) of the pMOSFET 201 is connected to the power supply Vdd.
Are also connected to GND. The input terminal Vin is connected to an input stage of a MOSFET circuit to be protected (not shown).

In the input protection circuit having the configuration shown in FIG. 10, when a negative overvoltage is applied to the input terminal Vin in a state where the power supply Vdd is opened, the voltage between the drain (D) of the nMOSFET 202 and the substrate (SB) is increased. Current flows to the GND side to prevent the destruction of the internal element, and when a positive overvoltage is applied to the input terminal Vin, the nMOSFET 202 operates in a parasitic bipolar operation. Is performed, a current flows to the GND side,
The destruction of the internal element is prevented. When a positive overvoltage is applied to the input terminal Vin with the GND open, the drain (D) of the pMOSFET 201 and the substrate (S
Since the pn junction between B) and B) is forward biased, a current flows to the power supply Vdd side to prevent the destruction of the internal element and, when a negative overvoltage is applied to the input terminal Vin, the pMOSFET 201 Performs a parasitic bipolar operation, a current flows to the power supply Vdd side, and destruction of internal elements is prevented.

In the parasitic bipolar operation, when a current flows through the substrate, a voltage drop occurs due to the substrate resistance, and the source (S)
A phenomenon that occurs when a parasitic bipolar transistor including a substrate (BS) and a drain (D) conducts,
As shown in FIG. 11, a current called snapback
It has voltage characteristics. Here, the voltage Vt1 that shifts from the high resistance region to the low resistance region is called a trigger voltage, and this trigger voltage needs to be set lower than the breakdown voltage of the internal element (normally, the withstand voltage of the gate oxide film).

[0006]

However, the conventional input protection circuit has the following problems. Recent MO
With the miniaturization of SFET elements, the gate oxide film thickness has also been reduced. For example, in the generation having a gate length of 0.35 μm, the gate oxide film thickness is 7 to 8 nm and the gate length is 0.25 μm.
Generation has a gate oxide film thickness of 5 to 6 nm and a gate length of 0.18 μm has a gate oxide film thickness of 3.5 to 4 n.
Like m, it is getting thinner every generation.

The breakdown voltage of the gate oxide film is about 15 MV / cm in terms of an electric field, and 10 to 12 V for the generation with the gate length of 0.35 μm, 7 to 9 V for the generation with the gate length of 0.25 μm,
It becomes about 5 to 6 V in the 0.18 μm generation. Input terminal V
Since the overvoltage applied to in is instantaneous, even if a voltage higher than the above breakdown voltage is applied, the gate oxide film is not immediately destroyed. However, it still leads to a decrease in reliability such as characteristic fluctuation. Therefore, in the conventional input protection circuit, it is considered that the internal elements cannot be completely protected in the future as the elements are miniaturized.

Accordingly, an object of the present invention is to provide a MOSFE
An object of the present invention is to provide an input protection circuit in which a trigger voltage for snapback of T is reduced to prevent a gate oxide film of an internal element from being destroyed when an overvoltage is input.

[0009]

SUMMARY OF THE INVENTION According to the present invention, there is provided a MOSFET formed on a semiconductor substrate.
The gate and the source of the MOSFET are connected to a power source having a predetermined potential, and the drain of the MOSFET is connected to the input terminal of the circuit to be protected. Increasing the voltage level of the semiconductor substrate by
An input protection circuit is provided, wherein protection means for reducing a trigger voltage of ET snapback is provided between the power supply having the predetermined potential and the input terminal.

According to this configuration, the voltage applied to the semiconductor substrate by the protection means increases as the voltage level applied to the input terminal increases. Therefore, MOSFE
The trigger voltage of the snapback of T is reduced, and it is possible to prevent the gate oxide film of the MOSFET from being destroyed when an overvoltage is input.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the input protection circuit according to the present invention. nMOSFET1
One drain (D) is connected to the input terminal Vin, its source (S) and gate (G) are commonly connected, and this source (S) and gate (G) are connected to GND (ground). On the other hand, the drain (D) of the pMOSFET 12 is connected to the input terminal Vin, and its source (S) and gate (G) are connected to the power supply Vdd in a state of being commonly connected. A resistor 13 is provided between the input terminal Vin and the power supply Vdd.
(R3) and the resistor 14 (R4) are connected in series and inserted,
The intermediate connection point is the semiconductor substrate (S
B). Further, the input terminal Vin and GND
A resistor 15 (R1) and a resistor 16 (R2) are connected in series between them, and an intermediate connection point between them is nMOSFET1.
Connected to one semiconductor substrate (SB).

FIG. 2 shows a sectional structure of the first embodiment of the present invention. Here, only the lower half of the circuit shown in FIG. 1 is shown. The reason is that the nMOSFET 11 and the resistor 1
Circuit portion composed of 5, 16 and pMOSF
The circuit portion constituted by the ET 12 and the resistors 13 and 14 differs only in the conductivity type and bias of the impurity, and the other structures and operations are symmetrical and basically the same. Therefore, hereinafter, only the nMOSFET 11 side will be illustrated and described.

An element having a depth of 450 nm is provided in a p-type substrate 21.
After forming the isolation oxide film 22, the photoresist is masked.
The phosphorus (P) is 3 × 10 at 1 MeV¹³cm^-2Injection
Then, a deep n-well 23 is formed. Then, photo
Using resist as a mask, boron (B) is 300 keV
2 × 10¹³cm^-24 × 10 at 200 keV¹²c
m ^-25 × 10 at 30 keV¹²cm^-2And continuous injection
Then, a p-well 24 is formed. Next, a 7 nm thick game
Thickness 150 nm, gate length 0.35 μ via oxide film
Then, a gate electrode 25 of polycrystalline silicon is formed. simultaneous
Then, the polysilicon is formed on the element isolation oxide film 22 as shown in FIG.
The resistors R1 and R2 shown in FIG. Next, the photo cashier
5 × 1 at 20 keV using arsenic as mask
0¹³cm^-2Implant the lightly doped source and drain regions
(Not shown), and the gate side of an oxide film having a width of 100 nm
Form a wall (not shown). Next, mask the photoresist
Arsenic at 50 keV and 3 × 10^Fifteencm^-2Inject
And the source and drain high concentration regions 26 and 27 and the
A contact region 28 of a deep n-well 23 is formed, and n
The MOSFET 11 is formed. This nMOSFET 11
Has a channel width of 500 μm. In addition, photo cash register
BF2 (boron difluoride) for 30
3 × 10 at keV^Fifteencm^-2Inject and mix in p-well 24
Tact region 29 and contact region 3 of p-type substrate 21
0 is formed. Thereafter, the gate electrode 25, the resistors R1, R
2, high concentration regions 26 and 27 of source and drain
And a thickness 30 on the surface of the contact regions 28, 29, 30.
nm cobalt silicide layer 31 is formed and an interlayer insulating film is formed.
(Not shown) are formed, and each part is connected by metal wiring. What
The semiconductor substrate of the nMOSFET 11 described with reference to FIG.
In the present embodiment, (SB) is a digital signal as shown in FIG.
Corresponds to the p-well 24 surrounded by the n-well 23
The deep n-well 23 is connected to the power supply Vdd and the p-type substrate 2
1 is connected to the ground (GND).

As will be described later, the values of the resistors R1 and R2 are preferably set so that the ratio R1 / R2 becomes about 10 when the power supply voltage is 3.3V. Thus, for example, R
Assuming that 1 = 1 kΩ and R2 = 100Ω, the layer resistance of the cobalt silicidized polycrystalline silicon is about 10Ω / □. Therefore, if the width of the resistors R1 and R2 is 0.5 μm, the lengths are 50 μm and 5 μm. if,
If a photolithography step is added to prevent silicidation of the resistors R1 and R2, the layer resistance of the polycrystalline silicon becomes 1
00Ω / □ or more, so that the resistance R
The length of 1, R2 is 10 or more of the above value.

In FIG. 2, a pMOSF (not shown) is used.
ET12 will be formed in n-wells and nM
The one corresponding to the deep n-well 23 of the OSFET 11 is unnecessary. Conversely, if an n-type substrate is used, pMOSFE
T12 is formed in an n-well surrounded by a deep p-well, and nMOSFET 11 is formed in a p-well, eliminating the need for a deep n-well.

Next, when the power supply voltage is 3.3 V, the first and second
The operation of the first embodiment when the resistance ratio (R1 / R2) is set to 10 will be described. Also in the present invention, as described in [0005], the operation of the input protection circuit is confirmed by releasing the power supply Vdd or GND and applying an overvoltage to the input terminal Vin. Since the input terminal Vin is usually between 0 V and 3.3 V, the potential at the connection point of the resistor 15 (R1) and the resistor 16 (R2), that is, the substrate potential of the nMOSFET 11, is determined by connecting the input terminal Vin to the resistors R1 and R2. 0 V and 0.
It varies between 3V.

FIG. 3 shows the forward substrate voltage Vsu of the snapback trigger voltage Vt1 measured by an actual nMOSFET.
b (voltage applied to substrate SB). The sample used here had a gate length of 0.5 μm and a gate oxide film thickness of 7.5 nm.
V and the source voltage is 0V. As is clear from FIG.
It can be seen that the trigger voltage Vt1, which was about 10V when the substrate voltage Vsub = 0V, gradually decreases from around the point where the substrate voltage Vsub exceeds 0.5V. Therefore,
The input voltage is 3.3 V or less of the power supply voltage (the substrate voltage is 0.3 V or less).
V or less), the snapback characteristics hardly change, and snapback is likely to occur when an overvoltage of 5.5 V or more (substrate voltage is 0.5 V or more) is applied.
The breakdown voltage of a 7.5 nm thick gate oxide film is about 10
Therefore, in the conventional example where the substrate voltage Vsub is fixed to 0 V, about 10 V which is almost equal to the breakdown voltage is applied to the gate oxide film. On the other hand, in the present invention, when the input voltage exceeds 5.5 V, the substrate voltage Vsub rises to 0.5 V or more, and the trigger voltage Vt1 drops to 10 V or less, so that only a voltage lower than the breakdown voltage is applied to the gate oxide film. Will be. Incidentally, when the substrate is biased in the forward direction, there is a concern about off-leakage.

FIG. 4 shows the relationship between the off-state current Ioff measured by the same nMOSFET as in FIG. 3 and the forward substrate voltage Vsub. The measurement conditions here are that the gate voltage and the source voltage are 0 V, and the drain voltage is 3.3 V. As is apparent from FIG. 4, even when the substrate voltage Vsub increases from 0 V to 0.3 V, the off-state current Ioff increases from 6 × 10 ⁻¹⁴ A / μm to 3
The increase is only two digits or less to × 10 ⁻¹² A / μm, and it can be seen that this is not necessarily a level that poses a practical problem.

The above study is based on the first and second resistors R
1, R2 are replaced with first and second capacitors C1, C2,
The same holds when the ratio (C2 / C1) is set to 10. The case where the capacitors C1 and C2 are used will be described below.

FIG. 5 shows a second embodiment of the input protection circuit of the present invention. In this embodiment, the resistors R1 to R4 shown in FIG.
Are replaced with capacitances C1 to C4. That is, the resistors 11 (R3), 12 (R4), 13 (R
1) and 14 (R2) are converted to capacitances 51 (C3) and 52 (C
4), 53 (C1) and 54 (C2). The other configuration is the same as the configuration in FIG. 1, and a duplicate description is omitted here.

FIG. 6 shows a sectional structure according to the second embodiment of the present invention. The configuration of FIG. 6 is similar to that of FIG.
An input protection circuit including an OSFET 11 and first and second capacitances C1 and C2, and a pMOSFET 12
The input protection circuit composed of the first and third and fourth capacitances C3 and C4 differs only in the conductivity type and bias of the impurity, and the other structures and operations are substantially symmetric. Therefore, only the nMOSFET 11 and its peripheral configuration will be described here.

In the structure of FIG. 6, steps similar to those of the first embodiment are performed until the formation of an interlayer insulating film (not shown), except that the resistors R1 and R2 are not formed.
Thereafter, when connecting the respective parts with the metal wiring, the capacitances C1 and C2 are formed using two wiring layers. In particular,
One counter electrode 61, 62 is formed using the first metal wiring layer.
Is formed, and an interlayer insulating film (not shown) is formed. Then, the other counter electrode 6 is formed using the second metal wiring layer.
3, 64 are formed. In this way, the capacitance C1 is formed by the opposed electrodes 61 and 63, and the capacitance C2 is formed by the opposed electrodes 62 and 64.

As described above, when the power supply voltage is 3.3 V, the value of the capacitances C1 and C2 is expressed by the ratio (C2 / C1).
Should be set to about 10. Therefore,
For example, if C1 = 0.1 pF and C2 = 1 pF, the capacitance between wirings having an interlayer thickness of 1 μm is 0.035 pF / μm.
² , the counter electrodes 61 to 6 of the capacitances C1 and C2
4 have an area of 2900 μm (54
μm □) and 29000 μm (170 μm □).

FIG. 7 shows an electrode arrangement in which a capacitance is formed using three metal wiring layers in the second embodiment. In this case, the first capacitance C1 is
3 and between the opposing electrodes 71 and 63,
The second capacitance C2 is formed between the opposed electrodes 62 and 64 and between the opposed electrodes 72 and 64. As a result, the electrode area can be reduced to 値 of the above value, as compared with the case where up to two metal wiring layers are used. If an upper (four or more) metal wiring layer is used, the electrode area can be further reduced.

FIG. 8 shows a third embodiment of the input protection circuit of the present invention. In FIG. 8, the same reference numerals are used for the same portions as those in FIGS. 1 and 5, and thus, redundant description will be omitted below. In this embodiment, the nMOSFE
The drain (D) of T11 is connected to the input terminal Vin, the source (S) and the gate (G) are commonly connected, and the source (S) and the gate (G) are connected to GND (ground). On the other hand, the drain (D) of the pMOSFET 12 is connected to the input terminal Vin, and its source (S) and gate (G) are connected to the power supply Vdd in a state of being commonly connected. Between the power supply Vdd and the input terminal Vin, n3 + n4 diodes 81 are connected in series and inserted in the forward direction.
The connection point for dividing these into n3 and n4 is pMOSF
It is connected to the substrate (SB) of ET12. Further, a diode 81 is connected between the input terminal Vin and GND by n1 +
A connection point for connecting n2 pieces in series and inserting them in the forward direction and dividing them into n1 pieces and n2 pieces is connected to the substrate (SB) of the nMOSFET 11. The number of diodes will be described below.

Here, n1 and n2 diodes 81
The method of determining the number of used is described. Assuming that the forward voltage of one diode is Vf, it is set so as to satisfy Vdd / (n1 + n2) <Vf (1). This setting is the same for n3 and n4 diodes 81. The setting shown in the expression (1) is a condition for suppressing the leakage flowing through the diode during the normal operation. During normal operation, n1 +
Since a maximum voltage of Vdd is applied to both ends of the n2 diodes 81, the voltage Vdd /
If (n1 + n2) is smaller than the forward voltage Vf of each diode, the leakage can be suppressed.

For example, if the power supply voltage is 3.3 V, and if the forward voltage Vf is 0.33 V, then from the equation (1), Vdd /
Since Vf <n1 + n2, n1 + n2> 10 (=
3.3 / 0.33). Therefore, n1 is set to 10
And n2 are set to one. In this case, since the input voltage Vin in the normal operation is between 0 V and 3.3 V, the potential at the connection point between the n1 diodes 81 and the n2 diodes 81 is
That is, the substrate potential (SB potential) of the nMOSFET 11
Varies between 0V and 0.3V distributed by the n1 + n2 diodes 81. With such a configuration, pMOSFET according to the input voltage applied to the input terminal Vin
12 and the substrate (SB) of the nMOSFET 11 are biased in the forward direction, so that the snapback trigger voltage Vt1
Can be lowered.

FIG. 9 shows a sectional structure of the embodiment shown in FIG. Here, nMOSFET11, n1 and n2
Circuit portion composed of the diodes 81, the pMOSFET 12, n3 and n4 diodes 81
Is different from the MOSFET part only in the conductivity type and the bias of the impurities in the MOSFET part. Since the other structures and operations are symmetrical and basically the same, the nMOSFET 11 and the circuit related thereto Is shown only in FIG.

First, a p-type substrate 21 is provided with a depth of 450 nm.
Is formed. Next, phosphorus is implanted at 3 × 10 ¹³ cm ⁻² at 1 MeV using a photoresist as a mask to form a deep n-well 23. Next, using a photoresist as a mask, boron is applied at 300 keV for 2 ×.
10 ¹³ cm ^-2 , 4 × 10 ¹² cm ^{-2 at} 200 keV, 30
A p-well 24 is formed by continuously implanting 5 × 10 ¹² cm ⁻² at keV. Thereafter, using a photoresist as a mask, phosphorus is applied at 700 keV to 2 × 10 ¹³ cm ⁻² and 500 kV.
4 × 10 ¹² cm ^{−2 in} eV, and 100 keV in arsenic
5 × 10 ¹² cm ⁻² to form an n-well 91. Next, a gate electrode 25 of polycrystalline silicon having a thickness of 150 nm and a gate length of 0.35 μm is formed via a gate oxide film having a thickness of 7 nm. Then, using a photoresist as a mask, arsenic is implanted at 5 × 10 ¹³ cm ^{−2 at 20} keV to form low-concentration regions (not shown) of source and drain, and then a gate sidewall (not shown) of an oxide film having a width of 100 nm is formed. )
To form

Then, using a photoresist as a mask, arsenic is implanted at 3 × 10 ¹⁵ cm ⁻² at 50 keV to form high-concentration regions 26 and 27 of source and drain to form an nMOSFET.
11 and the contact region 28 of the deep n-well 23 and the contact region 9 of the n-well 91
Form 2 The channel width of this nMOSFET 11 is 500 μm. Then, BF2 (boron difluoride) was applied at 30 keV to 3 × 10
^By implanting ¹⁵ cm ⁻² , the contact region 29 of the p well 24 and the contact region 30 of the p-type substrate 21 are formed, a high-concentration p-type region 93 is formed, and a diode 94 by a pn junction is formed. Thereafter, a 30-nm-thick cobalt silicide layer 31 is formed on the surfaces of the gate electrode 25, the source and drain high concentration regions 26 and 27, the contact regions 28, 29, 30, and 92, and the high concentration region 93 of the diode 94. An interlayer insulating film (not shown) is formed, and each part is connected using metal wirings 95 and 96.

The nMOSFET 11 described with reference to FIG.
In the present embodiment, the substrate (SB) corresponds to the p-well 24 surrounded by the deep n-well 23 in FIG.
The deep n-well 23 is connected to the power supply Vdd, and the p-type substrate 21 is connected to ground (GND).

In FIG. 9, a pMOSF (not shown)
The ET 12 is formed in another n-well formed simultaneously with the n-well 91, and the nMOSFET 11
The one corresponding to the deep n-well 23 is unnecessary.
Conversely, if an n-type substrate is used, the pMOSFET 12 is formed in an n-well surrounded by a deep p-well, and nM
Since the OSFET 11 is formed in the p-well, a deep n-well is not required.

In each of the embodiments described above, the power supply is a single positive power supply. That is, the source, gate and resistor 16 (or the capacitance 54 and the diode 84) of the nMOSFET 11 are set to G
A configuration in which connection is changed from ND to a negative power supply may be used. Further, it is not always necessary to use the same protection means (voltage dividing resistor, capacitance, diode) on both the positive potential power supply side and the ground potential or negative potential power supply side. May be used in combination,
Conventional methods may be used in combination.

[0034]

As described above, according to the input protection circuit of the present invention, the voltage divided by the resistor, the capacitance, or the diode between each power supply terminal and the input terminal is applied to the pMOSF.
Protective means applied to each substrate of ET and nMOSFET are provided, and the semiconductor substrate is biased according to the input voltage so that the snapback trigger voltage is lowered.
Destruction of the gate oxide film of the internal element by the MOSFET from input of an overvoltage can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an input protection circuit according to the present invention.

FIG. 2 is a sectional view showing a sectional structure according to the first embodiment of the present invention.

FIG. 3 is a characteristic diagram showing the dependency of a snapback trigger voltage Vt1 measured by an nMOSFET on a forward substrate voltage Vsub.

FIG. 4 is a characteristic diagram showing a relationship between an off-current Ioff measured by an nMOSFET and a forward substrate voltage Vsub.

FIG. 5 is a circuit diagram showing a second embodiment of the input protection circuit of the present invention.

FIG. 6 is a cross-sectional view illustrating a cross-sectional structure according to a second embodiment of the present invention.

FIG. 7 is a plan view showing an electrode arrangement in a case where a capacitance portion formed using three metal wiring layers is formed in the second embodiment.

FIG. 8 is a circuit diagram showing a third embodiment of the input protection circuit of the present invention.

FIG. 9 is a sectional view showing a sectional structure of the embodiment shown in FIG. 8;

FIG. 10 is a circuit diagram showing a conventional input protection circuit.

FIG. 11 is a characteristic diagram showing current-voltage characteristics when a snapback operation occurs.

[Explanation of symbols]

 11 nMOSFET 12 pMOSFET 13 resistance (R3) 14 resistance (R4) 15 resistance (R1) 16 resistance (R2) 51 capacitance (C3) 52 capacitance (C4) 53 capacitance (C1) 54 capacitance ( C2) 61-64, 71, 72 Counter electrode 81 Diode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 27/092 29/78 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/822 H01L 21/8234 H01L 21/8238 H01L 27/088 H01L 27/092 H01L 29/78

Claims (8)

(57) [Claims] 1. A MOSFET formed on a semiconductor substrate.
In the input protection circuit configured by connecting the gate and the source of the MOSFET to a power source of a predetermined potential and connecting the drain of the MOSFET to the input terminal of the circuit to be protected, according to an increase in the voltage level applied to the input terminal Protection means for reducing the snap-back trigger voltage of the MOSFET by increasing the level of the substrate voltage of the MOSFET between the power supply having the predetermined potential and the input terminal. circuit. 2. The MOSFET is a pMOSFET when the power supply of the predetermined potential is a power supply of a positive potential, and is an nMOSFET when the power supply of the predetermined potential is a power supply of a ground potential or a negative potential. The protection means is connected between a power supply of the positive potential, the ground potential or the negative potential and a first voltage-dividing resistor connected between the MOSFET substrate and the MOSFET substrate and the input terminal. 2. The input protection circuit according to claim 1, wherein said input protection circuit is constituted by a second voltage dividing resistor. 3. The input protection circuit according to claim 2, wherein said first and second voltage dividing resistors are formed of the same layer of polycrystalline silicon as the gate electrode. 4. The MOSFET is a pMOSFET when the power supply of the predetermined potential is a power supply of a positive potential, and is an nMOSFET when the power supply of the predetermined potential is a power supply of a ground potential or a negative potential, The protection means includes a first capacitance connected in a forward direction between the power supply of the positive potential, the ground potential or the negative potential, and the substrate of the MOSFET, and a first capacitance connected between the substrate of the MOSFET and the input terminal. 2. The input protection circuit according to claim 1, wherein the input protection circuit includes a second capacitance connected in a forward direction. 5. The input protection circuit according to claim 4, wherein said first and second capacitances are formed using two or more metal wiring layers as electrodes. 6. The MOSFET is a pMOSFET when the power supply of the predetermined potential is a power supply of a positive potential, and is an nMOSFET when the power supply of the predetermined potential is a power supply of a ground potential or a negative potential. The protection means includes: a first diode connected in a forward direction between the power supply of the positive potential, the ground potential or the negative potential and the substrate of the MOSFET; and a forward diode connected between the substrate of the MOSFET and the input terminal. 2. The input protection circuit according to claim 1, comprising a second diode connected to the input terminal. 7. The method of claim 1, wherein the first diode has at least one
The second diode is composed of a plurality of diodes connected in series, and when the voltage applied to the input terminal is equal to or less than the power supply voltage, each of the first and second diodes 7. The input protection circuit according to claim 6, wherein a voltage applied to the input protection circuit is lower than a forward diode voltage. 8. The protection device according to claim 1, wherein when a voltage applied to said input terminal is equal to or lower than said power supply voltage, a change in a potential of said semiconductor substrate is about 0.
2. The input protection circuit according to claim 1, wherein the input protection circuit is set to be 5 V or less.