WO2008012899A1 - Semiconductor circuit device, semiconductor circuit device system, and manufacturing method for the semiconductor circuit device - Google Patents

Semiconductor circuit device, semiconductor circuit device system, and manufacturing method for the semiconductor circuit device Download PDF

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Publication number
WO2008012899A1
WO2008012899A1 PCT/JP2006/314900 JP2006314900W WO2008012899A1 WO 2008012899 A1 WO2008012899 A1 WO 2008012899A1 JP 2006314900 W JP2006314900 W JP 2006314900W WO 2008012899 A1 WO2008012899 A1 WO 2008012899A1
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WO
WIPO (PCT)
Prior art keywords
diffusion region
type
conductivity type
circuit device
semiconductor circuit
Prior art date
Application number
PCT/JP2006/314900
Other languages
French (fr)
Japanese (ja)
Inventor
Hiroshi Katakura
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2006/314900 priority Critical patent/WO2008012899A1/en
Publication of WO2008012899A1 publication Critical patent/WO2008012899A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a technology for performing back bias control for reducing leakage current in a semiconductor circuit device.
  • Patent Document 1 discloses a back bias setting method in a MOS (Metal Oxide Semiconductor) circuit.
  • Leakage current refers to current that flows to the gate regardless of the operation of the transistor because the positional relationship between the source and the drain becomes closer as the transistor element becomes smaller due to miniaturization of the process.
  • the back bias control technique enables the leakage current at the gate of the transistor to be reduced by applying a negative bias to the entire semiconductor substrate in the direction in which the backside force current of the electronic device is difficult to flow.
  • FIGS. 8 to 10 are diagrams for explaining a back bias control method in a conventional semiconductor circuit device, and FIG. 8 is a side sectional view schematically showing a configuration of a back-input controlled 2-input NAND circuit.
  • FIG. 9 is a plan view schematically showing wiring in the second layer of the power wiring metal, and
  • FIG. 10 is a plan view schematically showing a part of the power wiring metal first layer in an enlarged manner.
  • the conventional two-input NAND circuit 100 shown in FIG. 8 is configured by forming NMOS transistors 61 and 62 on a P-type conductive semiconductor substrate 51 (hereinafter referred to as P-type substrate) 51.
  • a second N-type well 53 having N-type conductivity is formed so as to surround the type 52 and the first N-type 54 having N-type conductivity by forming PMOS transistors 63 and 64. It is constituted by.
  • the second N-type well 53 electrically isolates the first P-type well 52 and the first N-type well 54 from the P-type substrate 51.
  • the symbol G in the figure indicates the gate.
  • the ground voltage Vss is supplied to the NMOS transistors 61 and 62 via the wiring L1, and the power supply voltage Vdd is supplied to the PMOS transistors 63 and 64 via the wiring L2.
  • the 2-input NAND circuit 100 is configured so that the back bias voltage VBN1 is applied by pulling the wiring L3 to the P + region 65 power supply wiring metal layer (see Fig. 9) formed in the first P-type well 52. At the same time, it is possible to perform knock bias control by drawing the wiring L4 from the N + region 66 formed in the first N-type well 54 to the power distribution metal layer and applying the back bias voltage VBP1. Yes.
  • the P-type substrate 51 is partitioned in a matrix by a plurality of sites 71 and power supply wiring regions 72, which are arrangement regions for transistors and the like, and in one direction (vertical direction in FIG. 9).
  • a plurality of sites 71 are continuously formed in the direction), and the sites 71 and the power supply wiring regions 72 are alternately formed in the other direction (the horizontal direction in FIG. 9).
  • Each site 71 is provided with a first P-type 52 or a first N-type 54, and in the example shown in FIG.
  • the 1st N type uel 54 is formed alternately and repeatedly.
  • the power supply wiring area 72 includes a power supply wiring area 721 that supplies power to the first N-type well 54 and a power supply wiring area 722 that supplies power to the first P-type well 52.
  • a power supply wiring region 721 is formed adjacent to the first N-type well 54, and a power supply wiring region 722 is formed adjacent to the first P-type well 52. That is, for the P-type substrate 51, the power supply wiring region 72 is formed adjacent to each site 71, and power is supplied to each site 71.
  • the second layer of the power wiring metal formed as a layer different from the layer in which the NMOS transistors 61 and 62 and the PMOS transistors 63 and 64 are formed is shown in FIG. As shown, the wirings L1 to L4 are formed in parallel.
  • the power wiring metal first layer formed as a layer lower than the power wiring metal second layer in the P-type substrate 51 and different from the layer in which the NMOS transistors 61 and 62 and the PMOS transistors 63 and 64 are formed.
  • the direction in which the wires Ll to L4 are disposed (the vertical direction in the drawing of FIG. 9) and the direction perpendicular to the drawing (the horizontal direction in the drawing of FIG. 9) Wirings L1 to L4 are formed.
  • the wirings LI and L3 are formed so as to overlap the first P-type well 52, and the wirings L2 and L4 are formed so as to overlap the first N-type well 54.
  • the wiring 73 in the first layer of the power wiring metal is electrically connected to the wiring L4 in the second layer of the power wiring metal by the contact 73 formed from the first layer of the power wiring metal to the second layer of the power wiring metal. It is connected.
  • the contacts 74, 75, and 76 formed from the first layer of the power wiring metal to the second layer of the power wiring metal cause the wiring in the first layer of the power wiring metal and the second layer of the power wiring metal.
  • L2, L3, and L1 are electrically connected to each other.
  • the contact 73 is connected to the wiring M 11, and this wiring Ml 1 is connected to the IN type well 54 through the contact 78.
  • the contact 75 is connected to the wiring M12, and this wiring M12 is connected to the first P-type well 54 via the contact 79.
  • the back bias voltages VBN 1, VBP 1, Vss, and Vdd are supplied to the first P-type well 52 and the first N-type well 54 formed at the site 71 in the conventional semiconductor circuit device. It has come to be.
  • Patent Document 1 International Publication WO00Z45437 Pamphlet
  • the present invention was devised in view of such problems, and in a semiconductor circuit device, a power supply wiring region is reduced by pulling out a contact for supplying a back bias voltage from the outer periphery of the site matrix. At the same time, the purpose is to secure a normal logic circuit layout area.
  • a semiconductor circuit device of the present invention includes a first conductive type in which a first conductive type semiconductor substrate and a second conductive type transistor different from the first conductive type are formed.
  • the first conductivity type first diffusion region and the second conductivity type second diffusion region form a transistor placement region, and the semiconductor circuit device is formed in the placement region.
  • a first power supply terminal for supplying a voltage to the transistor, and the third diffusion region force formed in the third diffusion region is also a back bias having a first polarity with respect to the first diffusion region.
  • the third power supply terminal may be further provided.
  • the semiconductor circuit device is further On the first conductive type semiconductor substrate, the first conductive type fifth and seventh diffusion regions, and the second conductive type sixth diffusion region, A second conductivity type transistor is formed on the sixth diffusion region, and a first conductivity type transistor is formed on the sixth diffusion region.
  • a back bias voltage is applied to the fifth and sixth diffusion regions. It may be configured not to.
  • the third diffusion region is formed such that its longitudinal direction forms a predetermined angle with respect to the longitudinal direction of the fourth diffusion region. Further, the predetermined angle may be configured to be 90 degrees.
  • a semiconductor circuit device of the present invention includes a fourth diffusion region of a second conductivity type different from the first conductivity type formed on the first conductivity type semiconductor substrate, and a fourth diffusion region in the fourth diffusion region.
  • a first conductivity type transistor formed on the second diffusion region and a power supply terminal for applying a second bias knock bias voltage different from the first polarity in the fourth diffusion region force It is characterized by having. Further, the third diffusion region and the fourth diffusion region are formed so that the longitudinal direction of the third diffusion region and the longitudinal direction of the fourth diffusion region are at a predetermined angle. May be. Further, the predetermined angle may be 90 degrees.
  • the combination of the first conductivity type and the second conductivity type is a combination of P type and N type or a combination of N type and P type, respectively.
  • a semiconductor circuit device system of the present invention includes a semiconductor circuit device and a power supply device that supplies a voltage to the semiconductor circuit device.
  • the semiconductor circuit device includes a first conductivity type semiconductor substrate, the first A first conductivity type first diffusion region in which a second conductivity type transistor different from the first conductivity type is formed; and a second conductivity type second diffusion region in which the first conductivity type transistor is formed; The first conductivity is applied with the back bias voltage of the first polarity from the power supply device.
  • a third diffusion region of a mold and a fourth diffusion region of a second conductivity type to which a back bias voltage having a second polarity different from the first polarity is applied. It is a circuit device system.
  • the first conductivity type first diffusion region and the second conductivity type second diffusion region form a transistor arrangement region and are formed in the arrangement region.
  • a first power supply terminal for supplying a voltage to the transistor, and the third diffusion region force formed in the third diffusion region also has the first polarity with respect to the first diffusion region.
  • a second power supply terminal for applying a back bias voltage and the fourth diffusion region force formed in the fourth diffusion region also have a back bias voltage of the second polarity with respect to the second diffusion region.
  • a third power supply terminal for applying voltage includes the step of forming a second conductivity type fourth diffusion region on a first conductivity type semiconductor substrate;
  • the method for manufacturing the semiconductor circuit device further includes forming a second conductivity type transistor on the first diffusion region and forming a first conductivity type transistor on the second diffusion region; Forming a power supply terminal for applying a back-bias voltage of the first polarity on the third diffusion region and a second-polarity knock bias different from the first polarity on the fourth diffusion region; A step of forming a power supply terminal for applying a source voltage may be included.
  • a semiconductor circuit device of the present invention includes a first conductivity type semiconductor substrate, a first conductivity type first diffusion region in which a second conductivity type transistor different from the first conductivity type is formed, and A second conductivity type second diffusion region in which a first conductivity type transistor is formed; and an i th conductivity type third diffusion region to which a back bias voltage of the first polarity is applied.
  • the present invention has at least one of the following effects or advantages.
  • Wiring can be reduced, and by reducing the power supply wiring area, it is possible to secure a normal logic circuit arrangement area and increase the density.
  • FIG. 1 is a side sectional view schematically showing a configuration of a semiconductor circuit device as a first embodiment of the present invention.
  • FIG. 2 is a plan view for explaining a wiring state of the semiconductor circuit device as the first embodiment of the present invention.
  • FIG. 3 is a plan view for explaining a well arrangement in the semiconductor circuit device as the first embodiment of the present invention.
  • FIG. 4 is a side sectional view schematically showing a configuration of a modification of the semiconductor circuit device according to the first embodiment of the present invention.
  • FIG. 5 is a plan view for explaining a well arrangement in a semiconductor circuit device as a modification of the first embodiment of the present invention.
  • FIG. 6 is a side sectional view schematically showing a configuration of a semiconductor circuit device according to a second embodiment of the present invention.
  • FIG. 7 is a side sectional view schematically showing a configuration of a modified example of the semiconductor circuit device according to the first embodiment of the present invention.
  • FIG. 8 is a diagram for explaining a back bias control method in a conventional semiconductor circuit device.
  • FIG. 9 is a diagram for explaining a back bias control method in a conventional semiconductor circuit device.
  • FIG. 10 is a diagram for explaining a back bias control method in a conventional semiconductor circuit device.
  • FIG. 11 is a diagram schematically showing a configuration of a semiconductor circuit device system as one embodiment of the present invention.
  • FIG. 1 is a side sectional view schematically showing the configuration of the semiconductor circuit device as the first embodiment of the present invention
  • FIG. 2 is a plan view for explaining the wiring state
  • FIG. 3 is a plan view for explaining the arrangement of the wells in the semiconductor circuit device la according to the first embodiment, and schematically shows the arrangement of the respective wells.
  • the semiconductor circuit device (semiconductor circuit device system) la is configured by a technology such as a gate array or a standard cell method, and is used in an information processing device, for example.
  • a technology such as a gate array or a standard cell method
  • P-type substrate (semiconductor substrate) 10 1st N-type well (second diffusion region) 11, 1st P-type well (first diffusion region) 13, 2nd P-type well (third A diffusion region) 14 and a second N-type well (fourth diffusion region) 12 are provided, and a power supply device 201 (see FIG. 11) is further provided.
  • the semiconductor circuit device includes a digital circuit.
  • inverter circuit 30a that is a CMOS (Complementary Metal Oxide Semiconductor) circuit is formed as the semiconductor circuit device la will be described.
  • CMOS Complementary Metal Oxide Semiconductor
  • the P-type substrate 10 is a semiconductor substrate having P-type (first conductivity type) conductivity.
  • an N-type (second type) different from the P-type substrate 10 is used.
  • a second N-type well (fourth diffusion region) 12 having conductivity of the conductivity type is formed.
  • the first P-type well (first diffusion region) 13, the first N-type well (second diffusion region) 11, and the second P-type well (third diffusion region). ) 14 is formed, and the second N-type well 12 electrically separates the first P-type well 13, the first N-type well 11 and the second P-type well 14 and the P-type substrate 10.
  • the first N-type well 11 is formed with various elements such as resistors, capacitors, diodes, transistors, etc. on its surface (upper surface in the example shown in FIG. 1), and has N-type conductivity. Configured.
  • a P-type transistor (P-type transistor) 302 is formed on the first N-type well 11, and the P + regions 22-1, 22 -2 are formed in the first N-type well 11.
  • the gate 32 is formed in an insulated state through an oxide film or the like (not shown).
  • the power supply voltage Vdd is supplied to the P + region 22-1 through the wiring L12. It has become so.
  • the symbol G represents the gate and the symbol D represents the drain.
  • the first P-type well 13 has various elements such as resistors, capacitors, diodes, transistors, etc. formed on its surface (upper surface in the example shown in FIG. 1), and has P-type conductivity. Been Yes.
  • an N-type transistor (N-type transistor) 301 is formed on the first P-type well 13 and an N + region 23-1, 23-2 force S is formed.
  • the gate 31 is formed in an insulated state through an oxide film (not shown), and the ground voltage Vss is supplied to the N + region 23-2 through the wiring L13. Yes.
  • the first N-type well 11 and the first P-type well 13 form a transistor arrangement region.
  • the N + region 23-1 of the 1st P-type wel 13 and the P + region 22-2 of the 1st N-type wel 11 are connected as a drain output (X), and the gate 31 of the 1st P-type wel 13 and the 1st N-type wel 11 gate 32 is connected as gate input (A).
  • a site region 41 composed of a plurality of rectangular shaped sites 411 and a power supply wiring region 42 composed of a plurality of rectangular power supply wiring regions 421, 422 are provided.
  • the site areas 41 and the power supply wiring areas 42 are alternately arranged.
  • the site region 41 In the site region 41, the direction orthogonal to the direction in which the site regions 41 and the power supply wiring regions 42 are alternately arranged (in the example shown in FIG. 2, the horizontal direction in the drawing), the vertical direction in the drawing, in the example shown in FIG. ), The 1st N-type wel 11 and the 1st P-type wel 13 are alternately arranged. Further, in the power supply wiring area 42, the direction perpendicular to the direction in which the site areas 41 and the power supply wiring areas 42 are alternately arranged (the horizontal direction in the example in FIG. 2) (the vertical direction in the example in FIG. 2). Direction), power supply wiring regions 421 and power supply wiring regions 422 are alternately and repeatedly formed.
  • a plurality of rectangular sites 411 and power supply wiring regions 421 and 422 are formed (partitioned) in a matrix shape, and one direction thereof (in the example shown in FIG. ) And a plurality of sites 411 are formed continuously, and the sites 411 and the power supply wiring regions 42 are alternately formed in the other direction (the horizontal direction in the example shown in FIG. 2).
  • Each site 411 is formed with the first P-type well 13 or the first N-type well 11 described above.
  • p-type wel 13 and 1st n-type wel 11 and force It is.
  • the first N-type well 11 and the first P-type well 13 are alternately and repeatedly arranged in a matrix in parallel or substantially in parallel with each other.
  • site matrix the entire region where the site 411 and the power supply wiring regions 421 and 422 are formed in a matrix on the P-type substrate 10 may be referred to as a site matrix.
  • the power supply wiring area 42 includes a power supply wiring area 421 that supplies power to the first N-type wel 11 and a power supply wiring area 422 that supplies power to the first P-type wel 13.
  • a power supply wiring region 421 is formed adjacent to the first N-type well 11, and a power supply wiring region 422 is formed adjacent to the first P-type well 13.
  • the power supply wiring region 42 is formed adjacent to each site 411, and power is supplied to each site 411.
  • first N-type well 11, first P-type well 13 and power supply wiring regions 42, 422 may be referred to as a site array portion 43.
  • the second N-type well 12 is formed on the P-type substrate 10 as a region that includes cytolytics (a plurality of site array portions 43), and on the P-type substrate 10,
  • the P-type substrate 10 and the first N-type well 11, the first P-type well 13, and the second P-type well 14 are formed so as to be electrically separated.
  • the second P-type well 14 is disposed so as to be in electrical communication with at least a portion of the first P-type well 13 and is connected to the P + region (power supply terminal). , Contact) 26 is formed.
  • the P + region 26 is supplied with the first polarity knock bias voltage VBBN from the power supply device 201 (see FIG. 11).
  • an N + region (power supply terminal, contact) 21 is formed in the second N-type well 12.
  • the power supply device 201 receives the first polarity and the first polarity.
  • the knock bias voltage VBBP having a different second polarity is applied (supplied).
  • the power supply wiring metal second layer formed as a layer different from the layer in which the N-type transistor 301 and the P-type transistor 302 are formed has a power supply wiring region 421,
  • the wiring L12 and the wiring L13 are formed in parallel along the arrangement direction 422 (the vertical direction in FIG. 2).
  • the wirings L12 and L13 are formed in the direction perpendicular to the direction in which the wirings L12 and L13 are formed in the second power supply metal layer (the horizontal direction in FIG. 2). Yes.
  • a wiring L 12 is formed along the longitudinal direction of the first N-type well 11 so as to overlap the first N-type well 11, and overlaps the first P-type well 13.
  • a wiring L13 is formed along the longitudinal direction of the first P-type well 13.
  • the contact 17 formed from the first layer of the power distribution metal to the second layer of the power wiring metal causes the wiring L12 in the first layer of the power wiring metal to be electrically connected to the wiring L12 of the second layer of the power wiring metal. It is connected.
  • the wiring L12 is formed along the edge of the site 411 at the upper side of the paper, and the wiring L13 is placed near the lower mold of the paper at the site 411.
  • the contacts 17 and 18 are also formed close to the end of the site 411.
  • the second P-type well 14 is disposed and formed so as to be in contact with at least a part of the first N-type well 11, the first P-type well 13 and the power supply wiring regions 421 and 422 forming the site array unit 43. ing.
  • the second P-type well 14 is formed in a plane elongated shape, and in the longitudinal direction (the vertical direction in FIG. 3), the first N It is arranged and formed so that it intersects (orthogonally) at a predetermined angle (90 degrees or almost 90 degrees) with the longitudinal direction of the mold wel 11 and the first P wel 13 (lateral direction in FIG. 3).
  • one second P-type well 14 force is formed so as to cross and contact with a plurality of site array parts 43 in the longitudinal direction.
  • the mold wel 11 and the second N-type wel 12 are arranged so that they intersect (directly intersect) at a predetermined angle (90 degrees or almost 90 degrees). It is arranged and formed so that the longitudinal direction of the 2P-type well 14 intersects (orthogonally) at a predetermined angle (90 degrees or almost 90 degrees).
  • the semiconductor circuit device la according to the first embodiment has a triple wel structure including the second N-type wel 12, the second P-type wel 14 and the first N-type wel 11 (or the first P-type wel 13). It can be said.
  • the second P-type well 14 and the first N-type well 11 and the first P-type well 13 formed in a plane elongated shape have an angle of 90 degrees or almost 90 degrees.
  • Crossing (orthogonal) force The second P-type well 14 is not limited to this, but at least partially abuts against the first N-type well 11 and the first P-type well 13 (polymerization).
  • the position and shape of the 1N-type wel 11 and the 1P-type wel 13 that intersect at an angle other than 90 degrees may be variously modified. Can be implemented.
  • a back bias voltage is applied to the second P-type well 14 in a region that does not overlap with the site array portion 43 in the second P-type well 14, that is, outside the site matrix in the second P-type 14 (outer peripheral portion).
  • a contact 141 for electrically connecting the metal layer (not shown) for supplying VBBN and the second P-type well 14 is formed, and a power supply device 201 (see FIG. 11) is connected to the contact 141.
  • the first polarity back bias voltage VBBN supplied from the power supply device 201 is applied to the second P-type well 14 via the S contact 141. That is, this contact 141 force corresponds to the P + region 26 in FIG.
  • a contact layer 123 for electrically connecting the metal layer (not shown) for supplying the back bias voltage V BBP to the second N-type well 12 and the second N-type well 12 is formed.
  • a power supply device 201 (see FIG. 11) is connected to.
  • the second polarity back bias voltage VBBP supplied from the power supply device 201 is applied to the second P-type well 12 via the S contact 123. This corresponds to N + region 21 in 1.
  • the back bias voltage VBBN is applied to the first P-type well 13 via the second P-type well 14, and the back bias voltage VBBP to the first N-type well 11 is applied to the second N-type well 14. It is done through uel 12.
  • the semiconductor circuit device la of the first embodiment for example, after the second N-type well 12 is formed on the P-type substrate 10, the second P-type well 14 is grown, and then the first N-type
  • the semiconductor circuit device la can be manufactured by forming the wel 11 and the first P-type wel 13 and then performing a transistor bulking process (BULK) manufacturing process, a process for manufacturing each power supply terminal and wiring, and the like. .
  • BULK transistor bulking process
  • the contact 141 in the region where the site array portion 43 is absent in the second P-type well 14, the contact 141 (P + region 26)
  • the back bias voltage VBBN is applied to the second P-type well 14 and the contact 123 (N + region 21) force is applied to the second N-type well 12 in the region where the site array part 43 and the second P-type well 14 are absent.
  • the back bias voltage VBB P is applied to the wel 12.
  • the second P-type is supplied by the back bias voltage V BBN applied from the power supply device 201 through the P + region 26.
  • the N-channel MOS (NMOS) transistor is controlled via the well 14 and the first P-type well 13, and the second N-type well 12 is supplied by the back bias voltage VBBP supplied from the power supply 201 via the N + region 21. Further, by controlling the P-channel MOS (PMOS) transistor via the first N-type well 11, the back noise control of the inverter circuit 30a is performed.
  • the reverse bias voltage is applied so that the pell is directly minus if the well voltage just below the transistor is NMOS, and the nwell is plus if PMOS. Become! /
  • the power supply wiring In area 42 (power supply wiring areas 421 and 422), it is not necessary to arrange and form wiring and contacts to supply the back bias voltages VBBN and VBBP.
  • the area occupied by the regions (421, 422) can be reduced, and the density of the semiconductor circuit device la can be increased.
  • the number of wiring channels can be increased.
  • the power wiring area 42 since there is no contact or the like for supplying back bias voltages V BBN and VBBP to the power wiring area 42 (power wiring areas 421 and 422), the power wiring area 42 In this case, for example, a logic circuit such as a transistor can be arranged and formed below the metal layer, and this can also increase the density of the semiconductor circuit device la.
  • the leakage current can be reduced and the power consumption can be reduced.
  • the back bias voltage VBBN is applied via the second P-type well 14 and the back bias voltage VBBP is applied via the second N-type well 12.
  • the back bias control is performed for both the NMOS transistor and the PMOS transistor, but the present invention is not limited to this.
  • the NMOS transistor and the PMOS formed on the P-type substrate 10 are not limited thereto. Only one of the transistors may be applied with a back bias voltage through the well.
  • FIG. 4 is a side sectional view schematically showing a configuration of a modified example of the semiconductor circuit device according to the first embodiment of the present invention.
  • FIG. 5 is a side view of the semiconductor circuit device lb as a modified example of the first embodiment.
  • FIG. 6 is a plan view for explaining a cell arrangement. In FIG. 5, for convenience, a part of the semiconductor circuit device lb is extracted and shown.
  • the semiconductor circuit device lb as a modified example of the first embodiment is configured by, for example, a technology such as a gate array or a standard cell system. Etc. are used.
  • an inverter circuit 30b that is a CMOS circuit is formed as a semiconductor circuit device lb as a modification of the first embodiment will be described.
  • the semiconductor circuit device lb includes a P-type substrate (semiconductor substrate) 10, a first N-type well (second diffusion region) 11, a first P-type well (first diffusion region) 13 and A second N-type well (fourth diffusion region) 12 is configured, and a first polarity knock bias voltage VBBN is applied from the power supply 201 (see FIG. 11) to the P + region (power supply terminal) 261.
  • Back bias voltage with a second polarity different from the first polarity VBBP force The power is supplied from the power supply 201 (see Fig. 11) via the N + region (power terminal) 21 formed in the second N-type well 12. Yes.
  • the semiconductor circuit device lb as a modification of the first embodiment has N-type (second conductivity type) conductivity on a P-type substrate 10 having P-type (first conductivity type) conductivity.
  • a second N-type wel 12 is formed, and on the second N-type wel 12, a first P-type wel 13 and a first N-type wel 11 are formed.
  • the wel 13 and the first N-type wel 11 and the P-type substrate 10 are electrically separated.
  • a P-type transistor (P-type transistor) 302 is formed on the first N-type well 11.
  • An N-type transistor (P-type transistor) 301 is formed on the first P-type well 13, and N + regions 23-1, 23-2 and 31 are formed, and a P + region 261 is formed.
  • the knock bias voltage VBBN is applied from the power supply device 201 (see FIG. 11) through the metal wiring (not shown) from the P + region 261. Further, the ground voltage Vss is supplied to the N + region 23-2 from the power supply device 201 (see FIG. 11) via the wiring L13.
  • the first N-type well 11 and the first P-type well 13 form a transistor arrangement region.
  • the second N-type well 12 is formed on the P-type substrate 10 as a region including the cytomatrix (a plurality of site array portions 43).
  • This P-type substrate 10 is electrically connected to the 1st N-type well 11 and the 1st P-type well 13 It is formed so as to be separated.
  • the semiconductor circuit device lb as a modification of the first embodiment is configured without the second P-type well 14 in the semiconductor circuit device la of the first embodiment, and the P + region 261
  • the P + region 261 is configured in substantially the same manner as the semiconductor circuit device la of the first embodiment except that it is applied from the power supply device 201 via the back bias voltage VBBN cathodic wiring (not shown). Yes.
  • Back bias control is performed by the back bias voltage VBBP applied via the PB, and only the P-channel MOS (PMOS) transistor performs the back bias control via the second N-type well 12 and the first N-type well 11. It has come to be.
  • PMOS P-channel MOS
  • this back-bias control is specifically applied by applying a reverse bias to the P-well when the NMOS voltage is just below the transistor is N MOS, and to the N-well plus when the PMOS is PMOS. To do.
  • the semiconductor circuit device lb as a modification of the first embodiment has a double-well structure by the second N-type wel 12 and the first N-type wel 11 (or the first P-type wel 13).
  • the semiconductor circuit device lb as a modification of the first embodiment includes, for example, the first N-type well 11 and the first P-type well after the second N-type well 12 is formed on the P-type substrate 10. 13 is formed, and then the transistor is manufactured by the process of manufacturing the transistor and the process of manufacturing each power supply terminal and wiring.
  • the power supply device 201 in the region where the site array portion 43 (see FIGS. 2 and 3) is absent in the second N-type well 12.
  • the back bias voltage VBBP applied to the second N-type well 12 from the N + region 21 to the P + region 261 from the power supply unit 201 is controlled by the back bias voltage VBBN applied to the second N-type well 12 from the power supply device 201. It is.
  • the power supply wiring In area 42 (power supply wiring area 421, 422), arrange wiring and contacts to supply knock bias voltage VBBP.By reducing the number of wirings that need not be formed, power supply wiring area 42 (power supply wiring area 421, 422 422) can be reduced, and the density of the semiconductor circuit device lb can be increased. In addition, the number of wiring channels can be increased.
  • the power supply wiring area 42 since there is no contact or the like for supplying the back bias voltage V BBP to the power supply wiring area 42 (power supply wiring areas 421, 422), the power supply wiring area 42 has no contact.
  • a logic circuit such as a transistor can be arranged and formed below the metal layer, and this can also increase the density of the semiconductor circuit device la.
  • the space efficiency is improved, and by performing the knock bias control, the leakage current can be reduced and the power consumption can be reduced. it can.
  • the inverter circuits 30a and 30b are formed on the P-type substrate 10 is described.
  • Various circuits may be formed on the P-type substrate 10.
  • a plurality of CMOS circuits may be provided on the P-type substrate 10, and moreover, these plural CMOS circuits may be provided.
  • Back bias control may be performed on only part of the circuit.
  • FIG. 6 is a side sectional view schematically showing the configuration of the semiconductor circuit device lc according to the second embodiment of the present invention.
  • the semiconductor circuit device lc of the second embodiment is configured by, for example, a gate array or a standard cell system and used in an information processing device or the like. .
  • the 2-input NAND circuit 30c and the inverter circuit 30d are formed on the same P-type substrate 10, and the 2-input NAND circuit 30c among them is formed in the 2-input NAND circuit 30c.
  • the back bias control is performed only on the inverter circuit 30d, and the back bias control is not performed on the inverter circuit 30d.
  • the inverter circuit 30d functions as a non-back bias control circuit unit in which knock bias control is not performed.
  • the semiconductor circuit device lc of the second embodiment of the present invention includes a P-type substrate (semiconductor substrate) 10, a first N-type well 11-1, 11-2, and a first P-type as shown in FIG. It consists of wels 13–1, 13-2, second P type wels 14–1, 14–2 and second N type wels 12.
  • P-type substrate 10, 1st N-type wel (second diffusion region) 11—1, 1st P-type wel (first diffusion region) 13—1, 2nd P-type wel (third diffusion region) 14— 1 and 2N type well (fourth diffusion region) 12 form a 2-input NAND circuit 30c
  • P type substrate 10, 1st N type well 11-2, 1st type P well 13-2 and 2nd type P An example in which the inverter circuit 30d is formed by the wel 14-2 is shown below.
  • N-type (second conductivity type) conductivity which is a conductivity type different from P-type substrate 10 on P-type substrate 10 having P-type (first conductivity type) conductivity.
  • a second N-type well (fourth diffusion region) 12 is formed. Further, on the second N-type well 12, the first P-type wel 13-1, the first N-type wel 11-1 and the second P-type wel 14-1 are formed. The 1P type wel 13-1, the first N type wel 11-1 and the second P type wel 14-1 are electrically separated from the P type substrate 10.
  • the first N-type well 11-1 forms a transistor arrangement region, and various elements such as resistors, capacitors, diodes, and transistors are arranged on the surface (the upper surface in the example of FIG. 6). It has N-type conductivity.
  • a P-type transistor (P-type transistor) 3 04 forming a part of a 2-input NAND circuit 30c is formed on the first N-type well 11-1 and a P + region 22— 1, 22-2, 22-3 are formed, and gates 32-1, 32-2 are formed in an insulated state through an oxide film or the like (not shown). Then, in the P + region 22-2, the power supply voltage Vdd is supplied from the power supply 201 (see FIG. 11) via the wiring L121.
  • the first P-well 13-1 forms an arrangement region of transistors, and various elements such as resistors, capacitors, diodes, transistors, etc. are formed on its surface (upper surface in the example of FIG. 6). It has P-type conductivity.
  • an N-type transistor (N-type transistor) 303 force S is formed on the first P-type well 13-1 and forms part of the 2-input NAND circuit 30c. 1, 23-2, 23-3 are formed, and gates 31-1, 31-2 are formed in an insulated state through an oxide film or the like (not shown). Further, the ground voltage Vss is supplied to the N + region 23-3 from the power supply device 201 (see FIG. 11) via the wiring L131.
  • a P-type second P-type well (seventh diffusion region) 14-2 is formed on the P-type substrate 10, and the second P-type well 14 is formed.
  • the 1st P-type wel (fifth diffusion region) 13-2 and the 1st N-type wel (sixth diffusion region) 11-2 are formed, and the 2nd P-type wel 14-2
  • the first P-type well 13-2 and the P-type substrate 10 are electrically connected.
  • the first N-type well 11-2 also forms a transistor arrangement region, and various elements such as resistors, capacitors, diodes, and transistors are arranged on the surface (the upper surface in the example of FIG. 6). Has N-type conductivity.
  • P + regions 22-4, 22-5 and N + region 24 are formed in the first N-type well 11-2 and insulated through an oxide film (not shown).
  • a gate 33 is formed.
  • the power supply voltage Vdd is supplied to the P + region 22-5 and the N + region 24 from the power supply device 201 (see FIG. 11) via the wiring L124.
  • the first P-type well 13-2 also forms a transistor arrangement region, and various elements such as resistors, capacitors, diodes, and transistors are formed on the surface (upper surface in the example of FIG. 6). It has the conductivity of.
  • N + regions 23-4, 23-5 and P + region 25 are formed in the first P-type well 13-2 and insulated through an oxide film or the like (not shown).
  • a gate 34 is formed.
  • the P + region 25 and the N + region 2 3-4 are supplied with the ground voltage Vss from the power supply device 201 (see FIG. 11) via the wiring L132.
  • the inverter circuit 30d does not perform back bias control, and does not apply a back bias voltage to the first P-type well 13-2 and the first N-type well 11-2.
  • the two-input NAND circuit 30c is configured as a site matrix similarly to the semiconductor circuit device la of the first embodiment (see FIGS. 2 and 3).
  • a site array portion 43 is formed on the second N-type well 12 formed on the P-type substrate 10.
  • the semiconductor circuit device lc of the second embodiment is also the same as the semiconductor circuit device la of the first embodiment in the two-input NAND circuit 30c as in the second N-type well 12, the second P-type well 14- It can be said that it has a triple wel structure by 1 and 1N type wel 11-1 (or 1st type P wel 13-1).
  • a contact layer 141 (see FIG. 3) is formed to electrically connect a metal layer (not shown) for supplying a back bias voltage VBBN of the first polarity to the second P-type well 14-1.
  • the first-polarity back bias voltage VBBN supplied from the power supply device 201 (see FIG. 11) is applied to the second P-type well 14-1 via 141 (P + region 26).
  • the region where neither the site array portion 43 nor the second P-type well 14-1 overlaps that is, the site matrix in the second N-type well 12 and the second P-type well 14
  • a metal layer (not shown) for supplying a back bias voltage VBBP having a second polarity different from the first polarity to the second N-type well 12 and a second N-type well 12 are electrically connected.
  • a contact 123 (see FIG. 3) is formed, and the second polarity back bias voltage VBBP supplied from the power supply device 201 (see FIG. 11) is supplied via this contact 123 (N + region 21). It is designed to be applied to 2nd N-type wel 12.
  • the back bias voltage VBBN is supplied to the first P-type well 13-1 from the second P-type well 14-1 and to the first N-type well 11-1.
  • the back bias voltage VBBP is supplied from the second N-type well 12.
  • the size in the second P-type well 14-1 is the same as the semiconductor circuit device la of the first embodiment.
  • the back bias voltage VBB N is applied to the second P-type well 14 1 in the region where the second array type 43 14 is absent, and the second N-type well 12 in the region where the site array unit 43 and the second P-type well 14-1 are absent.
  • Back bias voltage VBBP is applied to 2N type wel 12.
  • the 2-input NA ND circuit 30c formed in the first N-type wel 11-1 and the first P-type wel 13-1 it is applied via the P + region 26 from the power supply device 201 (see FIG. 11).
  • the N-channel MOS (NMOS) transistor is controlled by the back bias voltage VBBN via the second P-type 14 1 and the first P-type 131, and also from the power supply 201 (see FIG. 11).
  • the P-channel MOS (PMOS) transistor is controlled by the back bias voltage VBB P applied through the second N-type well 12 and the first N-type well 11—1, thereby Back bias control is performed.
  • this back bias control is specifically applied by applying a reverse bias to the P-well when the NMOS voltage is just below the transistor is N MOS, and to the N-well when the PMOS is N-MOS. It is done by.
  • the semiconductor circuit device lc of the second embodiment for example, after forming the second N-type well 12 on the P-type substrate 10, forms the second P-type wells 14-1, 14-2, After forming the 1st N-type wels 11-1, 11-2 and 1st P-type wels 13-1, 13-2, perform the transistor's Balta manufacturing process, the manufacturing process of each power supply terminal and wiring, etc. Can be manufactured.
  • the semiconductor circuit device lc as the second embodiment of the present invention it is possible to obtain the same effect as that of the first embodiment.
  • the area where power consumption is reduced by controlling the voltage to reduce the leakage current in this second embodiment, the 2-input NAND circuit 30c part
  • the back bias voltage sometimes referred to as the well voltage
  • a region (inverter circuit 30d portion in the second embodiment; non-back bias control circuit portion) can be formed without control, and one P-type substrate 10 can be formed in accordance with, for example, circuit characteristics. Can be used properly.
  • two types of transistors with and without knock bias control can be placed on the same chip. It can be created and is very convenient.
  • the clock width and the sensitivity of the sense amplifier are controlled. It is desirable to form a circuit without the need for knock bias control because of the influence on the
  • the back bias voltage VBBN is applied via the second P-type 14-1 in the 2-input NAND circuit 30c, and the second N-type 12 is applied.
  • the back bias voltage VBBP is applied to control the back bias for the! / And the deviation between the NMOS transistor and the PMOS transistor.
  • the back bias control may be performed only on one of the NMOS transistor and the PMOS transistor formed in the above.
  • FIG. 7 is a side sectional view schematically showing a configuration of a modified example of the semiconductor circuit device according to the first embodiment of the present invention.
  • the semiconductor circuit device Id as a modification of the second embodiment is also configured by, for example, a gate array, a standard cell system, etc. It is what is done.
  • a two-input NAND circuit 30e and an inverter circuit 30d are formed on the same P-type substrate 10, and this two-input NAND circuit An example in which back bias control is performed only for the PMOS transistor at 30e will be described.
  • the inverter circuit 30d functions as a non-back bias control circuit unit that does not perform back bias control.
  • a semiconductor circuit device Id as a modification of the second embodiment of the present invention includes a P-type substrate 10, first N-type wells 11-1, 11-2, first P-type well 13 — 1, 13-2, 2nd P-type wel 14-2 and 2nd N-type wel 12.
  • a two-input NAND circuit 30e is formed by the P-type wel (first diffusion region) 13-1 and the second N-type wel (fourth diffusion region) 12 and supplied from the power supply 201 (see FIG. 11).
  • a back bias voltage VBBN of the first polarity is applied to the P + region (power supply terminal) 262, and a back bias voltage of the second polarity different from the first polarity supplied from the power supply device 201 (see FIG. 11).
  • VBBP is applied through an N + region (power supply terminal) 21 formed in the second N-type well 12.
  • the inverter circuit 30d is formed by the P-type substrate 10, the first N-type well 11-2, the first P-type well 13-2, and the second P-type well 14-2.
  • the N-type (second conductivity type) conductivity is provided on the P-type substrate 10 having the P-type conductivity in the two-input NAND circuit 30e.
  • a second N-type well 12 is formed.
  • the first P-type well 13-1 and the first N-type well 11-1 are formed, and the second N-type well 1 2 force. These first P-type well 13-1 and the first N The mold well 11-1 and the P-type substrate 10 are electrically separated.
  • the first P-type well 13-1 forms an arrangement region of the transistor, and various elements such as a resistor, a capacitor, a diode, and a transistor are formed on the surface (upper surface in the example of FIG. 7).
  • P-type conductivity In the example shown in FIG. 7, the N + region 23-1, 1, 23-2, 23-3 and the P + region 262 are formed in the first P-type well 13-1, and the power supply device 201 is included in the P + region 262.
  • the back bias voltage VBBN of the first polarity is printed.
  • gates 31-1 and 31-2 are formed on the first P-type well 13-1 in an insulated state through an oxide film or the like (not shown). Further, the ground voltage Vss is supplied to the N + region 23-3 from the power supply device 201 (see FIG. 11) via the wiring L131.
  • the second N-type well 12 has a site matrix (a plurality of site array units 43) formed on the P-type substrate 10 in the same manner as the two-input NA ND circuit 30c in the semiconductor circuit device lc of the second embodiment.
  • the P-type substrate 1 is formed on the P-type substrate 10. It is formed so that 0 is electrically separated from the IN type wel 11-1 and the IP type wel 13-1.
  • the 2-input NAND circuit 30e is not provided with the second P-type well 14-1 in the semiconductor circuit device lc of the second embodiment.
  • the P + region 262 is provided, and the back bias voltage VBBN is applied to the P + region 262.
  • the semiconductor circuit device 1c of the second embodiment is substantially the same.
  • a double well formed by the second N-type well 12 and the first N-type well 11-1 (or the first P-type well 13-1) is used. If you have a structure,
  • a semiconductor circuit device Id as a modification of the second embodiment includes, for example, forming a second N-type well 12-2 on a P-type substrate 10 and then forming a second P-type well 14-2.
  • First N-type wels 11-1, 11-2 and 1P-type wels 13-1, 1, 13-2 are formed, and then manufactured by performing the transistor's Balta manufacturing process and the power supply terminal and wiring manufacturing processes. Can do.
  • the site array section 43 in the second N-type well 12 (Fig. 2, Fig. 2). 3) Back bias voltage VBBP applied to second N-type well 12 from power supply 201 through Balta contact N + region 21 in the absence region, and back bias voltage VBBN applied to P + region 262 from power supply 201
  • the back bias control of the 2-input NAND circuit 30e is performed.
  • this back bias control is specifically applied by applying a reverse bias voltage to the p-well if the NMOS voltage just below the transistor is N MOS, to P-minus if it is PMOS, or to N-plus if it is PMOS. Is done.
  • the semiconductor circuit device Id as a modified example of the second embodiment of the present invention can obtain the same operation and effect as the semiconductor circuit device lc of the second embodiment, and the power wiring region 42 ( In the power supply wiring area (421, 422), it is not necessary to arrange and form wiring and contacts to supply the back bias voltage VBBP, and to reduce the number of wiring As a result, the area occupied by the power supply wiring region 42 (power supply wiring regions 421 and 422) can be reduced, and the density of the semiconductor circuit device la can be increased. In addition, the number of wiring channels can be increased.
  • the power supply wiring area 42 Since there is no contact or the like for supplying the back bias voltage V BBP to the power supply wiring area 42 (power supply wiring areas 421, 422), the power supply wiring area 42 has no contact.
  • a logic circuit such as a transistor can be arranged and formed below the metal layer, and this can also increase the density of the semiconductor circuit device Id.
  • FIG. 11 is a diagram schematically showing a configuration of a semiconductor circuit device system as an embodiment of the present invention.
  • the semiconductor circuit device system 100 includes a power supply device 201 and a semiconductor circuit device la, and the power supply device 201 has a back bias voltage VBBN, VBBP, power supply voltage Vdd, and ground voltage Vss are supplied.
  • the semiconductor circuit device to which the power supply device 201 supplies the voltage is not limited to the semiconductor circuit device la shown in FIG. 11, and the semiconductor circuit device shown as each of the above-described embodiments and modifications thereof. Even if it is lb, lc, or Id, various modifications can be made without departing from the spirit of the present invention. In addition, the present invention is not limited to the above-described embodiments and modifications thereof, and various modifications can be made without departing from the spirit of the present invention.
  • the force described in the example in which the inverter circuit or the 2-input NAND circuit is formed on the P-type substrate 10 is not limited to this.
  • Various circuits other than these inverter circuits and 2-input NAND circuits may be formed.
  • the bias control voltage is applied to the second P-type well 14 (14-1) and the second N-type well 12 as contacts 141 (P + region 26),
  • force applied through contact 123 (N + region 21) is not limited to this.
  • it can be applied directly from the second P-type well 14 or the second N-type well 12 to the metal first layer, etc.
  • You can apply the back bias voltage by using various known methods that can be passed through the 1st P-type wel 13 or the 1st N-type wel 11! /.
  • the knock bias setting of the well may be performed by directly supplying the external terminal force. Further, as the knock bias setting circuit inside the chip, the power supply voltage force supplied from the external terminal is boosted. Alternatively, it may be supplied after being stepped down.
  • the well voltage directly under the transistor is NMOS
  • the P-type well is negative
  • PMO S is the N-type well
  • the force described for the example in which the inverter circuit 30d is provided as the non-back bias control circuit unit in which the back bias control is not performed is not performed.
  • Various circuits other than the inverter circuit that is not limited may be used as the non-back bias control circuit section.
  • the P-type substrate 10 which is a semiconductor substrate having a P-type conductivity is used.
  • the present invention is not limited to this.
  • An N-type substrate having a mold may be used.
  • the second P-type well 14 is replaced with an N-type well (second N-type well).
  • second N-type well an N-type well
  • second P-type well instead of the second n-type well 12.
  • it can manufacture easily by reversing the formation order of the well produced
  • the PMOS transistor in the inverter circuit 30b is well (second N-type well 12).
  • the force shown in the example of applying the back bias voltage through the gate is not limited to this.
  • the back bias voltage may be applied through the well only to the NMOS transistor.
  • the back bias voltage is applied only to the PMOS transistor in the two-input NAND circuit 30e via the well (the first N-type well 11-1).
  • the present invention is not limited to this.
  • the back bias voltage may be applied to the NMOS transistor only through the well.
  • the present invention can be applied to back bias control of various circuits in a semiconductor circuit device.

Abstract

Provided is a semiconductor circuit device constituted to comprise a first semiconductor substrate (10) of a first conduction type, a first diffusion domain (13) of the first conduction type having a second conduction type transistor (301) formed therein, a second diffusion domain (11) of a second conduction type having a first conduction type transistor (302) formed therein, a third diffusion domain (14) of the first conduction type, to which a back bias voltage of a first polarity is applied, and a fourth diffusion domain (12) of the second conduction type, to which a back bias voltage of a second polarity is applied. This constitution can decrease the wiring number thereby to narrow a power source wiring area.

Description

明 細 書  Specification
半導体回路装置，半導体回路装置システムおよび半導体回路装置の製 造方法  Semiconductor circuit device, semiconductor circuit device system, and manufacturing method of semiconductor circuit device
技術分野  Technical field
[0001] 本発明は、半導体回路装置においてリーク電流を低減するためのバックバイアス制 御を行なう技術に関する。  TECHNICAL FIELD [0001] The present invention relates to a technology for performing back bias control for reducing leakage current in a semiconductor circuit device.
背景技術  Background art
[0002] 例えばゲートアレイやスタンダードセル方式等のテクノロジにより構成された半導体 回路装置にぉ 、て、トランジスタのノックバイアスを制御してリーク電流を低減するこ とにより、その消費電力を下げる手法が知られており、例えば、下記特許文献 1には、 MOS (Metal Oxide Semiconductor)回路におけるバックバイアスの設定手法が開示 されている。  [0002] For example, a semiconductor circuit device configured by a technology such as a gate array or a standard cell method is known to reduce power consumption by controlling the knock bias of a transistor to reduce leakage current. For example, Patent Document 1 below discloses a back bias setting method in a MOS (Metal Oxide Semiconductor) circuit.
[0003] リーク電流とは、プロセスの微細化によるトランジスタ素子の小型化に伴い、ソースと ドレイン間の位置関係が近くなることにより、トランジスタの動作とは無関係にゲートに 流れる電流をいう。電子デバイスの裏側力 電流の流れにくい方向に対して、半導体 基板全体に負のバイアスをかけることにより、トランジスタのゲートにおけるリーク電流 の減少を可能にするのがバックバイアス制御手法である。  [0003] Leakage current refers to current that flows to the gate regardless of the operation of the transistor because the positional relationship between the source and the drain becomes closer as the transistor element becomes smaller due to miniaturization of the process. The back bias control technique enables the leakage current at the gate of the transistor to be reduced by applying a negative bias to the entire semiconductor substrate in the direction in which the backside force current of the electronic device is difficult to flow.
[0004] 図 8〜図 10は従来の半導体回路装置におけるバックバイアス制御手法を説明する ための図であり、図 8はバックノィァス制御された 2入力 NAND回路の構成を模式的 に示す側断面図、図 9はその電源配線メタル第 2層における配線を模式的に示す平 面図、図 10はその電源配線メタル第 1層における一部を拡大して模式的に示す平面 図である。  FIGS. 8 to 10 are diagrams for explaining a back bias control method in a conventional semiconductor circuit device, and FIG. 8 is a side sectional view schematically showing a configuration of a back-input controlled 2-input NAND circuit. FIG. 9 is a plan view schematically showing wiring in the second layer of the power wiring metal, and FIG. 10 is a plan view schematically showing a part of the power wiring metal first layer in an enlarged manner.
図 8に示す従来の 2入力 NAND回路 100は、 P型の導電性を有する半導体基板（ 以下、 P型基板） 51上において、 NMOSトランジスタ 61, 62が形成され P型の導電 性を有する第 1P型ゥエル 52と、 PMOSトランジスタ 63, 64が形成され N型の導電性 を有する第 1N型ゥエル 54とを環囲するように、 N型の導電性を有する第 2N型ゥェ ル 53が形成されることにより構成されている。 [0005] また、この 2入力 NAND回路 100においては、第 2N型ゥエル 53が、第 1P型ゥェ ル 52および第 1N型ゥエル 54を P型基板 51と電気的に分離している。なお、以下、 図中、符号 Gはゲートを示すものとする。 The conventional two-input NAND circuit 100 shown in FIG. 8 is configured by forming NMOS transistors 61 and 62 on a P-type conductive semiconductor substrate 51 (hereinafter referred to as P-type substrate) 51. A second N-type well 53 having N-type conductivity is formed so as to surround the type 52 and the first N-type 54 having N-type conductivity by forming PMOS transistors 63 and 64. It is constituted by. In the two-input NAND circuit 100, the second N-type well 53 electrically isolates the first P-type well 52 and the first N-type well 54 from the P-type substrate 51. In the following, the symbol G in the figure indicates the gate.
そして、 NMOSトランジスタ 61, 62には、配線 L1を介してグランド電圧 Vssが供給 され、 PMOSトランジスタ 63, 64には、配線 L2を介して電源電圧 Vddが供給される ようになっている。  The ground voltage Vss is supplied to the NMOS transistors 61 and 62 via the wiring L1, and the power supply voltage Vdd is supplied to the PMOS transistors 63 and 64 via the wiring L2.
[0006] また、 2入力 NAND回路 100においては、第 1P型ゥエル 52に形成した P+領域 65 力 電源配線メタル層（図 9参照）に配線 L3を引き出してバックバイアス電圧 VBN1 をかけるように構成するとともに、第 1N型ゥエル 54に形成した N+領域 66から電源配 線メタル層に配線 L4を引き出してバックバイアス電圧 VBP1をかけるように構成する ことにより、ノックバイアス制御を行なうことができるようになつている。  [0006] In addition, the 2-input NAND circuit 100 is configured so that the back bias voltage VBN1 is applied by pulling the wiring L3 to the P + region 65 power supply wiring metal layer (see Fig. 9) formed in the first P-type well 52. At the same time, it is possible to perform knock bias control by drawing the wiring L4 from the N + region 66 formed in the first N-type well 54 to the power distribution metal layer and applying the back bias voltage VBP1. Yes.
[0007] そして、このようなバックバイアス制御を行なうことにより、トランジスタにおけるリーク 電流を軽減して、消費電力を低減することができるのである。  [0007] By performing such back bias control, the leakage current in the transistor can be reduced and the power consumption can be reduced.
さて、 P型基板 51は、図 9に示すように、トランジスタ等の配置領域である複数のサ イト 71および電源配線領域 72によりマトリクス状に区画され、その一の方向（図 9の紙 面縦方向）に複数のサイト 71が連続して形成されるとともに、他の方向（図 9の紙面横 方向）においては、サイト 71と電源配線領域 72とが交互に形成されている。  As shown in FIG. 9, the P-type substrate 51 is partitioned in a matrix by a plurality of sites 71 and power supply wiring regions 72, which are arrangement regions for transistors and the like, and in one direction (vertical direction in FIG. 9). A plurality of sites 71 are continuously formed in the direction), and the sites 71 and the power supply wiring regions 72 are alternately formed in the other direction (the horizontal direction in FIG. 9).
[0008] 各サイト 71には、それぞれ第 1P型ゥエル 52もしくは第 1N型ゥエル 54が形成され るようになっており、図 9に示す例においては、その縦方向に、第 1P型ゥエル 52と第 1N型ゥエル 54とが交互に繰り返し並べて形成されている。  [0008] Each site 71 is provided with a first P-type 52 or a first N-type 54, and in the example shown in FIG. The 1st N type uel 54 is formed alternately and repeatedly.
電源配線領域 72は、図 9に示すように、第 1N型ゥエル 54に電力を供給する電源 配線領域 721と、第 1P型ゥエル 52に電力を供給する電源配線領域 722とをそなえ て構成されており、第 1N型ゥエル 54に隣接して電源配線領域 721が、又、第 1P型 ゥエル 52に隣接して電源配線領域 722がそれぞれ形成されている。すなわち、 P型 基板 51にお ヽては、各サイト 71に隣接して電源配線領域 72がそれぞれ形成され、 サイト 71毎に電力供給が行なわれるようになつている。  As shown in FIG. 9, the power supply wiring area 72 includes a power supply wiring area 721 that supplies power to the first N-type well 54 and a power supply wiring area 722 that supplies power to the first P-type well 52. A power supply wiring region 721 is formed adjacent to the first N-type well 54, and a power supply wiring region 722 is formed adjacent to the first P-type well 52. That is, for the P-type substrate 51, the power supply wiring region 72 is formed adjacent to each site 71, and power is supplied to each site 71.
[0009] 電源配線領域 72における、 NMOSトランジスタ 61, 62や PMOSトランジスタ 63, 6 4が形成された層とは異なる層として形成された電源配線メタル第 2層には、図 9に示 すように、配線 L1〜L4が平行に形成されている。 In the power wiring region 72, the second layer of the power wiring metal formed as a layer different from the layer in which the NMOS transistors 61 and 62 and the PMOS transistors 63 and 64 are formed is shown in FIG. As shown, the wirings L1 to L4 are formed in parallel.
また、 P型基板 51における、電源配線メタル第 2層よりも下位であって、 NMOSトラ ンジスタ 61, 62や PMOSトランジスタ 63, 64が形成された層とは異なる層として形成 された電源配線メタル第 1層にお 、ては、電源配線メタル第 2層にお 、て配線 Ll〜 L4が配設された方向（図 9の紙面縦方向）と直行する方向（図 9の紙面横方向）に、 配線 L1〜L4が形成されている。  Further, the power wiring metal first layer formed as a layer lower than the power wiring metal second layer in the P-type substrate 51 and different from the layer in which the NMOS transistors 61 and 62 and the PMOS transistors 63 and 64 are formed. In the first layer, in the second layer of the power wiring metal, the direction in which the wires Ll to L4 are disposed (the vertical direction in the drawing of FIG. 9) and the direction perpendicular to the drawing (the horizontal direction in the drawing of FIG. 9) Wirings L1 to L4 are formed.
[0010] なお、図 9に示す例においては、第 1P型ゥエル 52に重なるように配線 LI, L3が形 成され、第 1N型ゥエル 54に重なるように配線 L2, L4が形成されている。又、電源配 線メタル第 1層カゝら電源配線メタル第 2層にかけて形成されたコンタクト 73により、電 源配線メタル第 1層における配線 L4が電源配線メタル第 2層の配線 L4と電気的に接 続されている。 In the example shown in FIG. 9, the wirings LI and L3 are formed so as to overlap the first P-type well 52, and the wirings L2 and L4 are formed so as to overlap the first N-type well 54. In addition, the wiring 73 in the first layer of the power wiring metal is electrically connected to the wiring L4 in the second layer of the power wiring metal by the contact 73 formed from the first layer of the power wiring metal to the second layer of the power wiring metal. It is connected.
[0011] 同様にして、電源配線メタル第 1層から電源配線メタル第 2層にかけて形成されたコ ンタクト 74, 75, 76により、電源配線メタル第 1層と電源配線メタル第 2層とにおいて 、配線 L2, L3, L1どうしがそれぞれ電気的に接続されている。  [0011] Similarly, the contacts 74, 75, and 76 formed from the first layer of the power wiring metal to the second layer of the power wiring metal cause the wiring in the first layer of the power wiring metal and the second layer of the power wiring metal. L2, L3, and L1 are electrically connected to each other.
このように、従来の半導体回路装置においては、電源配線領域 72には、ゥエルコ ンタクト用に、電源配線メタル 2層とゥエルとを繋ぐコンタクトが形成され、電源配線メ タル 1層における横方向の配線は分断されるようになって!/、る。  Thus, in the conventional semiconductor circuit device, in the power supply wiring region 72, a contact connecting the power supply metal 2 layer and the well is formed for the contact, and the horizontal wiring in the power supply metal 1 layer is formed. Is now divided! /
[0012] また、電源配線メタル第 1層においては、図 10に示すように、コンタクト 73は配線 M 11に接続されており、この配線 Ml 1はコンタクト 78を介して第 IN型ゥエル 54と接続 されている。更に、コンタクト 75は配線 M12に接続されており、この配線 M12はコン タクト 79を介して第 1P型ゥエル 54と接続されて 、る。  Further, in the first layer of the power wiring metal, as shown in FIG. 10, the contact 73 is connected to the wiring M 11, and this wiring Ml 1 is connected to the IN type well 54 through the contact 78. Has been. Further, the contact 75 is connected to the wiring M12, and this wiring M12 is connected to the first P-type well 54 via the contact 79.
このように構成することにより、従来の半導体回路装置では、サイト 71に形成された 第 1 P型ゥエル 52や第 1N型ゥエル 54に対してバックバイアス電圧 VBN 1 , VBP 1 , Vss, Vddが供給されるようになっている。  With this configuration, the back bias voltages VBN 1, VBP 1, Vss, and Vdd are supplied to the first P-type well 52 and the first N-type well 54 formed at the site 71 in the conventional semiconductor circuit device. It has come to be.
特許文献 1：国際公開 WO00Z45437号パンフレット  Patent Document 1: International Publication WO00Z45437 Pamphlet
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0013] し力しながら、このような従来の半導体回路装置においては、配線 LI, L2, L3, L 4やコンタクト 73〜76が形成された電源配線領域 72には、ロジックセルを形成するこ とができず、このような電源配線領域が増大すると、半導体回路装置の高密度化が 阻害されるという課題がある。 However, in such a conventional semiconductor circuit device, the wirings LI, L2, L3, L 4 and the power wiring region 72 where the contacts 73 to 76 are formed, a logic cell cannot be formed. If the power wiring region increases, the density of the semiconductor circuit device is hindered. There are challenges.
半導体回路装置においては、高密度化の要求及び低消費電力化の要求に伴い、 例えば、ロジック用や IZO (Input Output)用，バックバイアス用（Nゥエル用， Pゥエル 用）等、サイトに供給される電源信号は増加する傾向にあり、これらの電源供給用の 信号線を、 1サイト毎あるいは 2サイト， 3サイト毎等の所定間隔で設ける必要がある。 このため、従来の半導体回路装置においては、通常のロジック回路の結線に使用す る配線用のチャネル領域の減少や、通常のロジック回路の配置領域力 実装上大き な問題となっている。  In semiconductor circuit devices, in response to demands for higher density and lower power consumption, for example, logic, IZO (Input Output), back bias (N-well, P-well), etc. are supplied to the site. The number of power supply signals tends to increase, and it is necessary to provide these power supply signal lines at predetermined intervals such as one site or two sites or three sites. For this reason, in the conventional semiconductor circuit device, the channel area for wiring used for the connection of the normal logic circuit is reduced, and the layout area power of the normal logic circuit is a serious problem in mounting.
[0014] 本発明は、このような課題に鑑み創案されたもので、半導体回路装置において、バ ックバイアス電圧供給用のコンタクトをサイトマトリクスの外周のゥエルから引き出すこ とにより、電源配線領域を小さくするとともに通常のロジック回路の配置領域を確保す るようにすることを目的とする。  [0014] The present invention was devised in view of such problems, and in a semiconductor circuit device, a power supply wiring region is reduced by pulling out a contact for supplying a back bias voltage from the outer periphery of the site matrix. At the same time, the purpose is to secure a normal logic circuit layout area.
課題を解決するための手段  Means for solving the problem
[0015] 上記の目的を達成するために、本発明の半導体回路装置は、第 1導電型の半導体 基板と、前記第 1導電型とは異なる第 2導電型のトランジスタが形成された第 1導電型 の第 1の拡散領域と、第 1導電型のトランジスタが形成された第 2導電型の第 2の拡散 領域と、第 1極性のバックバイアス電圧が印加される第 1導電型の第 3の拡散領域と、 前記第 1極性とは異なる第 2極性のバックバイアス電圧が印加される第 2導電型の第 4の拡散領域とを有することを特徴とする。また、前記第 1導電型の第 1の拡散領域と 、前記第 2導電型の第 2の拡散領域は、トランジスタの配置領域を形成し、前記半導 体回路装置は、前記配置領域内に形成された、前記トランジスタに電圧を供給する ための第一の電源端子と、前記第 3の拡散領域に形成された、前記第 3の拡散領域 力も前記第 1の拡散領域に対する第 1極性のバックバイアス電圧を印加するための 第 2の電源端子と、前記第 4の拡散領域に形成された、前記第 4の拡散領域から前 記第 2の拡散領域に対する第 2極性のバックバイアス電圧を印加するための第 3の電 源端子と、を更に備えるように形成するようにしてもよい。前記半導体回路装置はさら に、前記第 1導電型の半導体基板上に、第 1導電型の第 5及び第 7の拡散領域と、第 2導電型の第 6の拡散領域とを有し、前記第 5の拡散領域上に第 2導電型のトランジ スタが形成されるとともに、前記第 6の拡散領域上に第 1導電型のトランジスタが形成 され、前記第 5及び前記第 6の拡散領域にはバックバイアス電圧を印カロしないように 構成してもよい。なお、前記第 3の拡散領域は、その長手方向が前記第 4の拡散領 域の長手方向に対して所定の角度をなすように形成されることを特徴としてもょ 、。 さらに、前記所定の角度が 90度であるように構成してもよ 、。 [0015] In order to achieve the above object, a semiconductor circuit device of the present invention includes a first conductive type in which a first conductive type semiconductor substrate and a second conductive type transistor different from the first conductive type are formed. Type first diffusion region, second conductivity type second diffusion region in which a first conductivity type transistor is formed, and first conductivity type third diffusion region to which a back bias voltage of the first polarity is applied. A diffusion region; and a fourth diffusion region of a second conductivity type to which a back bias voltage having a second polarity different from the first polarity is applied. The first conductivity type first diffusion region and the second conductivity type second diffusion region form a transistor placement region, and the semiconductor circuit device is formed in the placement region. A first power supply terminal for supplying a voltage to the transistor, and the third diffusion region force formed in the third diffusion region is also a back bias having a first polarity with respect to the first diffusion region. A second power supply terminal for applying a voltage, and a second bias voltage formed on the fourth diffusion region from the fourth diffusion region to the second diffusion region. The third power supply terminal may be further provided. The semiconductor circuit device is further On the first conductive type semiconductor substrate, the first conductive type fifth and seventh diffusion regions, and the second conductive type sixth diffusion region, A second conductivity type transistor is formed on the sixth diffusion region, and a first conductivity type transistor is formed on the sixth diffusion region. A back bias voltage is applied to the fifth and sixth diffusion regions. It may be configured not to. The third diffusion region is formed such that its longitudinal direction forms a predetermined angle with respect to the longitudinal direction of the fourth diffusion region. Further, the predetermined angle may be configured to be 90 degrees.
また、前記第 1導電型と前記第 2導電型の組み合わせはそれぞれ、 P型と N型の組み 合わせ及び N型と P型の組み合わせの 、ずれか一つの組み合わせであるように構成 してもよい。次に、本発明の半導体回路装置は、第 1導電型の半導体基板上に形成 された前記第 1導電型とは異なる第 2導電型の第 4の拡散領域と、前記第 4の拡散領 域内に形成された第 1導電型の第 3の拡散領域と、前記第 3拡散領域内に形成され た第 1導電型の第 1の拡散領域と、前記第 3拡散領域内に形成された第 2導電型の 第 2の拡散領域と、前記第 1の拡散領域上に形成された第 2導電型のトランジスタと、 前記第 3の拡散領域力も第 1極性のバックバイアス電圧を印加するための電源端子と 、前記第 2の拡散領域上に形成された第 1導電型のトランジスタと、前記第 4の拡散 領域力も前記第 1極性とは異なる第 2極性のノ ックバイアス電圧を印加するための電 源端子とを有することを特徴とする。また、前記第 3の拡散領域の長手方向と前記第 4の拡散領域の長手方向とが所定の角度をもって、前記第 3の拡散領域と前記第 4 の拡散領域とが形成されるように構成してもよい。さらに、前記所定の角度が 90度で あるように構成してもよい。 Further, the combination of the first conductivity type and the second conductivity type may be configured to be any one of a combination of P type and N type and a combination of N type and P type. . Next, a semiconductor circuit device of the present invention includes a fourth diffusion region of a second conductivity type different from the first conductivity type formed on the first conductivity type semiconductor substrate, and a fourth diffusion region in the fourth diffusion region. A third diffusion region of the first conductivity type formed in the first diffusion region, a first diffusion region of the first conductivity type formed in the third diffusion region, and a second diffusion region formed in the third diffusion region. A second diffusion region of conductivity type, a second conductivity type transistor formed on the first diffusion region, and a power supply terminal for applying a back bias voltage of the first polarity also to the third diffusion region force A first conductivity type transistor formed on the second diffusion region and a power supply terminal for applying a second bias knock bias voltage different from the first polarity in the fourth diffusion region force It is characterized by having. Further, the third diffusion region and the fourth diffusion region are formed so that the longitudinal direction of the third diffusion region and the longitudinal direction of the fourth diffusion region are at a predetermined angle. May be. Further, the predetermined angle may be 90 degrees.
なお、。前記第 1導電型と前記第 2導電型の組み合わせはそれぞれ、 P型と N型の組 み合わせ又は N型と P型の組み合わせであることを特徴とする。 In addition ,. The combination of the first conductivity type and the second conductivity type is a combination of P type and N type or a combination of N type and P type, respectively.
次に、本発明の半導体回路装置システムは、半導体回路装置と、前記半導体回路 装置に電圧を供給する電源装置とを備え、前記半導体回路装置は、第 1導電型の半 導体基板と、前記第 1導電型とは異なる第 2導電型のトランジスタが形成された第 1導 電型の第 1の拡散領域と、第 1導電型のトランジスタが形成された第 2導電型の第 2の 拡散領域と、前記電源装置から第 1極性のバックバイアス電圧が印加される第 1導電 型の第 3の拡散領域と、前記電源装置力 前記第 1極性とは異なる第 2極性のバック バイアス電圧が印加される第 2導電型の第 4の拡散領域とを有することを特徴とする 半導体回路装置システムであることを特徴とする。また、前記半導体回路装置におい て、前記第 1導電型の第 1の拡散領域と、前記第 2導電型の第 2の拡散領域は、トラ ンジスタの配置領域を形成し、前記配置領域内に形成された、前記トランジスタに電 圧を供給するための第 1の電源端子と、前記第 3の拡散領域に形成された、前記第 3 の拡散領域力も前記第 1の拡散領域に対する前記第 1極性のバックバイアス電圧を 印加するための第 2の電源端子と、前記第 4の拡散領域に形成された、前記第 4の拡 散領域力も前記第 2の拡散領域に対する前記第 2極性のバックバイアス電圧を印加 するための第 3の電源端子とを有することを特徴とする。次に、本発明の半導体回路 装置の製造方法は、第 1導電型の半導体基板上に第 2導電型の第 4の拡散領域を 形成するステップと、 Next, a semiconductor circuit device system of the present invention includes a semiconductor circuit device and a power supply device that supplies a voltage to the semiconductor circuit device. The semiconductor circuit device includes a first conductivity type semiconductor substrate, the first A first conductivity type first diffusion region in which a second conductivity type transistor different from the first conductivity type is formed; and a second conductivity type second diffusion region in which the first conductivity type transistor is formed; The first conductivity is applied with the back bias voltage of the first polarity from the power supply device. A third diffusion region of a mold and a fourth diffusion region of a second conductivity type to which a back bias voltage having a second polarity different from the first polarity is applied. It is a circuit device system. Further, in the semiconductor circuit device, the first conductivity type first diffusion region and the second conductivity type second diffusion region form a transistor arrangement region and are formed in the arrangement region. A first power supply terminal for supplying a voltage to the transistor, and the third diffusion region force formed in the third diffusion region also has the first polarity with respect to the first diffusion region. A second power supply terminal for applying a back bias voltage and the fourth diffusion region force formed in the fourth diffusion region also have a back bias voltage of the second polarity with respect to the second diffusion region. And a third power supply terminal for applying voltage. Next, a method for manufacturing a semiconductor circuit device of the present invention includes the step of forming a second conductivity type fourth diffusion region on a first conductivity type semiconductor substrate;
前記第 4の拡散領域内に第 1導電型の第 3の拡散領域を形成するステップと、 前記第 3拡散領域内に第 1導電型の第 1の拡散領域と第 2導電型の第 2の拡散領域 とを形成するステップを有することを特徴とする。また、前記半導体回路装置の製造 方法はさらに、前記第 1の拡散領域上に第 2導電型のトランジスタを形成するとともに 、前記第 2の拡散領域上に第 1導電型のトランジスタを形成するステップと、前記第 3 の拡散領域上に第 1極性のバックバイアス電圧を印加するための電源端子を形成す るとともに、前記第 4の拡散領域上に前記第 1極性とは異なる第 2極性のノ ックバィァ ス電圧を印加するための電源端子を形成するステップを有するようにしてもよい。 次に、本発明の半導体回路装置は、第 1導電型の半導体基板と、前記第 1導電型と は異なる第 2導電型のトランジスタが形成された第 1導電型の第 1の拡散領域と、第 1 導電型のトランジスタが形成された第 2導電型の第 2の拡散領域と、第 1極性のバック バイアス電圧が印加される第 i導電型の第 3の拡散領域とを有することを特徴とする。 発明の効果 Forming a first conductivity type third diffusion region in the fourth diffusion region; and a first conductivity type first diffusion region and a second conductivity type second in the third diffusion region. And a step of forming a diffusion region. The method for manufacturing the semiconductor circuit device further includes forming a second conductivity type transistor on the first diffusion region and forming a first conductivity type transistor on the second diffusion region; Forming a power supply terminal for applying a back-bias voltage of the first polarity on the third diffusion region and a second-polarity knock bias different from the first polarity on the fourth diffusion region; A step of forming a power supply terminal for applying a source voltage may be included. Next, a semiconductor circuit device of the present invention includes a first conductivity type semiconductor substrate, a first conductivity type first diffusion region in which a second conductivity type transistor different from the first conductivity type is formed, and A second conductivity type second diffusion region in which a first conductivity type transistor is formed; and an i th conductivity type third diffusion region to which a back bias voltage of the first polarity is applied. To do. The invention's effect
本発明によれば、以下の少なくともいずれ力 1つの効果ないし利点がある。  The present invention has at least one of the following effects or advantages.
(1)配線を削減することができ、電源配線領域を小さくすることにより、通常のロジッ ク回路の配置領域を確保して高密度化することができる。 (2)特別なコンタクトを形成することなくゥエルの制御を行なうことができ、高密度化 することができるとともに製造コストを低減することができる。 (1) Wiring can be reduced, and by reducing the power supply wiring area, it is possible to secure a normal logic circuit arrangement area and increase the density. (2) It is possible to control the well without forming a special contact, and the density can be increased and the manufacturing cost can be reduced.
図面の簡単な説明  Brief Description of Drawings
[0017] [図 1]本発明の第 1実施形態としての半導体回路装置の構成を模式的に示す側断面 図である。  FIG. 1 is a side sectional view schematically showing a configuration of a semiconductor circuit device as a first embodiment of the present invention.
[図 2]本発明の第 1実施形態としての半導体回路装置の配線状態を説明するための 平面図である。  FIG. 2 is a plan view for explaining a wiring state of the semiconductor circuit device as the first embodiment of the present invention.
[図 3]本発明の第 1実施形態としての半導体回路装置におけるゥエル配置を説明す るための平面図である。  FIG. 3 is a plan view for explaining a well arrangement in the semiconductor circuit device as the first embodiment of the present invention.
圆 4]本発明の第 1実施形態の半導体回路装置の変形例の構成を模式的に示す側 断面図である。  FIG. 4 is a side sectional view schematically showing a configuration of a modification of the semiconductor circuit device according to the first embodiment of the present invention.
[図 5]本発明の第 1実施形態の変形例としての半導体回路装置におけるゥエル配置 を説明するための平面図である。  FIG. 5 is a plan view for explaining a well arrangement in a semiconductor circuit device as a modification of the first embodiment of the present invention.
[図 6]本発明の第 2実施形態の半導体回路装置の構成を模式的に示す側断面図で ある。  FIG. 6 is a side sectional view schematically showing a configuration of a semiconductor circuit device according to a second embodiment of the present invention.
[図 7]本発明の第 1実施形態の半導体回路装置の変形例の構成を模式的に示す側 断面図である。  FIG. 7 is a side sectional view schematically showing a configuration of a modified example of the semiconductor circuit device according to the first embodiment of the present invention.
[図 8]従来の半導体回路装置におけるバックバイアス制御手法を説明するための図 である。  FIG. 8 is a diagram for explaining a back bias control method in a conventional semiconductor circuit device.
[図 9]従来の半導体回路装置におけるバックバイアス制御手法を説明するための図 である。  FIG. 9 is a diagram for explaining a back bias control method in a conventional semiconductor circuit device.
[図 10]従来の半導体回路装置におけるバックバイアス制御手法を説明するための図 である。  FIG. 10 is a diagram for explaining a back bias control method in a conventional semiconductor circuit device.
[図 11]本発明の一実施形態としての半導体回路装置システムの構成を模式的に示 す図である。  FIG. 11 is a diagram schematically showing a configuration of a semiconductor circuit device system as one embodiment of the present invention.
符号の説明  Explanation of symbols
[0018] la, lb, lc, Id 半導体回路装置 [0018] la, lb, lc, Id Semiconductor circuit device
10 P型基板 (半導体基板） 11, 11 - 1 第 IN型ゥエル (第 2の拡散領域） 10 P-type substrate (semiconductor substrate) 11, 11-1 IN type wel (second diffusion region)
11 - 2 第 1N型ゥエル  11-2 Type 1 N-well
12 第 2N型ゥエル (第 4の拡散領域）  12 2nd N-type (fourth diffusion region)
13. 13- 1 第 1P型ゥエル (第 1の拡散領域）  13. 13-1 1st P-type wel (first diffusion region)
13- 2 第 1P型ゥエル  13-2 Type 1 P-well
14. 14- 1 第 2P型ゥエル (第 3の拡散領域）  14. 14-1 Second Pwell (Third Diffusion Area)
14- 2 第 2P型ゥエル  14-2 Type 2P Well
17, 18, 141, 123 コンタクト（電源端子）  17, 18, 141, 123 Contact (Power supply terminal)
30a, 30b, 30d インバータ  30a, 30b, 30d inverter
22- 1, 22- 2, 22- 3, 22-4, 22- 5, 25, 26, 261 P+領域（電源端子） 22- 1, 22- 2, 22- 3, 22-4, 22- 5, 25, 26, 261 P + area (power supply terminal)
21, 23- 1, 23- 2, 23— 3, 24 N+領域（電源端子） 21, 23- 1, 23- 2, 23— 3, 24 N + area (power supply terminal)
41 サイト領域  41 Site area
42, 421, 422 電源配線領域  42, 421, 422 Power supply wiring area
43 サイトアレイ部  43 Site array section
200 半導体回路装置システム  200 Semiconductor circuit equipment system
201 電源装置  201 power supply
301, 303 N型卜ランジスタ  301, 303 N type 卜 transistor
302, 304 P型トランジスタ  302, 304 P-type transistor
411 サイ卜  411 Sai
421, 422 電源配線領域  421, 422 Power supply wiring area
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0019] 以下、図面を参照して本発明の実施の形態を説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(A)第 1実施形態の説明  (A) Description of the first embodiment
図 1は本発明の第 1実施形態としての半導体回路装置の構成を模式的に示す側断 面図、図 2はその配線状態を説明するための平面図である。又、図 3は本第 1実施形 態としての半導体回路装置 laにおけるゥエル配置を説明するための平面図であり、 各ゥエルの配置を模式的に示す図である。  FIG. 1 is a side sectional view schematically showing the configuration of the semiconductor circuit device as the first embodiment of the present invention, and FIG. 2 is a plan view for explaining the wiring state. FIG. 3 is a plan view for explaining the arrangement of the wells in the semiconductor circuit device la according to the first embodiment, and schematically shows the arrangement of the respective wells.
[0020] なお、図 2,図 3においては、便宜上、それぞれ半導体回路装置 laにおける一部を 抽出して示している。 2 and 3, for convenience, a part of the semiconductor circuit device la is shown. Extracted and shown.
本発明の第 1実施形態の半導体回路装置（半導体回路装置システム） laは、例え ば、ゲートアレイやスタンダードセル方式等のテクノロジにより構成され、情報処理装 置等において使用されるものであって、図 1に示すように、 P型基板（半導体基板） 10 ,第 1N型ゥエル (第 2の拡散領域） 11,第 1P型ゥエル (第 1の拡散領域） 13,第 2P 型ゥエル (第 3の拡散領域） 14および第 2N型ゥエル (第 4の拡散領域） 12をそなえて 構成され、更に、電源装置 201 (図 11参照）をそなえて構成されている。なお、以下、 半導体回路装置には、デジタル回路を含むものとする。  The semiconductor circuit device (semiconductor circuit device system) la according to the first embodiment of the present invention is configured by a technology such as a gate array or a standard cell method, and is used in an information processing device, for example. As shown in Figure 1, P-type substrate (semiconductor substrate) 10, 1st N-type well (second diffusion region) 11, 1st P-type well (first diffusion region) 13, 2nd P-type well (third A diffusion region) 14 and a second N-type well (fourth diffusion region) 12 are provided, and a power supply device 201 (see FIG. 11) is further provided. Hereinafter, the semiconductor circuit device includes a digital circuit.
[0021] また、本第 1実施形態においては、半導体回路装置 laとして、 CMOS (Complemen tary Metal Oxide Semiconductor)回路であるインバータ回路 30aが形成された例に ついて説明する。 In the first embodiment, an example in which an inverter circuit 30a that is a CMOS (Complementary Metal Oxide Semiconductor) circuit is formed as the semiconductor circuit device la will be described.
P型基板 10は、 P型 (第 1導電型)の導電性を有する半導体基板であって、この P型 基板 10上には、 P型基板 10とは異なる導電型である N型 (第 2導電型)の導電性を 有する第 2N型ゥエル (第 4の拡散領域） 12が形成されている。更に、この第 2N型ゥ エル 12上には、第 1P型ゥエル (第 1の拡散領域） 13,第 1N型ゥエル (第 2の拡散領 域） 11および第 2P型ゥエル (第 3の拡散領域） 14が形成され、第 2N型ゥエル 12が、 これらの第 1P型ゥエル 13,第 1N型ゥエル 11および第 2P型ゥエル 14と P型基板 10 とを電気的に分離している。  The P-type substrate 10 is a semiconductor substrate having P-type (first conductivity type) conductivity. On the P-type substrate 10, an N-type (second type) different from the P-type substrate 10 is used. A second N-type well (fourth diffusion region) 12 having conductivity of the conductivity type is formed. Furthermore, on the second N-type well 12, the first P-type well (first diffusion region) 13, the first N-type well (second diffusion region) 11, and the second P-type well (third diffusion region). ) 14 is formed, and the second N-type well 12 electrically separates the first P-type well 13, the first N-type well 11 and the second P-type well 14 and the P-type substrate 10.
[0022] 第 1N型ゥエル 11は、その表面に（図 1に示す例では上面）に抵抗，コンデンサ，ダ ィオード，トランジスタ等の種々の素子が配置'形成され、 N型の導電性を有して構成 されている。図 1に示す例においては、この第 1N型ゥエル 11上に P型のトランジスタ (P型トランジスタ） 302が形成されており、第 1N型ゥエル 11には、 P+領域 22— 1, 22 —2が形成されるとともに、酸ィ匕膜等（図示省略)を介して絶縁された状態でゲート 32 が形成されており、 P+領域 22— 1には、配線 L 12を介して電源電圧 Vddが供給され るようになっている。なお、以下、図中、符号 Gはゲートを、符号 Dはドレインをそれぞ れ示すものとする。 [0022] The first N-type well 11 is formed with various elements such as resistors, capacitors, diodes, transistors, etc. on its surface (upper surface in the example shown in FIG. 1), and has N-type conductivity. Configured. In the example shown in FIG. 1, a P-type transistor (P-type transistor) 302 is formed on the first N-type well 11, and the P + regions 22-1, 22 -2 are formed in the first N-type well 11. In addition, the gate 32 is formed in an insulated state through an oxide film or the like (not shown). The power supply voltage Vdd is supplied to the P + region 22-1 through the wiring L12. It has become so. In the following figure, the symbol G represents the gate and the symbol D represents the drain.
[0023] 第 1P型ゥエル 13は、その表面に（図 1に示す例では上面）に抵抗，コンデンサ，ダ ィオード，トランジスタ等の種々の素子が形成され、 P型の導電性を有して構成されて いる。図 1に示す例においては、第 1P型ゥエル 13に上に N型のトランジスタ（N型トラ ンジスタ） 301が形成されており、 N+領域 23— 1, 23— 2力 S形成されるととも〖こ、酸ィ匕 膜等（図示省略)を介して絶縁された状態でゲート 31が形成されており、 N+領域 23 —2には配線 L13を介してグランド電圧 Vssが供給されるようになっている。 [0023] The first P-type well 13 has various elements such as resistors, capacitors, diodes, transistors, etc. formed on its surface (upper surface in the example shown in FIG. 1), and has P-type conductivity. Been Yes. In the example shown in FIG. 1, an N-type transistor (N-type transistor) 301 is formed on the first P-type well 13 and an N + region 23-1, 23-2 force S is formed. The gate 31 is formed in an insulated state through an oxide film (not shown), and the ground voltage Vss is supplied to the N + region 23-2 through the wiring L13. Yes.
[0024] このように、本半導体回路装置 laにおいては、第 1N型ゥエル 11および第 1P型ゥ エル 13がトランジスタの配置領域を形成しているのである。  Thus, in the present semiconductor circuit device la, the first N-type well 11 and the first P-type well 13 form a transistor arrangement region.
また、第 1P型ゥエル 13の N+領域 23— 1と第 1N型ゥエル 11の P+領域 22— 2とはド レイン出力（X)として接続され、第 1P型ゥエル 13のゲート 31と第 1N型ゥエル 11の ゲート 32とはゲート入力（A)として接続されている。  The N + region 23-1 of the 1st P-type wel 13 and the P + region 22-2 of the 1st N-type wel 11 are connected as a drain output (X), and the gate 31 of the 1st P-type wel 13 and the 1st N-type wel 11 gate 32 is connected as gate input (A).
[0025] P型基板 10においては、図 2に示すように、矩形形状の複数のサイト 411からなる サイト領域 41と、矩形形状の複数の電源配線領域 421, 422からなる電源配線領域 42とが形成され、その一の方向（図 2に示す例では紙面横方向）において、サイト領 域 41と電源配線領域 42とが交互に配置されている。  In the P-type substrate 10, as shown in FIG. 2, a site region 41 composed of a plurality of rectangular shaped sites 411 and a power supply wiring region 42 composed of a plurality of rectangular power supply wiring regions 421, 422 are provided. In the one direction (in the example shown in FIG. 2, the horizontal direction in the drawing), the site areas 41 and the power supply wiring areas 42 are alternately arranged.
そして、サイト領域 41においては、このサイト領域 41と電源配線領域 42とが交互に 配列された方向（図 2に示す例では紙面横方向）と直交する方向（図 2に示す例では 紙面縦方向）に、第 1N型ゥエル 11と第 1P型ゥエル 13とが交互に繰り返し並べて形 成されている。又、電源配線領域 42においては、サイト領域 41と電源配線領域 42と が交互に配列された方向（図 2に示す例では紙面横方向）と直交する方向（図 2に示 す例では紙面縦方向）に、電源配線領域 421と電源配線領域 422とが交互に繰り返 し並べて形成されている。  In the site region 41, the direction orthogonal to the direction in which the site regions 41 and the power supply wiring regions 42 are alternately arranged (in the example shown in FIG. 2, the horizontal direction in the drawing), the vertical direction in the drawing, in the example shown in FIG. ), The 1st N-type wel 11 and the 1st P-type wel 13 are alternately arranged. Further, in the power supply wiring area 42, the direction perpendicular to the direction in which the site areas 41 and the power supply wiring areas 42 are alternately arranged (the horizontal direction in the example in FIG. 2) (the vertical direction in the example in FIG. 2). Direction), power supply wiring regions 421 and power supply wiring regions 422 are alternately and repeatedly formed.
[0026] すなわち、 P型基板 10においては、矩形形状の複数のサイト 411および電源配線 領域 421, 422がマトリクス状に形成（区画)され、その一の方向（図 2に示す例では 紙面縦方向）に複数のサイト 411が連続して形成されるとともに、他の方向（図 2に示 す例では紙面横方向）においては、サイト 411と電源配線領域 42とが交互に形成さ れている。  That is, in the P-type substrate 10, a plurality of rectangular sites 411 and power supply wiring regions 421 and 422 are formed (partitioned) in a matrix shape, and one direction thereof (in the example shown in FIG. ) And a plurality of sites 411 are formed continuously, and the sites 411 and the power supply wiring regions 42 are alternately formed in the other direction (the horizontal direction in the example shown in FIG. 2).
[0027] 各サイト 411には、それぞれ上述した第 1P型ゥエル 13もしくは第 1N型ゥエル 11が 形成されるようになっており、図 2に示す例においては、 P型基板 10上において、第 1 p型ゥエル 13と第 1N型ゥエル 11と力 紙面縦方向に交互に繰り返し並べて形成さ れている。すなわち、 P型基板 10上において、第 1N型ゥエル 11と第 1P型ゥエル 13 と力 互いに平行もしくはほぼ平行に、マトリクス状に交互に繰り返し並べて形成され ている。 [0027] Each site 411 is formed with the first P-type well 13 or the first N-type well 11 described above. In the example shown in FIG. p-type wel 13 and 1st n-type wel 11 and force It is. In other words, on the P-type substrate 10, the first N-type well 11 and the first P-type well 13 are alternately and repeatedly arranged in a matrix in parallel or substantially in parallel with each other.
[0028] なお、 P型基板 10上における、サイト 411および電源配線領域 421, 422がマトリク ス状に形成された領域全体をサイトマトリクスという場合がある。  [0028] It should be noted that the entire region where the site 411 and the power supply wiring regions 421 and 422 are formed in a matrix on the P-type substrate 10 may be referred to as a site matrix.
電源配線領域 42は、図 2に示すように、第 1N型ゥエル 11に電力を供給する電源 配線領域 421と、第 1P型ゥエル 13に電力を供給する電源配線領域 422とをそなえ て構成されており、第 1N型ゥエル 11に隣接して電源配線領域 421が、又、第 1P型 ゥエル 13に隣接して電源配線領域 422がそれぞれ形成されている。  As shown in FIG. 2, the power supply wiring area 42 includes a power supply wiring area 421 that supplies power to the first N-type wel 11 and a power supply wiring area 422 that supplies power to the first P-type wel 13. A power supply wiring region 421 is formed adjacent to the first N-type well 11, and a power supply wiring region 422 is formed adjacent to the first P-type well 13.
[0029] すなわち、 P型基板 10においては、各サイト 411に隣接して電源配線領域 42がそ れぞれ形成され、サイト 411毎に電源供給が行なわれるようになって 、る。  That is, in the P-type substrate 10, the power supply wiring region 42 is formed adjacent to each site 411, and power is supplied to each site 411.
なお、以下、隣接する第 1N型ゥエル 11,第 1P型ゥエル 13および電源配線領域 4 21, 422によって形成される矩形形状をサイトアレイ部 43という場合がある。  Hereinafter, the rectangular shape formed by the adjacent first N-type well 11, first P-type well 13 and power supply wiring regions 42, 422 may be referred to as a site array portion 43.
そして、第 2N型ゥエル 12は、図 3に示すように、 P型基板 10上において、サイトマト リクス (複数のサイトアレイ部 43)を包含するような領域として形成され、 P型基板 10上 において、この P型基板 10と、第 1N型ゥエル 11,第 1P型ゥエル 13,および第 2P型 ゥエル 14とを電気的に分離するように形成されて 、るのである。  Then, as shown in FIG. 3, the second N-type well 12 is formed on the P-type substrate 10 as a region that includes cytolytics (a plurality of site array portions 43), and on the P-type substrate 10, The P-type substrate 10 and the first N-type well 11, the first P-type well 13, and the second P-type well 14 are formed so as to be electrically separated.
[0030] 第 2P型ゥエル 14は、第 1P型ゥエル 13と少なくとも一部において接することにより電 気的に連通するように配置され、又、この第 2P型ゥエル 14には、 P+領域 (電源端子， コンタクト） 26が形成されている。そして、この P+領域 26には、電源装置 201 (図 11参 照）から第 1極性のノックバイアス電圧 VBBNが印カロ (供給)されるようになつている。  [0030] The second P-type well 14 is disposed so as to be in electrical communication with at least a portion of the first P-type well 13 and is connected to the P + region (power supply terminal). , Contact) 26 is formed. The P + region 26 is supplied with the first polarity knock bias voltage VBBN from the power supply device 201 (see FIG. 11).
[0031] また、第 2N型ゥエル 12においては、 N+領域 (電源端子，コンタクト） 21が形成され ており、この N+領域 21には、電源装置 201 (図 11参照）から、上記第 1極性とは異な る第 2極性のノックバイアス電圧 VBBPが印加 (供給)されるようになって 、る。  [0031] Further, in the second N-type well 12, an N + region (power supply terminal, contact) 21 is formed. In the N + region 21, the power supply device 201 (see FIG. 11) receives the first polarity and the first polarity. The knock bias voltage VBBP having a different second polarity is applied (supplied).
電源配線領域 42における、 N型トランジスタ 301や P型トランジスタ 302が形成され た層とは異なる層として形成された電源配線メタル第 2層には、図 2に示すように、電 源配線領域 421, 422の配列方向（図 2中では紙面縦方向）に沿って、配線 L12と配 線 L13とが平行に形成されている。 [0032] また、 P型基板 10における、電源配線メタル第 2層よりも下位であって、 N型トランジ スタ 301や P型トランジスタ 302が形成された層とは異なる層として形成された電源配 線メタル第 1層においては、上述した電源配線メタル第 2層において配線 L 12, L13 が形成された方向と直行する方向（図 2中では紙面横方向）に、配線 L12, L13が形 成されている。 In the power supply wiring region 42, the power supply wiring metal second layer formed as a layer different from the layer in which the N-type transistor 301 and the P-type transistor 302 are formed has a power supply wiring region 421, The wiring L12 and the wiring L13 are formed in parallel along the arrangement direction 422 (the vertical direction in FIG. 2). In addition, the power supply wiring formed as a layer lower than the power supply wiring metal second layer in the P-type substrate 10 and different from the layer in which the N-type transistor 301 and the P-type transistor 302 are formed. In the first metal layer, the wirings L12 and L13 are formed in the direction perpendicular to the direction in which the wirings L12 and L13 are formed in the second power supply metal layer (the horizontal direction in FIG. 2). Yes.
[0033] なお、図 2に示す例においては、第 1N型ゥエル 11に重なるように、この第 1N型ゥ エル 11の長手方向に沿って配線 L12が形成され、第 1P型ゥエル 13に重なるように 、この第 1P型ゥエル 13の長手方向に沿って配線 L13が形成されている。又、電源配 線メタル第 1層カゝら電源配線メタル第 2層にかけて形成されたコンタクト 17により、電 源配線メタル第 1層における配線 L12が電源配線メタル第 2層の配線 L12と電気的 に接続されている。  In the example shown in FIG. 2, a wiring L 12 is formed along the longitudinal direction of the first N-type well 11 so as to overlap the first N-type well 11, and overlaps the first P-type well 13. In addition, a wiring L13 is formed along the longitudinal direction of the first P-type well 13. In addition, the contact 17 formed from the first layer of the power distribution metal to the second layer of the power wiring metal causes the wiring L12 in the first layer of the power wiring metal to be electrically connected to the wiring L12 of the second layer of the power wiring metal. It is connected.
[0034] 同様にして、電源配線メタル第 1層から電源配線メタル第 2層にかけて形成されたコ ンタクト 18により、電源配線メタル第 1層における配線 L13が電源配線メタル第 2層の 配線 L 13と電気的に接続されて!、る。  [0034] Similarly, due to the contact 18 formed from the first layer of the power wiring metal to the second layer of the power wiring metal, the wiring L13 in the first layer of the power wiring metal is connected to the wiring L 13 of the second layer of the power wiring metal. Electrically connected!
また、図 2に示すように、例えば、配線 L12はサイト 411における紙面上側に寄せて 、その端に沿って形成されるとともに、配線 L13はサイト 411における紙面下型に寄 せて、その端に沿って形成されており、コンタクト 17, 18もサイト 411の端部に寄せて 形成されている。  In addition, as shown in FIG. 2, for example, the wiring L12 is formed along the edge of the site 411 at the upper side of the paper, and the wiring L13 is placed near the lower mold of the paper at the site 411. The contacts 17 and 18 are also formed close to the end of the site 411.
[0035] 第 2P型ゥエル 14は、サイトアレイ部 43を形成する第 1N型ゥエル 11,第 1P型ゥェ ル 13および電源配線領域 421, 422に、少なくとも一部において接するように配置' 形成されている。  [0035] The second P-type well 14 is disposed and formed so as to be in contact with at least a part of the first N-type well 11, the first P-type well 13 and the power supply wiring regions 421 and 422 forming the site array unit 43. ing.
本第 1実施形態の半導体回路装置 laにおいては、図 3に示すように、第 2P型ゥェ ル 14が平面細長状に形成され、その長手方向（図 3では紙面縦方向）において、第 1N型ゥエル 11や第 1P型ゥエル 13の長手方向（図 3では紙面横方向）とそれぞれ所 定の角度（90度もしくはほぼ 90度)で交差 (直交)するように配置 ·形成されており、 図 3に示すように、一の第 2P型ゥエル 14力 その長手方向において複数のサイトァ レイ部 43と交差 ·接触するように形成されて!、る。  In the semiconductor circuit device la of the first embodiment, as shown in FIG. 3, the second P-type well 14 is formed in a plane elongated shape, and in the longitudinal direction (the vertical direction in FIG. 3), the first N It is arranged and formed so that it intersects (orthogonally) at a predetermined angle (90 degrees or almost 90 degrees) with the longitudinal direction of the mold wel 11 and the first P wel 13 (lateral direction in FIG. 3). As shown in FIG. 3, one second P-type well 14 force is formed so as to cross and contact with a plurality of site array parts 43 in the longitudinal direction.
[0036] また、本第 1実施形態の半導体回路装置 laにおいては、図 3に示すように、第 1N 型ゥエル 11と第 2N型ゥエル 12とが所定の角度（90度もしくはほぼ 90度)で交差 (直 交)するように配置 '形成されており、又、第 2N型ゥエル 12の長手方向と第 2P型ゥェ ル 14の長手方向とが所定の角度（90度もしくはほぼ 90度)で交差 (直交)するように 配置，形成されている。 In addition, in the semiconductor circuit device la of the first embodiment, as shown in FIG. The mold wel 11 and the second N-type wel 12 are arranged so that they intersect (directly intersect) at a predetermined angle (90 degrees or almost 90 degrees). It is arranged and formed so that the longitudinal direction of the 2P-type well 14 intersects (orthogonally) at a predetermined angle (90 degrees or almost 90 degrees).
[0037] 本第 1実施形態の半導体回路装置 laは、第 2N型ゥエル 12,第 2P型ゥエル 14お よび第 1N型ゥエル 11 (もしくは第 1P型ゥエル 13)による 3重ゥエル構造をそなえてい るといえる。  [0037] The semiconductor circuit device la according to the first embodiment has a triple wel structure including the second N-type wel 12, the second P-type wel 14 and the first N-type wel 11 (or the first P-type wel 13). It can be said.
なお、図 3に示す例においては、平面細長状に形成された第 2P型ゥエル 14と第 1 N型ゥエル 11や第 1P型ゥエル 13とは、 90度もしくはほぼ 90度の角度を有して交差 ( 直交）している力 これに限定されるものではなぐ第 2P型ゥエル 14は、第 1N型ゥェ ル 11や第 1P型ゥエル 13に対して、それぞれ、少なくとも部分的に当接 (重合)するよ うに形成されていればよぐ例えば、第 1N型ゥエル 11や第 1P型ゥエル 13に対して 9 0度以外の角度で交差してもよぐその配置位置や形状については種々変形して実 施することができる。  In the example shown in FIG. 3, the second P-type well 14 and the first N-type well 11 and the first P-type well 13 formed in a plane elongated shape have an angle of 90 degrees or almost 90 degrees. Crossing (orthogonal) force The second P-type well 14 is not limited to this, but at least partially abuts against the first N-type well 11 and the first P-type well 13 (polymerization). For example, the position and shape of the 1N-type wel 11 and the 1P-type wel 13 that intersect at an angle other than 90 degrees may be variously modified. Can be implemented.
[0038] また、第 2P型ゥエル 14におけるサイトアレイ部 43と重合しない領域、すなわち、第 2P型ゥエル 14におけるサイトマトリクスの外側（外周部分）には、この第 2P型ゥエル 1 4にバックバイアス電圧 VBBNを供給するメタル層（図示省略）と第 2P型ゥエル 14と を電気的に接続するコンタクト 141が形成されており、更に、このコンタクト 141には 電源装置 201 (図 11参照）が接続されて!、る。  [0038] Further, a back bias voltage is applied to the second P-type well 14 in a region that does not overlap with the site array portion 43 in the second P-type well 14, that is, outside the site matrix in the second P-type 14 (outer peripheral portion). A contact 141 for electrically connecting the metal layer (not shown) for supplying VBBN and the second P-type well 14 is formed, and a power supply device 201 (see FIG. 11) is connected to the contact 141. !
[0039] これにより、この電源装置 201から供給される第 1極性のバックバイアス電圧 VBBN 力 Sコンタクト 141を介して第 2P型ゥエル 14に印加されるようになっている。すなわち、 このコンタクト 141力 図 1における P+領域 26に相当するものである。  Thus, the first polarity back bias voltage VBBN supplied from the power supply device 201 is applied to the second P-type well 14 via the S contact 141. That is, this contact 141 force corresponds to the P + region 26 in FIG.
また、第 2N型ゥエル 12における、サイトアレイ部 43や第 2P型ゥエル 14のいずれと も重合しない領域、すなわち、第 2N型ゥエル 12におけるサイトマトリクスおよび第 2P 型ゥエル 14の外側（外周部分）には、この第 2N型ゥエル 12にバックバイアス電圧 V BBPを供給するメタル層（図示省略）と第 2N型ゥエル 12とを電気的に接続するコン タクト 123が形成されており、更に、このコンタクト 123には電源装置 201 (図 11参照） が接続されている。 [0040] これにより、この電源装置 201から供給される第 2極性のバックバイアス電圧 VBBP 力 Sコンタクト 123を介して第 2P型ゥエル 12に印加されるようになっており、このコンタ タト 123力 図 1における N+領域 21に相当するものである。 Also, in the second N-type wel 12, the region that does not overlap with either the site array part 43 or the second P-type wel 14, that is, on the outside (outer peripheral part) of the site matrix in the second N-type wel 12 and the second P-type wel 14. A contact layer 123 for electrically connecting the metal layer (not shown) for supplying the back bias voltage V BBP to the second N-type well 12 and the second N-type well 12 is formed. A power supply device 201 (see FIG. 11) is connected to. As a result, the second polarity back bias voltage VBBP supplied from the power supply device 201 is applied to the second P-type well 12 via the S contact 123. This corresponds to N + region 21 in 1.
すなわち、第 1 P型ゥエル 13へのバックバイアス電圧 VBBNの印加は第 2P型ゥェ ル 14を介して行なわれ、又、第 1N型ゥエル 11へのバックバイアス電圧 VBBPの印 加は第 2N型ゥエル 12を介して行なわれるのである。  In other words, the back bias voltage VBBN is applied to the first P-type well 13 via the second P-type well 14, and the back bias voltage VBBP to the first N-type well 11 is applied to the second N-type well 14. It is done through uel 12.
[0041] また、本第 1実施形態の半導体回路装置 laは、例えば、 P型基板 10に第 2N型ゥ エル 12を形成させた後に、第 2P型ゥエル 14を成長させ、その後、第 1N型ゥエル 11 および第 1P型ゥエル 13を形成させ、その後、トランジスタのバルタ (BULK)製造工程 や、各電源端子や配線の製造工程等を行なうことにより、本半導体回路装置 laを製 造することができる。  In addition, the semiconductor circuit device la of the first embodiment, for example, after the second N-type well 12 is formed on the P-type substrate 10, the second P-type well 14 is grown, and then the first N-type The semiconductor circuit device la can be manufactured by forming the wel 11 and the first P-type wel 13 and then performing a transistor bulking process (BULK) manufacturing process, a process for manufacturing each power supply terminal and wiring, and the like. .
[0042] 上述の如く構成された本発明の第 1実施形態としての半導体回路装置 laによれば 、第 2P型ゥエル 14におけるサイトアレイ部 43不在の領域において、コンタクト 141 (P +領域 26)から第 2P型ゥエル 14にバックバイアス電圧 VBBNが印加されるとともに、 第 2N型ゥエル 12におけるサイトアレイ部 43および第 2P型ゥエル 14不在の領域に おいて、コンタクト 123 (N+領域 21)力 第 2N型ゥエル 12にバックバイアス電圧 VBB Pが印加される。  According to the semiconductor circuit device la as the first embodiment of the present invention configured as described above, in the region where the site array portion 43 is absent in the second P-type well 14, the contact 141 (P + region 26) The back bias voltage VBBN is applied to the second P-type well 14 and the contact 123 (N + region 21) force is applied to the second N-type well 12 in the region where the site array part 43 and the second P-type well 14 are absent. The back bias voltage VBB P is applied to the wel 12.
[0043] そして、第 1N型ゥエル 11および第 1P型ゥエル 13に形成されたインバータ回路 30 aにおいては、電源装置 201から P+領域 26を介して印加されるバックバイアス電圧 V BBNにより、第 2P型ゥエル 14および第 1P型ゥエル 13を経由して Nチャンネル MO S (NMOS)トランジスタが制御されるとともに、電源装置 201から N+領域 21を介して 供給されるバックバイアス電圧 VBBPにより、第 2N型ゥエル 12および第 1N型ゥエル 11を経由して Pチャンネル MOS (PMOS)トランジスタが制御されることにより、イン バータ回路 30aのバックノ ィァス制御が行なわれる。  [0043] In the inverter circuit 30a formed in the first N-type wel 11 and the first P-type wel 13, the second P-type is supplied by the back bias voltage V BBN applied from the power supply device 201 through the P + region 26. The N-channel MOS (NMOS) transistor is controlled via the well 14 and the first P-type well 13, and the second N-type well 12 is supplied by the back bias voltage VBBP supplied from the power supply 201 via the N + region 21. Further, by controlling the P-channel MOS (PMOS) transistor via the first N-type well 11, the back noise control of the inverter circuit 30a is performed.
[0044] このバックバイアス制御においては、具体的には、トランジスタ直下のゥエル電圧を NMOSであれば Pゥエルをマイナスへ、 PMOSであれば Nゥエルをプラスへ、逆バイ ァス電圧を印加するようになって!/、る。  [0044] In this back bias control, specifically, the reverse bias voltage is applied so that the pell is directly minus if the well voltage just below the transistor is NMOS, and the nwell is plus if PMOS. Become! /
このように、本発明の第 1実施形態としての半導体回路装置 laによれば、電源配線 領域 42 (電源配線領域 421, 422)において、バックバイアス電圧 VBBN, VBBPを 供給するための配線やコンタクト等を配置 ·形成する必要がなく、配線数を削減する ことにより電源配線領域 42 (電源配線領域 421, 422)の占有面積を低減することが でき、半導体回路装置 laを高密度化することができる。又、配線チャネルの増加を行 なうことができる。 Thus, according to the semiconductor circuit device la as the first embodiment of the present invention, the power supply wiring In area 42 (power supply wiring areas 421 and 422), it is not necessary to arrange and form wiring and contacts to supply the back bias voltages VBBN and VBBP. The area occupied by the regions (421, 422) can be reduced, and the density of the semiconductor circuit device la can be increased. In addition, the number of wiring channels can be increased.
[0045] また、電源配線領域 42 (電源配線領域 421, 422)にお!/、て、バックバイアス電圧 V BBN, VBBPを印カロ'供給するためのコンタクト等がないので、この電源配線領域 42 において、例えば、メタル層よりも下層にトランジスタ等のロジック回路を配置 '形成す ることができ、これによつても、半導体回路装置 laを高密度化することができる。  In addition, since there is no contact or the like for supplying back bias voltages V BBN and VBBP to the power wiring area 42 (power wiring areas 421 and 422), the power wiring area 42 In this case, for example, a logic circuit such as a transistor can be arranged and formed below the metal layer, and this can also increase the density of the semiconductor circuit device la.
[0046] また、サイト 411においてコンタクト 17, 18を端部に寄せて形成することにより、スぺ ース効率が向上する。 In addition, by forming the contacts 17 and 18 close to the ends at the site 411, the space efficiency is improved.
そして、ノ ックバイアス制御を行なうことにより、リーク電流を減少させ消費電力を低 減することができる。  By performing the knock bias control, the leakage current can be reduced and the power consumption can be reduced.
(B)第 1実施形態の変形例の説明  (B) Description of a modification of the first embodiment
上述した第 1実施形態に力かる半導体回路装置 laにおいては、第 2P型ゥエル 14 を介してバックバイアス電圧 VBBNを印加するとともに、第 2N型ゥエル 12を介してバ ックバイアス電圧 VBBPを印加することにより、インバータ回路 30aにおいて、 NMOS トランジスタと PMOSトランジスタとのいずれに対してもバックバイアス制御を行なって いるが、これに限定されるものではなぐこれらの P型基板 10上に形成された NMOS トランジスタおよび PMOSトランジスタのうちいずれか一方に対してのみゥエルを介し たバックバイアス電圧の印加を行なってもよ 、。  In the semiconductor circuit device la according to the first embodiment described above, the back bias voltage VBBN is applied via the second P-type well 14 and the back bias voltage VBBP is applied via the second N-type well 12. In the inverter circuit 30a, the back bias control is performed for both the NMOS transistor and the PMOS transistor, but the present invention is not limited to this. The NMOS transistor and the PMOS formed on the P-type substrate 10 are not limited thereto. Only one of the transistors may be applied with a back bias voltage through the well.
[0047] 図 4は本発明の第 1実施形態の半導体回路装置の変形例の構成を模式的に示す 側断面図、図 5は本第 1実施形態の変形例としての半導体回路装置 lbにおけるゥェ ル配置を説明するための平面図である。なお、図 5においては、便宜上、半導体回 路装置 lbにおける一部を抽出して示している。 FIG. 4 is a side sectional view schematically showing a configuration of a modified example of the semiconductor circuit device according to the first embodiment of the present invention. FIG. 5 is a side view of the semiconductor circuit device lb as a modified example of the first embodiment. FIG. 6 is a plan view for explaining a cell arrangement. In FIG. 5, for convenience, a part of the semiconductor circuit device lb is extracted and shown.
本第 1実施形態の変形例としての半導体回路装置 lbも、第 1実施形態の半導体回 路装置 laと同様に、例えば、ゲートアレイやスタンダードセル方式等のテクノロジによ り構成され、情報処理装置等において使用されるものである。 [0048] 以下、本第 1実施形態の変形例としての半導体回路装置 lbとして、 CMOS回路で あるインバータ回路 30bが形成された例について説明する。 Similarly to the semiconductor circuit device la of the first embodiment, the semiconductor circuit device lb as a modified example of the first embodiment is configured by, for example, a technology such as a gate array or a standard cell system. Etc. are used. Hereinafter, an example in which an inverter circuit 30b that is a CMOS circuit is formed as a semiconductor circuit device lb as a modification of the first embodiment will be described.
半導体回路装置 lbは、図 4に示すように、 P型基板 (半導体基板） 10,第 1N型ゥェ ル (第 2の拡散領域） 11,第 1P型ゥエル (第 1の拡散領域） 13および第 2N型ゥエル（ 第 4の拡散領域） 12をそなえて構成され、第 1極性のノ ックバイアス電圧 VBBNが電 源装置 201 (図 11参照)から P+領域 (電源端子） 261に印加されるとともに、第 1極性 とは異なる第 2極性のバックバイアス電圧 VBBP力 電源装置 201 (図 11参照）から 第 2N型ゥエル 12に形成された N+領域 (電源端子） 21を介して供給されるようになつ ている。  As shown in FIG. 4, the semiconductor circuit device lb includes a P-type substrate (semiconductor substrate) 10, a first N-type well (second diffusion region) 11, a first P-type well (first diffusion region) 13 and A second N-type well (fourth diffusion region) 12 is configured, and a first polarity knock bias voltage VBBN is applied from the power supply 201 (see FIG. 11) to the P + region (power supply terminal) 261. Back bias voltage with a second polarity different from the first polarity VBBP force The power is supplied from the power supply 201 (see Fig. 11) via the N + region (power terminal) 21 formed in the second N-type well 12. Yes.
[0049] なお、図中、既述の符号と同一の符号は同一もしくは略同一の部分を示しているの で、その詳細な説明は省略する。  [0049] In the figure, the same reference numerals as those already described indicate the same or substantially the same parts, and detailed description thereof will be omitted.
本第 1実施形態の変形例としての半導体回路装置 lbにおいては、 P型 (第 1導電 型)の導電性を有する P型基板 10上に、 N型 (第 2導電型)の導電性を有する第 2N 型ゥエル 12が形成され、更に、この第 2N型ゥエル 12上には、第 1P型ゥエル 13およ び第 1N型ゥエル 11が形成され、第 2N型ゥエル 12が、これらの第 1P型ゥエル 13お よび第 1N型ゥエル 11と P型基板 10とを電気的に分離している。  The semiconductor circuit device lb as a modification of the first embodiment has N-type (second conductivity type) conductivity on a P-type substrate 10 having P-type (first conductivity type) conductivity. A second N-type wel 12 is formed, and on the second N-type wel 12, a first P-type wel 13 and a first N-type wel 11 are formed. The wel 13 and the first N-type wel 11 and the P-type substrate 10 are electrically separated.
[0050] 図 4に示す例においては、この第 1N型ゥエル 11上に P型のトランジスタ（P型トラン ジスタ） 302が形成されている。又、第 1P型ゥエル 13上には、 N型のトランジスタ（P 型トランジスタ） 301が形成されており、 N+領域 23— 1, 23- 2,ゲート 31が形成され るとともに、 P+領域 261が形成され、この P+領域 261〖こ、電源装置 201 (図 11参照）か らメタル配線（図示省略)を介してノックバイアス電圧 VBBNが印加されるようになつ ている。又、 N+領域 23— 2には、電源装置 201 (図 11参照）から配線 L13を介してグ ランド電圧 Vssが供給されるようになって 、る。  In the example shown in FIG. 4, a P-type transistor (P-type transistor) 302 is formed on the first N-type well 11. An N-type transistor (P-type transistor) 301 is formed on the first P-type well 13, and N + regions 23-1, 23-2 and 31 are formed, and a P + region 261 is formed. The knock bias voltage VBBN is applied from the power supply device 201 (see FIG. 11) through the metal wiring (not shown) from the P + region 261. Further, the ground voltage Vss is supplied to the N + region 23-2 from the power supply device 201 (see FIG. 11) via the wiring L13.
[0051] このように、本半導体回路装置 lbにおいても、第 1N型ゥエル 11および第 1P型ゥ エル 13がトランジスタの配置領域を形成しているのである。  [0051] Thus, also in the present semiconductor circuit device lb, the first N-type well 11 and the first P-type well 13 form a transistor arrangement region.
また、第 2N型ゥエル 12は、図 5に示すように、 P型基板 10上において、サイトマトリ タス (複数のサイトアレイ部 43)を包含するような領域として形成され、 P型基板 10上 において、この P型基板 10と、第 1N型ゥエル 11および第 1P型ゥエル 13とを電気的 に分離するように形成されて ヽる。 Further, as shown in FIG. 5, the second N-type well 12 is formed on the P-type substrate 10 as a region including the cytomatrix (a plurality of site array portions 43). This P-type substrate 10 is electrically connected to the 1st N-type well 11 and the 1st P-type well 13 It is formed so as to be separated.
[0052] すなわち、本第 1実施形態の変形例としての半導体回路装置 lbにおいては、第 1 実施形態の半導体回路装置 laにおける第 2P型ゥエル 14をそなえずに構成されると ともに、 P+領域 261をそなえ、この P+領域 261に、電源装置 201からバックバイアス電 圧 VBBNカ タル配線（図示省略)を介して印加される他は、第 1実施形態の半導体 回路装置 laとほぼ同様に構成されている。  That is, the semiconductor circuit device lb as a modification of the first embodiment is configured without the second P-type well 14 in the semiconductor circuit device la of the first embodiment, and the P + region 261 The P + region 261 is configured in substantially the same manner as the semiconductor circuit device la of the first embodiment except that it is applied from the power supply device 201 via the back bias voltage VBBN cathodic wiring (not shown). Yes.
[0053] これにより、本第 1実施形態の変形例としての半導体回路装置 lbにおいては、電 源装置 201から P+領域 261を介して印加されるバックバイアス電圧 VBBNや，電源 装置 201から N+領域 21を介して印加されるバックバイアス電圧 VBBPによりバックバ ィァス制御が行なわれるものであって、 Pチャンネル MOS (PMOS)トランジスタのみ が第 2N型ゥエル 12および第 1N型ゥエル 11を介したバックバイアス制御を行なわれ るようになっている。  Thus, in the semiconductor circuit device lb as a modified example of the first embodiment, the back bias voltage VBBN applied from the power supply device 201 via the P + region 261, or the power supply device 201 to the N + region 21. Back bias control is performed by the back bias voltage VBBP applied via the PB, and only the P-channel MOS (PMOS) transistor performs the back bias control via the second N-type well 12 and the first N-type well 11. It has come to be.
[0054] また、このバックバイアス制御は、具体的には、トランジスタ直下のゥエル電圧を N MOSであれば Pゥエルをマイナスへ、 PMOSであれば Nゥエルをプラスへ、逆バイァ スを印加することにより行なう。  [0054] Further, this back-bias control is specifically applied by applying a reverse bias to the P-well when the NMOS voltage is just below the transistor is N MOS, and to the N-well plus when the PMOS is PMOS. To do.
なお、本第 1実施形態の変形例としての半導体回路装置 lbは、第 2N型ゥエル 12 および第 1N型ゥエル 11 (もしくは第 1P型ゥエル 13)による 2重ゥエル構造をそなえて いるといえる。  In addition, it can be said that the semiconductor circuit device lb as a modification of the first embodiment has a double-well structure by the second N-type wel 12 and the first N-type wel 11 (or the first P-type wel 13).
[0055] また、本第 1実施形態の変形例としての半導体回路装置 lbは、例えば、 P型基板 1 0に第 2N型ゥエル 12を形成させた後に、第 1N型ゥエル 11および第 1P型ゥエル 13 を形成させ、その後、トランジスタのノ レク製造工程や各電源端子や配線の製造ェ 程を行なうことにより製造することができる。  Further, the semiconductor circuit device lb as a modification of the first embodiment includes, for example, the first N-type well 11 and the first P-type well after the second N-type well 12 is formed on the P-type substrate 10. 13 is formed, and then the transistor is manufactured by the process of manufacturing the transistor and the process of manufacturing each power supply terminal and wiring.
上述の如く構成された本発明の第 1実施形態の変形例としての半導体回路装置 lb によっても、第 2N型ゥエル 12におけるサイトアレイ部 43 (図 2,図 3参照）不在の領域 において電源装置 201から N+領域 21を介して第 2N型ゥエル 12に印加されるバック バイアス電圧 VBBPと、電源装置 201から P+領域 261に印加されるバックバイアス電 圧 VBBNとにより、インバータ回路 30bのバックバイアス制御が行なわれる。  Even with the semiconductor circuit device lb as a modification of the first embodiment of the present invention configured as described above, the power supply device 201 in the region where the site array portion 43 (see FIGS. 2 and 3) is absent in the second N-type well 12. The back bias voltage VBBP applied to the second N-type well 12 from the N + region 21 to the P + region 261 from the power supply unit 201 is controlled by the back bias voltage VBBN applied to the second N-type well 12 from the power supply device 201. It is.
[0056] このように、本発明の第 1実施形態としての半導体回路装置 lbによれば、電源配線 領域 42 (電源配線領域 421, 422)において、ノックバイアス電圧 VBBPを供給する ための配線やコンタクト等を配置 '形成する必要がなぐ配線数を削減することにより 電源配線領域 42 (電源配線領域 421, 422)の占有面積を低減することができ、半 導体回路装置 lbを高密度化することができる。又、配線チャネルの増加を行なうこと ができる。 Thus, according to the semiconductor circuit device lb as the first embodiment of the present invention, the power supply wiring In area 42 (power supply wiring area 421, 422), arrange wiring and contacts to supply knock bias voltage VBBP.By reducing the number of wirings that need not be formed, power supply wiring area 42 (power supply wiring area 421, 422 422) can be reduced, and the density of the semiconductor circuit device lb can be increased. In addition, the number of wiring channels can be increased.
[0057] また、電源配線領域 42 (電源配線領域 421, 422)にお!/、て、バックバイアス電圧 V BBPを印カロ'供給するためのコンタクト等がな 、ので、この電源配線領域 42にお 、て 、例えば、メタル層よりも下層にトランジスタ等のロジック回路を配置 '形成することが でき、これによつても、半導体回路装置 laを高密度化することができる。  [0057] Further, since there is no contact or the like for supplying the back bias voltage V BBP to the power supply wiring area 42 (power supply wiring areas 421, 422), the power supply wiring area 42 has no contact. For example, a logic circuit such as a transistor can be arranged and formed below the metal layer, and this can also increase the density of the semiconductor circuit device la.
さらに、サイト 411においてコンタクト 17, 18を端部に寄せて形成することにより、ス ペース効率が向上し、又、ノ ックバイアス制御を行なうことにより、リーク電流を減少さ せ消費電力を低減することができる。  Furthermore, by forming the contacts 17 and 18 close to the end at the site 411, the space efficiency is improved, and by performing the knock bias control, the leakage current can be reduced and the power consumption can be reduced. it can.
[0058] (C)第 2実施形態の説明  [0058] (C) Description of Second Embodiment
上述した第 1実施形態としての半導体回路装置 laおよびその変形例としての半導 体回路装置 lbにおいては、 P型基板 10上にインバータ回路 30a, 30bが形成された 例について説明しているがこれに限定されるものではなぐ P型基板 10上において種 々の回路が形成されてもよぐ例えば、 P型基板 10上において、複数の CMOS回路 をそなえてもよく、更に、これらの複数の CMOS回路のうち一部に対してのみバック バイアス制御を行なってもよ ヽ。  In the semiconductor circuit device la as the first embodiment described above and the semiconductor circuit device lb as a modification thereof, an example in which the inverter circuits 30a and 30b are formed on the P-type substrate 10 is described. Various circuits may be formed on the P-type substrate 10. For example, a plurality of CMOS circuits may be provided on the P-type substrate 10, and moreover, these plural CMOS circuits may be provided. Back bias control may be performed on only part of the circuit.
[0059] 図 6は本発明の第 2実施形態の半導体回路装置 lcの構成を模式的に示す側断面 図である。  FIG. 6 is a side sectional view schematically showing the configuration of the semiconductor circuit device lc according to the second embodiment of the present invention.
本第 2実施形態の半導体回路装置 lcも、第 1実施形態の半導体回路装置 laと同 様に、例えば、ゲートアレイやスタンダードセル方式等で構成され、情報処理装置等 において使用されるものである。  Similarly to the semiconductor circuit device la of the first embodiment, the semiconductor circuit device lc of the second embodiment is configured by, for example, a gate array or a standard cell system and used in an information processing device or the like. .
[0060] 以下、本第 2実施形態の半導体回路装置 lcにおいては、同一の P型基板 10上に 2 入力 NAND回路 30cとインバータ回路 30dとを形成し、これらのうち 2入力 NAND回 路 30cに対してのみバックバイアス制御を行な!/、、インバータ回路 30dにはバックバ ィァス制御を行なわな 、例につ!、て説明する。 なお、本第 2実施形態においては、インバータ回路 30dが、ノ ックバイアス制御が 行なわれない非バックバイアス制御回路部として機能する。 [0060] Hereinafter, in the semiconductor circuit device lc of the second embodiment, the 2-input NAND circuit 30c and the inverter circuit 30d are formed on the same P-type substrate 10, and the 2-input NAND circuit 30c among them is formed in the 2-input NAND circuit 30c. For example, the back bias control is performed only on the inverter circuit 30d, and the back bias control is not performed on the inverter circuit 30d. In the second embodiment, the inverter circuit 30d functions as a non-back bias control circuit unit in which knock bias control is not performed.
[0061] 本発明の第 2実施形態の半導体回路装置 lcは、図 6に示すように、 P型基板 (半導 体基板） 10,第 1N型ゥエル 11— 1, 11 - 2,第 1P型ゥエル 13— 1, 13- 2,第 2P 型ゥエル 14— 1, 14— 2および第 2N型ゥエル 12をそなえて構成されている。そして 、 P型基板 10,第 1N型ゥエル (第 2の拡散領域） 11— 1,第 1P型ゥエル (第 1の拡散 領域） 13— 1,第 2P型ゥエル (第 3の拡散領域） 14— 1および第 2N型ゥエル (第 4の 拡散領域） 12によって 2入力 NAND回路 30cが形成され、又、 P型基板 10,第 1N 型ゥエル 11— 2,第 1P型ゥエル 13— 2および第 2P型ゥエル 14— 2によってインバー タ回路 30dが形成された例を示して 、る。  [0061] The semiconductor circuit device lc of the second embodiment of the present invention includes a P-type substrate (semiconductor substrate) 10, a first N-type well 11-1, 11-2, and a first P-type as shown in FIG. It consists of wels 13–1, 13-2, second P type wels 14–1, 14–2 and second N type wels 12. Then, P-type substrate 10, 1st N-type wel (second diffusion region) 11—1, 1st P-type wel (first diffusion region) 13—1, 2nd P-type wel (third diffusion region) 14— 1 and 2N type well (fourth diffusion region) 12 form a 2-input NAND circuit 30c, and P type substrate 10, 1st N type well 11-2, 1st type P well 13-2 and 2nd type P An example in which the inverter circuit 30d is formed by the wel 14-2 is shown below.
[0062] なお、図中、既述の符号と同一の符号は同一もしくは略同一の部分を示しているの で、その詳細な説明は省略する。  [0062] In the figure, the same reference numerals as those already described indicate the same or substantially the same parts, and detailed description thereof will be omitted.
2入力 NAND回路 30cにおいては、 P型 (第 1導電型）の導電性を有する P型基板 10上に、 P型基板 10とは異なる導電型である N型 (第 2導電型)の導電性を有する第 2N型ゥエル (第 4の拡散領域） 12が形成されている。更に、この第 2N型ゥエル 12上 には、第 1P型ゥエル 13— 1,第 1N型ゥエル 11—1および第 2P型ゥエル 14— 1が形 成され、第 2N型ゥエル 12が、これらの第 1P型ゥエル 13— 1,第 1N型ゥエル 11— 1 および第 2P型ゥエル 14— 1と P型基板 10とを電気的に分離している。  In the 2-input NAND circuit 30c, N-type (second conductivity type) conductivity, which is a conductivity type different from P-type substrate 10, on P-type substrate 10 having P-type (first conductivity type) conductivity. A second N-type well (fourth diffusion region) 12 is formed. Further, on the second N-type well 12, the first P-type wel 13-1, the first N-type wel 11-1 and the second P-type wel 14-1 are formed. The 1P type wel 13-1, the first N type wel 11-1 and the second P type wel 14-1 are electrically separated from the P type substrate 10.
[0063] 第 1N型ゥエル 11— 1は、トランジスタの配置領域を形成し、その表面に（図 6の例 では上面）に抵抗，コンデンサ，ダイオード，トランジスタ等の種々の素子が配置'形 成され、 N型の導電性を有している。図 6に示す例においては、第 1N型ゥエル 11— 1に上に、 2入力 NAND回路 30cの一部をなす P型のトランジスタ（P型トランジスタ） 3 04が形成されており、 P+領域 22— 1, 22- 2, 22— 3が形成されるとともに、酸ィ匕膜 等（図示省略)を介して絶縁された状態でゲート 32— 1, 32— 2が形成されている。そ して、 P+領域 22— 2〖こは、電源装置 201 (図 11参照）から配線 L121を介して電源電 圧 Vddが供給されるようになって!/、る。  [0063] The first N-type well 11-1 forms a transistor arrangement region, and various elements such as resistors, capacitors, diodes, and transistors are arranged on the surface (the upper surface in the example of FIG. 6). It has N-type conductivity. In the example shown in FIG. 6, a P-type transistor (P-type transistor) 3 04 forming a part of a 2-input NAND circuit 30c is formed on the first N-type well 11-1 and a P + region 22— 1, 22-2, 22-3 are formed, and gates 32-1, 32-2 are formed in an insulated state through an oxide film or the like (not shown). Then, in the P + region 22-2, the power supply voltage Vdd is supplied from the power supply 201 (see FIG. 11) via the wiring L121.
[0064] 第 1P型ゥエル 13— 1は、トランジスタの配置領域を形成し、その表面に（図 6の例 では上面）に抵抗，コンデンサ，ダイオード，トランジスタ等の種々の素子が形成され 、 P型の導電性を有している。図 6に示す例においては、第 1P型ゥエル 13— 1に上 に、 2入力 NAND回路 30cの一部をなす N型のトランジスタ（N型トランジスタ） 303力 S 形成されており、 N+領域 23— 1, 23- 2, 23— 3が形成されるとともに、酸ィ匕膜等（図 示省略)を介して絶縁された状態でゲート 31— 1, 31— 2が形成されている。又、 N+ 領域 23— 3には、電源装置 201 (図 11参照）から配線 L131を介してグランド電圧 Vs sが供給されるようになって 、る。 [0064] The first P-well 13-1 forms an arrangement region of transistors, and various elements such as resistors, capacitors, diodes, transistors, etc. are formed on its surface (upper surface in the example of FIG. 6). It has P-type conductivity. In the example shown in FIG. 6, an N-type transistor (N-type transistor) 303 force S is formed on the first P-type well 13-1 and forms part of the 2-input NAND circuit 30c. 1, 23-2, 23-3 are formed, and gates 31-1, 31-2 are formed in an insulated state through an oxide film or the like (not shown). Further, the ground voltage Vss is supplied to the N + region 23-3 from the power supply device 201 (see FIG. 11) via the wiring L131.
[0065] 一方、インバータ回路 30dにおいては、 P型基板 10上に、同じく P型の第 2P型ゥェ ル (第 7の拡散領域） 14— 2が形成され、更に、この第 2P型ゥエル 14— 2上には、第 1P型ゥエル (第 5の拡散領域） 13— 2および第 1N型ゥエル (第 6の拡散領域） 11— 2 が形成され、第 2P型ゥエル 14— 2が、これらの第 1P型ゥエル 13— 2と P型基板 10と を電気的に接続している。  On the other hand, in the inverter circuit 30d, a P-type second P-type well (seventh diffusion region) 14-2 is formed on the P-type substrate 10, and the second P-type well 14 is formed. — On the 2nd, the 1st P-type wel (fifth diffusion region) 13-2 and the 1st N-type wel (sixth diffusion region) 11-2 are formed, and the 2nd P-type wel 14-2 The first P-type well 13-2 and the P-type substrate 10 are electrically connected.
[0066] 第 1N型ゥエル 11— 2もトランジスタの配置領域を形成し、その表面に（図 6の例で は上面）に抵抗，コンデンサ，ダイオード，トランジスタ等の種々の素子が配置'形成 され、 N型の導電性を有している。図 6に示す例においては、第 1N型ゥエル 11— 2 には、 P+領域 22— 4, 22— 5および N+領域 24が形成されるとともに、酸化膜等（図示 省略)を介して絶縁された状態でゲート 33が形成されている。又、 P+領域 22— 5およ び N+領域 24には、電源装置 201 (図 11参照）から配線 L124を介して電源電圧 Vdd が供給されるようになって 、る。  [0066] The first N-type well 11-2 also forms a transistor arrangement region, and various elements such as resistors, capacitors, diodes, and transistors are arranged on the surface (the upper surface in the example of FIG. 6). Has N-type conductivity. In the example shown in FIG. 6, P + regions 22-4, 22-5 and N + region 24 are formed in the first N-type well 11-2 and insulated through an oxide film (not shown). In the state, a gate 33 is formed. Further, the power supply voltage Vdd is supplied to the P + region 22-5 and the N + region 24 from the power supply device 201 (see FIG. 11) via the wiring L124.
[0067] 第 1P型ゥエル 13— 2もトランジスタの配置領域を形成し、その表面に（図 6の例で は上面）に抵抗，コンデンサ，ダイオード，トランジスタ等の種々の素子が形成され、 P 型の導電性を有している。図 6に示す例においては、第 1P型ゥエル 13— 2には、 N+ 領域 23— 4, 23— 5および P+領域 25が形成されるとともに、酸化膜等（図示省略)を 介して絶縁された状態でゲート 34が形成されている。又、 P+領域 25および N+領域 2 3— 4〖こは、電源装置 201 (図 11参照）から配線 L132を介してグランド電圧 Vssが供 給されるようになっている。  [0067] The first P-type well 13-2 also forms a transistor arrangement region, and various elements such as resistors, capacitors, diodes, and transistors are formed on the surface (upper surface in the example of FIG. 6). It has the conductivity of. In the example shown in FIG. 6, N + regions 23-4, 23-5 and P + region 25 are formed in the first P-type well 13-2 and insulated through an oxide film or the like (not shown). In the state, a gate 34 is formed. In addition, the P + region 25 and the N + region 2 3-4 are supplied with the ground voltage Vss from the power supply device 201 (see FIG. 11) via the wiring L132.
[0068] すなわち、インバータ回路 30dはバックバイアス制御を行なわないようになつており 、第 1P型ゥエル 13— 2および第 1N型ゥエル 11— 2にはバックバイアス電圧を印加し ないようになっている。 また、本第 2実施形態に力かる半導体回路装置 lcにおいても、 2入力 NAND回路 30cは、第 1実施形態の半導体回路装置 laと同様にサイトマトリクスとして構成され（ 図 2,図 3参照）、 P型基板 10上に形成された第 2N型ゥエル 12上において、サイトァ レイ部 43として形成される。 That is, the inverter circuit 30d does not perform back bias control, and does not apply a back bias voltage to the first P-type well 13-2 and the first N-type well 11-2. . Also in the semiconductor circuit device lc according to the second embodiment, the two-input NAND circuit 30c is configured as a site matrix similarly to the semiconductor circuit device la of the first embodiment (see FIGS. 2 and 3). A site array portion 43 is formed on the second N-type well 12 formed on the P-type substrate 10.
[0069] すなわち、本第 2実施形態の半導体回路装置 lcも、 2入力 NAND回路 30cにおい て、第 1実施形態の半導体回路装置 laと同様に、第 2N型ゥエル 12,第 2P型ゥエル 14— 1および第 1N型ゥエル 11— 1 (もしくは第 1P型ゥエル 13— 1)による 3重ゥエル 構造をそなえて 、ると ゝえる。 That is, the semiconductor circuit device lc of the second embodiment is also the same as the semiconductor circuit device la of the first embodiment in the two-input NAND circuit 30c as in the second N-type well 12, the second P-type well 14- It can be said that it has a triple wel structure by 1 and 1N type wel 11-1 (or 1st type P wel 13-1).
そして、第 2P型ゥエル 14— 1におけるサイトアレイ部 43と重合しない領域、すなわ ち、第 2P型ゥエル 14— 1におけるサイトマトリクスの外側（外周部分）には、この第 2P 型ゥエル 14— 1に第 1極性のバックバイアス電圧 VBBNを供給するメタル層（図示省 略)と、第 2P型ゥエル 14— 1とを電気的に接続するコンタクト 141 (図 3参照）が形成 されており、このコンタクト 141 (P+領域 26)を介して、電源装置 201 (図 11参照）から 供給される第 1極性のバックバイアス電圧 VBBNが第 2P型ゥエル 14— 1に印加され るようになっている。  The region that does not overlap with the site array part 43 in the second P-type 14-1, that is, the outside of the site matrix in the second P-type 14-1 (outer peripheral part) is the second P-type 14-1 A contact layer 141 (see FIG. 3) is formed to electrically connect a metal layer (not shown) for supplying a back bias voltage VBBN of the first polarity to the second P-type well 14-1. The first-polarity back bias voltage VBBN supplied from the power supply device 201 (see FIG. 11) is applied to the second P-type well 14-1 via 141 (P + region 26).
[0070] また、第 2N型ゥエル 12における、サイトアレイ部 43や第 2P型ゥエル 14—1のいず れとも重合しない領域、すなわち、第 2N型ゥエル 12におけるサイトマトリクスおよび 第 2P型ゥエル 14の外側（外周部分）には、この第 2N型ゥエル 12に、第 1極性とは異 なる第 2極性のバックバイアス電圧 VBBPを供給するメタル層（図示省略）と第 2N型 ゥエル 12とを電気的に接続するコンタクト 123 (図 3参照）が形成されており、このコン タクト 123 (N+領域 21)を介して、電源装置 201 (図 11参照)から供給される第 2極性 のバックバイアス電圧 VBBPが第 2N型ゥエル 12に印加されるようになっている。  [0070] Further, in the second N-type well 12, the region where neither the site array portion 43 nor the second P-type well 14-1 overlaps, that is, the site matrix in the second N-type well 12 and the second P-type well 14 On the outside (outer periphery), a metal layer (not shown) for supplying a back bias voltage VBBP having a second polarity different from the first polarity to the second N-type well 12 and a second N-type well 12 are electrically connected. A contact 123 (see FIG. 3) is formed, and the second polarity back bias voltage VBBP supplied from the power supply device 201 (see FIG. 11) is supplied via this contact 123 (N + region 21). It is designed to be applied to 2nd N-type wel 12.
[0071] すなわち、 2入力 NAND回路 30cにおいては、第 1P型ゥエル 13— 1へのバックバ ィァス電圧 VBBNの供給は第 2P型ゥエル 14— 1から行なわれ、又、第 1N型ゥエル 11— 1へのバックバイアス電圧 VBBPの供給は第 2N型ゥエル 12から行なわれるの である。  That is, in the 2-input NAND circuit 30c, the back bias voltage VBBN is supplied to the first P-type well 13-1 from the second P-type well 14-1 and to the first N-type well 11-1. The back bias voltage VBBP is supplied from the second N-type well 12.
上述の如く構成された本発明の第 2実施形態としての半導体回路装置 lcにおいて も、第 1実施形態の半導体回路装置 laと同様に、第 2P型ゥエル 14— 1におけるサイ トアレイ部 43不在の領域において、第 2P型ゥエル 14 1にバックバイアス電圧 VBB Nが印加されるとともに、第 2N型ゥエル 12におけるサイトアレイ部 43および第 2P型 ゥエル 14—1不在の領域において、第 2N型ゥエル 12にバックバイアス電圧 VBBP が印加される。 Also in the semiconductor circuit device lc as the second embodiment of the present invention configured as described above, the size in the second P-type well 14-1 is the same as the semiconductor circuit device la of the first embodiment. The back bias voltage VBB N is applied to the second P-type well 14 1 in the region where the second array type 43 14 is absent, and the second N-type well 12 in the region where the site array unit 43 and the second P-type well 14-1 are absent. Back bias voltage VBBP is applied to 2N type wel 12.
[0072] そして、第 1N型ゥエル 11—1および第 1P型ゥエル 13—1に形成された 2入力 NA ND回路 30cにおいては、電源装置 201 (図 11参照）から P+領域 26を介して印加さ れるバックバイアス電圧 VBBNにより、第 2P型ゥエル 14 1および第 1P型ゥエル 13 1を経由して Nチャンネル MOS (NMOS)トランジスタが制御されるとともに、同じく 電源装置 201 (図 11参照）から N+領域 21介して印加されるバックバイアス電圧 VBB Pにより、第 2N型ゥエル 12および第 1N型ゥエル 11— 1を経由して Pチャンネル MO S (PMOS)トランジスタが制御されることにより、 2入力 NAND回路 30cのバックバイ ァス制御が行なわれる。  [0072] Then, in the 2-input NA ND circuit 30c formed in the first N-type wel 11-1 and the first P-type wel 13-1, it is applied via the P + region 26 from the power supply device 201 (see FIG. 11). The N-channel MOS (NMOS) transistor is controlled by the back bias voltage VBBN via the second P-type 14 1 and the first P-type 131, and also from the power supply 201 (see FIG. 11). The P-channel MOS (PMOS) transistor is controlled by the back bias voltage VBB P applied through the second N-type well 12 and the first N-type well 11—1, thereby Back bias control is performed.
[0073] また、このバックバイアス制御は、具体的には、トランジスタ直下のゥエル電圧を N MOSであれば Pゥエルをマイナスへ、 PMOSであれば Nゥエルをプラスへ、逆バイァ スを印加することにより行なわれる。  [0073] In addition, this back bias control is specifically applied by applying a reverse bias to the P-well when the NMOS voltage is just below the transistor is N MOS, and to the N-well when the PMOS is N-MOS. It is done by.
また、本第 2実施形態の半導体回路装置 lcは、例えば、 P型基板 10に第 2N型ゥ エル 12を形成させた後に、第 2P型ゥエル 14— 1, 14— 2を形成させ、更に、第 1N 型ゥエル 11— 1, 11— 2および第 1P型ゥエル 13— 1, 13— 2を形成させた後に、トラ ンジスタのバルタ製造工程や、各電源端子や配線の製造工程等を行なうことにより製 造することができる。  Further, the semiconductor circuit device lc of the second embodiment, for example, after forming the second N-type well 12 on the P-type substrate 10, forms the second P-type wells 14-1, 14-2, After forming the 1st N-type wels 11-1, 11-2 and 1st P-type wels 13-1, 13-2, perform the transistor's Balta manufacturing process, the manufacturing process of each power supply terminal and wiring, etc. Can be manufactured.
[0074] このように、本発明の第 2実施形態としての半導体回路装置 lcによれば、第 1実施 形態と同様の作用効果を得ることができる他、一の P型基板 10上において、ゥエル電 圧を制御してリーク電流を軽減することにより消費電力の軽減を図る領域 (本第 2実 施形態では 2入力 NAND回路 30c部分）と、バックバイアス電圧（ゥエル電圧という場 合もある）の制御を行なわな 、領域 (本第 2実施形態ではインバータ回路 30d部分； 非バックバイアス制御回路部）とを形成することができ、一の P型基板 10を、例えば回 路的な特徴に合わせて使い分けることができる。これにより、例えば、ノ ックバイアス 制御を有するものと有しないものとの 2種類のタイプのトランジスタを同一チップ上に 作成でき、利便性が高い。 As described above, according to the semiconductor circuit device lc as the second embodiment of the present invention, it is possible to obtain the same effect as that of the first embodiment. In the area where power consumption is reduced by controlling the voltage to reduce the leakage current (in this second embodiment, the 2-input NAND circuit 30c part) and the back bias voltage (sometimes referred to as the well voltage) A region (inverter circuit 30d portion in the second embodiment; non-back bias control circuit portion) can be formed without control, and one P-type substrate 10 can be formed in accordance with, for example, circuit characteristics. Can be used properly. As a result, for example, two types of transistors with and without knock bias control can be placed on the same chip. It can be created and is very convenient.
[0075] なお、ゥエル電圧の制御を行なわな ヽ領域には、例えば、クロック信号発生回路や SRAM (Static Random Access Memory)等のバックバイアスの電圧制御を行なうこと により、クロック幅やセンスアンプの感度に影響が出る等の理由により、ノ ックバイアス 制御を行う必要の無 、回路を形成することが望まし 、。 [0075] In addition, in the area where the well voltage is not controlled, for example, by controlling the back bias voltage of the clock signal generation circuit, SRAM (Static Random Access Memory), etc., the clock width and the sensitivity of the sense amplifier are controlled. It is desirable to form a circuit without the need for knock bias control because of the influence on the
(D)第 2実施形態の変形例の説明  (D) Description of modification of second embodiment
上述した第 2実施形態に力かる半導体回路装置 lcにおいては、 2入力 NAND回 路 30cにおいて、第 2P型ゥエル 14— 1を介してバックバイアス電圧 VBBNを印加す るとともに、第 2N型ゥエル 12を介してバックノィァス電圧 VBBPを印加することにより 、 NMOSトランジスタと PMOSトランジスタとの!/、ずれに対してもバックバイアス制御 を行なっているが、これに限定されるものではなぐこれらの P型基板 10上に形成さ れた NMOSトランジスタおよび PMOSトランジスタのうちいずれか一方に対してのみ バックバイアス制御を行なってもよ ヽ。  In the semiconductor circuit device lc that is effective in the second embodiment described above, the back bias voltage VBBN is applied via the second P-type 14-1 in the 2-input NAND circuit 30c, and the second N-type 12 is applied. The back bias voltage VBBP is applied to control the back bias for the! / And the deviation between the NMOS transistor and the PMOS transistor. However, the present invention is not limited to this. The back bias control may be performed only on one of the NMOS transistor and the PMOS transistor formed in the above.
[0076] 図 7は本発明の第 1実施形態の半導体回路装置の変形例の構成を模式的に示す 側断面図である。 FIG. 7 is a side sectional view schematically showing a configuration of a modified example of the semiconductor circuit device according to the first embodiment of the present invention.
本第 2実施形態の変形例としての半導体回路装置 Idも、第 2実施形態の半導体回 路装置 lcと同様に、例えば、ゲートアレイやスタンダードセル方式等で構成され、情 報処理装置等において使用されるものである。  Similar to the semiconductor circuit device lc of the second embodiment, the semiconductor circuit device Id as a modification of the second embodiment is also configured by, for example, a gate array, a standard cell system, etc. It is what is done.
[0077] 以下、本第 2実施形態の変形例としての半導体回路装置 Idとして、同一の P型基 板 10上に 2入力 NAND回路 30eとインバータ回路 30dとを形成し、この 2入力 NAN D回路 30eにおける PMOSトランジスタに対してのみバックバイアス制御を行なう例 について説明する。 Hereinafter, as a semiconductor circuit device Id as a modification of the second embodiment, a two-input NAND circuit 30e and an inverter circuit 30d are formed on the same P-type substrate 10, and this two-input NAND circuit An example in which back bias control is performed only for the PMOS transistor at 30e will be described.
なお、本第 2実施形態の変形例においても、インバータ回路 30dが、バックバイアス 制御が行なわれない非バックバイアス制御回路部として機能する。  In the modification of the second embodiment, the inverter circuit 30d functions as a non-back bias control circuit unit that does not perform back bias control.
[0078] 本発明の第 2実施形態の変形例としての半導体回路装置 Idは、図 7に示すように、 P型基板 10,第 1N型ゥエル 11— 1, 11 - 2,第 1P型ゥエル 13— 1, 13- 2,第 2P 型ゥエル 14— 2および第 2N型ゥエル 12をそなえて構成されている。 As shown in FIG. 7, a semiconductor circuit device Id as a modification of the second embodiment of the present invention includes a P-type substrate 10, first N-type wells 11-1, 11-2, first P-type well 13 — 1, 13-2, 2nd P-type wel 14-2 and 2nd N-type wel 12.
そして、 P型基板 (半導体基板) 10,第 1N型ゥエル (第 2の拡散領域) 11— 1,第 1 P型ゥエル (第 1の拡散領域） 13— 1および第 2N型ゥエル (第 4の拡散領域） 12によ つて 2入力 NAND回路 30eが形成され、電源装置 201 (図 11参照)から供給される 第 1極性のバックバイアス電圧 VBBNが、 P+領域 (電源端子） 262に印加されるととも に、電源装置 201 (図 11参照)から供給される第 1極性とは異なる第 2極性のバックバ ィァス電圧 VBBPが、第 2N型ゥエル 12に形成された N+領域 (電源端子） 21を介して 印加されるようになって 、る。 P-type substrate (semiconductor substrate) 10, 1st N-type well (second diffusion region) 11—1, 1st A two-input NAND circuit 30e is formed by the P-type wel (first diffusion region) 13-1 and the second N-type wel (fourth diffusion region) 12 and supplied from the power supply 201 (see FIG. 11). A back bias voltage VBBN of the first polarity is applied to the P + region (power supply terminal) 262, and a back bias voltage of the second polarity different from the first polarity supplied from the power supply device 201 (see FIG. 11). VBBP is applied through an N + region (power supply terminal) 21 formed in the second N-type well 12.
[0079] また、 P型基板 10,第 1N型ゥエル 11— 2,第 1P型ゥエル 13— 2および第 2P型ゥ エル 14— 2によってインバータ回路 30dが形成されて!、る。 Further, the inverter circuit 30d is formed by the P-type substrate 10, the first N-type well 11-2, the first P-type well 13-2, and the second P-type well 14-2.
なお、図中、既述の符号と同一の符号は同一もしくは略同一の部分を示しているの で、その詳細な説明は省略する。  In the figure, the same reference numerals as those described above indicate the same or substantially the same parts, and detailed description thereof will be omitted.
本第 2実施形態の変形例としての半導体回路装置 Idにおいては、 2入力 NAND 回路 30eにおいて、 P型の導電性を有する P型基板 10上に、 N型 (第 2導電型）の導 電性を有する第 2N型ゥエル 12が形成されている。更に、この第 2N型ゥエル 12上に は、第 1P型ゥエル 13— 1および第 1N型ゥエル 11— 1が形成され、第 2N型ゥエル 1 2力 これらの第 1P型ゥエル 13— 1および第 1N型ゥエル 11— 1と P型基板 10とを電 気的に分離している。  In the semiconductor circuit device Id as a modified example of the second embodiment, the N-type (second conductivity type) conductivity is provided on the P-type substrate 10 having the P-type conductivity in the two-input NAND circuit 30e. A second N-type well 12 is formed. Furthermore, on the second N-type well 12, the first P-type well 13-1 and the first N-type well 11-1 are formed, and the second N-type well 1 2 force. These first P-type well 13-1 and the first N The mold well 11-1 and the P-type substrate 10 are electrically separated.
[0080] また、第 1P型ゥエル 13— 1は、トランジスタの配置領域を形成し、その表面に（図 7 の例では上面）に抵抗，コンデンサ，ダイオード，トランジスタ等の種々の素子が形成 され、 P型の導電性を有している。図 7に示す例においては、第 1P型ゥエル 13— 1に は、 N+領域 23— 1, 23- 2, 23— 3および P+領域 262が形成されるとともに、 P+領域 262には、電源装置 201 (図 11参照）から第 1極性のバックバイアス電圧 VBBNが印 カロされるようになっている。又、第 1P型ゥエル 13— 1には、酸化膜等（図示省略)を介 して絶縁された状態でゲート 31— 1, 31— 2が形成されている。更に、 N+領域 23— 3 には、電源装置 201 (図 11参照）から配線 L131を介してグランド電圧 Vssが供給さ れるようになっている。  [0080] Further, the first P-type well 13-1 forms an arrangement region of the transistor, and various elements such as a resistor, a capacitor, a diode, and a transistor are formed on the surface (upper surface in the example of FIG. 7). P-type conductivity. In the example shown in FIG. 7, the N + region 23-1, 1, 23-2, 23-3 and the P + region 262 are formed in the first P-type well 13-1, and the power supply device 201 is included in the P + region 262. As shown in Fig. 11, the back bias voltage VBBN of the first polarity is printed. Further, gates 31-1 and 31-2 are formed on the first P-type well 13-1 in an insulated state through an oxide film or the like (not shown). Further, the ground voltage Vss is supplied to the N + region 23-3 from the power supply device 201 (see FIG. 11) via the wiring L131.
[0081] また、第 2N型ゥエル 12は、第 2実施形態の半導体回路装置 lcにおける 2入力 NA ND回路 30cと同様に、 P型基板 10上において、サイトマトリクス (複数のサイトアレイ 部 43)を包含するような領域として形成され、 P型基板 10上において、この P型基板 1 0と、第 IN型ゥエル 11—1および第 IP型ゥエル 13— 1とを電気的に分離するように 形成されている。 In addition, the second N-type well 12 has a site matrix (a plurality of site array units 43) formed on the P-type substrate 10 in the same manner as the two-input NA ND circuit 30c in the semiconductor circuit device lc of the second embodiment. The P-type substrate 1 is formed on the P-type substrate 10. It is formed so that 0 is electrically separated from the IN type wel 11-1 and the IP type wel 13-1.
[0082] すなわち、本第 2実施形態の変形例としての半導体回路装置 Idにおいては、 2入 力 NAND回路 30eにおいて、第 2実施形態の半導体回路装置 lcにおける第 2P型 ゥエル 14— 1をそなえずに構成されるとともに、 P+領域 262をそなえ、この P+領域 26 2にバックバイアス電圧 VBBNが印加される他は、第 2実施形態の半導体回路装置 1 cとほぼ同様に構成されて 、る。  That is, in the semiconductor circuit device Id as a modification of the second embodiment, the 2-input NAND circuit 30e is not provided with the second P-type well 14-1 in the semiconductor circuit device lc of the second embodiment. The P + region 262 is provided, and the back bias voltage VBBN is applied to the P + region 262. The semiconductor circuit device 1c of the second embodiment is substantially the same.
[0083] なお、本第 2実施形態の変形例としての半導体回路装置 Idにおいては、第 2N型 ゥエル 12および第 1N型ゥエル 11— 1 (もしくは第 1P型ゥエル 13— 1)による 2重ゥェ ル構造をそなえて 、ると ゝえる。  Note that in the semiconductor circuit device Id as a modification of the second embodiment, a double well formed by the second N-type well 12 and the first N-type well 11-1 (or the first P-type well 13-1) is used. If you have a structure,
また、本第 2実施形態の変形例としての半導体回路装置 Idは、例えば、 P型基板 1 0に第 2N型ゥエル 12を形成させた後に、第 2P型ゥエル 14— 2を形成させ、更に、第 1N型ゥエル 11— 1, 11— 2および第 1P型ゥエル 13— 1, 13— 2を形成させ、その後 、トランジスタのバルタ製造工程や各電源端子や配線の製造工程を行なうことにより 製造することができる。  Further, a semiconductor circuit device Id as a modification of the second embodiment includes, for example, forming a second N-type well 12-2 on a P-type substrate 10 and then forming a second P-type well 14-2. First N-type wels 11-1, 11-2 and 1P-type wels 13-1, 1, 13-2 are formed, and then manufactured by performing the transistor's Balta manufacturing process and the power supply terminal and wiring manufacturing processes. Can do.
[0084] 上述の如く構成された本発明の第 2実施形態の変形例としての半導体回路装置 Id によっても、 2入力 NAND回路 30eにおいて、第 2N型ゥエル 12におけるサイトァレ ィ部 43 (図 2,図 3参照）不在の領域において電源装置 201からバルタコンタクト N+領 域 21を介して第 2N型ゥエル 12に印加されるバックバイアス電圧 VBBPと、電源装置 201から P+領域 262に印加されるバックバイアス電圧 VBBNとにより、 2入力 NAND 回路 30eのバックバイアス制御が行なわれる。  [0084] Also with the semiconductor circuit device Id as a modification of the second embodiment of the present invention configured as described above, in the 2-input NAND circuit 30e, the site array section 43 in the second N-type well 12 (Fig. 2, Fig. 2). 3) Back bias voltage VBBP applied to second N-type well 12 from power supply 201 through Balta contact N + region 21 in the absence region, and back bias voltage VBBN applied to P + region 262 from power supply 201 Thus, the back bias control of the 2-input NAND circuit 30e is performed.
[0085] また、このバックバイアス制御は、具体的には、トランジスタ直下のゥエル電圧を N MOSであれば Pゥエルをマイナスへ、 PMOSであれば Nゥエルをプラスへ、逆バイァ ス電圧を印加することにより行なわれる。  [0085] In addition, this back bias control is specifically applied by applying a reverse bias voltage to the p-well if the NMOS voltage just below the transistor is N MOS, to P-minus if it is PMOS, or to N-plus if it is PMOS. Is done.
このように、本発明の第 2実施形態の変形例としての半導体回路装置 Idによっても 、第 2実施形態の半導体回路装置 lcと同様の作用効果を得ることができるほか、電 源配線領域 42 (電源配線領域 421, 422)において、バックバイアス電圧 VBBPを供 給するための配線やコンタクト等を配置 ·形成する必要がなく、配線数を削減すること により電源配線領域 42 (電源配線領域 421, 422)の占有面積を低減することができ 、半導体回路装置 laを高密度化することができる。又、配線チャネルの増加を行なう ことができる。 As described above, the semiconductor circuit device Id as a modified example of the second embodiment of the present invention can obtain the same operation and effect as the semiconductor circuit device lc of the second embodiment, and the power wiring region 42 ( In the power supply wiring area (421, 422), it is not necessary to arrange and form wiring and contacts to supply the back bias voltage VBBP, and to reduce the number of wiring As a result, the area occupied by the power supply wiring region 42 (power supply wiring regions 421 and 422) can be reduced, and the density of the semiconductor circuit device la can be increased. In addition, the number of wiring channels can be increased.
[0086] また、電源配線領域 42 (電源配線領域 421, 422)にお!/、て、バックバイアス電圧 V BBPを印カロ'供給するためのコンタクト等がな 、ので、この電源配線領域 42にお 、て 、例えば、メタル層よりも下層にトランジスタ等のロジック回路を配置 '形成することが でき、これによつても、半導体回路装置 Idを高密度化することができる。  [0086] Since there is no contact or the like for supplying the back bias voltage V BBP to the power supply wiring area 42 (power supply wiring areas 421, 422), the power supply wiring area 42 has no contact. For example, a logic circuit such as a transistor can be arranged and formed below the metal layer, and this can also increase the density of the semiconductor circuit device Id.
(E)その他  (E) Other
図 11は本発明の一実施形態としての半導体回路装置システムの構成を模式的に 示す図である。  FIG. 11 is a diagram schematically showing a configuration of a semiconductor circuit device system as an embodiment of the present invention.
[0087] 半導体回路装置システム 100は、図 11に示すように、電源装置 201と半導体回路 装置 laとをそなえて構成され、電源装置 201が、半導体回路装置 laに対して、バッ クバイアス電圧 VBBN, VBBP,電源電圧 Vddおよびグランド電圧 Vssを供給するよ うになつている。  As shown in FIG. 11, the semiconductor circuit device system 100 includes a power supply device 201 and a semiconductor circuit device la, and the power supply device 201 has a back bias voltage VBBN, VBBP, power supply voltage Vdd, and ground voltage Vss are supplied.
なお、図中、既述の符号と同一の符号は同一もしくは略同一の部分を示しているの で、その詳細な説明は省略する。  In the figure, the same reference numerals as those described above indicate the same or substantially the same parts, and detailed description thereof will be omitted.
[0088] また、電源装置 201が電圧を供給する半導体回路装置は、図 11に示す半導体回 路装置 laに限定されるものではなぐ上述した各実施形態およびその変形例として 示した、半導体回路装置 lb, lc, Idであってもよぐ本発明の趣旨を逸脱しない範 囲で種々変形して実施することができる。 また、本発明は上述した各実施形態およ びその変形例に限定されるものではなぐ本発明の趣旨を逸脱しない範囲で種々変 形して実施することができる。  Further, the semiconductor circuit device to which the power supply device 201 supplies the voltage is not limited to the semiconductor circuit device la shown in FIG. 11, and the semiconductor circuit device shown as each of the above-described embodiments and modifications thereof. Even if it is lb, lc, or Id, various modifications can be made without departing from the spirit of the present invention. In addition, the present invention is not limited to the above-described embodiments and modifications thereof, and various modifications can be made without departing from the spirit of the present invention.
[0089] 例えば、上述した第各実施形態およびその変形例においては、 P型基板 10上にィ ンバータ回路や 2入力 NAND回路を形成した例について説明している力 これに限 定するものではなぐこれらのインバータ回路や 2入力 NAND回路以外の種々の回 路を形成してもよい。  For example, in each of the above-described embodiments and the modifications thereof, the force described in the example in which the inverter circuit or the 2-input NAND circuit is formed on the P-type substrate 10 is not limited to this. Various circuits other than these inverter circuits and 2-input NAND circuits may be formed.
また、上述した各実施形態およびその変形例においては、第 2P型ゥエル 14 (14— 1)や第 2N型ゥエル 12へのバイアス制御電圧の印加をコンタクト 141 (P+領域 26) , コンタクト 123 (N+領域 21)を介して行なっている力 これに限定されるものではなぐ 例えば、第 2P型ゥエル 14や第 2N型ゥエル 12からメタル第 1層等へ直接与えても良 ぐ又、第 1P型ゥエル 13や第 1N型ゥエル 11を介してもよぐ既知の種々の手法を用 V、てバックバイアス電圧の印加を行なってもよ!/、。 Further, in each of the above-described embodiments and modifications thereof, the bias control voltage is applied to the second P-type well 14 (14-1) and the second N-type well 12 as contacts 141 (P + region 26), For example, force applied through contact 123 (N + region 21) is not limited to this. For example, it can be applied directly from the second P-type well 14 or the second N-type well 12 to the metal first layer, etc. You can apply the back bias voltage by using various known methods that can be passed through the 1st P-type wel 13 or the 1st N-type wel 11! /.
[0090] さらに、ゥエルのノ ックバイアス設定は、外部端子力も直接供給することによって行 なっても良ぐ又、チップ内部に、ノ ックバイアス設定回路として、外部端子から供給 された電源電圧力ゝら昇圧及び降圧して供給しても良い。  [0090] Further, the knock bias setting of the well may be performed by directly supplying the external terminal force. Further, as the knock bias setting circuit inside the chip, the power supply voltage force supplied from the external terminal is boosted. Alternatively, it may be supplied after being stepped down.
また、上述した各実施形態およびその変形例においては、低消費電力の観点から 、トランジスタ直下のゥエル電圧を NMOSであれば P型のゥエルをマイナスへ、 PMO Sであれば N型のゥエルをプラスへ、逆バイアス電圧を印加している力 これに限定さ れるものではなぐ回路の高速ィ匕を重視する場合には、ゥエルに対して順バイアス電 圧を印加するとともに、しきい値電圧 (Vth)を低くしてもよぐこれにより、半導体回路 装置の高速ィ匕を図る事ができる。  In each of the above-described embodiments and modifications thereof, from the viewpoint of low power consumption, if the well voltage directly under the transistor is NMOS, the P-type well is negative, and if PMO S is the N-type well, When applying a high-speed circuit that is not limited to this, the forward bias voltage is applied to the well and the threshold voltage (Vth Therefore, it is possible to increase the speed of the semiconductor circuit device.
[0091] さらに、上述した第 2実施形態およびその変形例にぉ 、ては、バックバイアス制御 が行なわれない非バックバイアス制御回路部としてインバータ回路 30dをそなえた例 について説明している力 これに限定するものではなぐインバータ回路以外の種々 の回路を非バックバイアス制御回路部として用いてもょ 、。  In addition, according to the second embodiment described above and its modification, the force described for the example in which the inverter circuit 30d is provided as the non-back bias control circuit unit in which the back bias control is not performed. Various circuits other than the inverter circuit that is not limited may be used as the non-back bias control circuit section.
また、上述した各実施形態およびその変形例においては、導電型が P型の導電性 を有する半導体基板である P型基板 10を用いているが、これに限定されるものでは なぐ N型の導電型を有する N型基板を用いてもよい。  Further, in each of the above-described embodiments and modifications thereof, the P-type substrate 10 which is a semiconductor substrate having a P-type conductivity is used. However, the present invention is not limited to this. An N-type substrate having a mold may be used.
[0092] この場合、上述した各実施形態および変形例に力かる半導体回路装置 la, lb, lc , Idにおいて、その第 2P型ゥエル 14に代えて導電型が N型のゥエル (第 2N型ゥェ ル）を用いるとともに、第 2N型ゥエル 12に代えて導電型が P型のゥエル (第 2P型ゥェ ル)を用いて構成することにより容易に実現することができる。そして、その製造に際 しては、基板上に生成するゥエルの形成順序を逆にすることにより、容易に製造する ことができる。  In this case, in the semiconductor circuit devices la, lb, lc, and Id that are effective in the above-described embodiments and modifications, the second P-type well 14 is replaced with an N-type well (second N-type well). This can be realized easily by using a p-type well (second P-type well) instead of the second n-type well 12. And in the case of the manufacture, it can manufacture easily by reversing the formation order of the well produced | generated on a board | substrate.
[0093] また、上述した第 1実施形態の変形例としての半導体回路装置 lbにおいては、イン バータ回路 30bにおける PMOSトランジスタに対してのみゥエル（第 2N型ゥエル 12) を介してバックバイアス電圧の印加を行なう例について示している力 これに限定さ れるものではなぐ NMOSトランジスタに対してのみゥエルを介したバックバイアス電 圧の印加を行なってもよぐ同様に、上述した第 2実施形態の変形例としての半導体 回路装置 Idにおいては、 2入力 NAND回路 30eにおける PMOSトランジスタに対し てのみゥエル (第 1N型ゥエル 11 - 1)を介してバックバイアス電圧の印加を行なう例 について示している力 これに限定されるものではなぐ NMOSトランジスタに対して のみゥエルを介したバックバイアス電圧の印加を行なってもよい。 In the semiconductor circuit device lb as a modified example of the first embodiment described above, only the PMOS transistor in the inverter circuit 30b is well (second N-type well 12). The force shown in the example of applying the back bias voltage through the gate is not limited to this. The back bias voltage may be applied through the well only to the NMOS transistor. In the semiconductor circuit device Id as a modified example of the second embodiment, the back bias voltage is applied only to the PMOS transistor in the two-input NAND circuit 30e via the well (the first N-type well 11-1). However, the present invention is not limited to this. The back bias voltage may be applied to the NMOS transistor only through the well.
[0094] なお、本発明の各実施形態が開示されていれば、本発明を当業者によって実施' 製造することが可能である。  It should be noted that if each embodiment of the present invention is disclosed, the present invention can be implemented and manufactured by those skilled in the art.
産業上の利用可能性  Industrial applicability
[0095] 半導体回路装置における種々の回路のバックバイアス制御に適用することができる [0095] The present invention can be applied to back bias control of various circuits in a semiconductor circuit device.

Claims

請求の範囲 The scope of the claims
[1] 第 1導電型の半導体基板と、  [1] a first conductivity type semiconductor substrate;
前記第 1導電型とは異なる第 2導電型のトランジスタが形成された第 1導電型の第 1 の拡散領域と、  A first conductivity type first diffusion region in which a second conductivity type transistor different from the first conductivity type is formed;
第 1導電型のトランジスタが形成された第 2導電型の第 2の拡散領域と、  A second conductivity type second diffusion region in which a first conductivity type transistor is formed;
第 1極性のバックバイアス電圧が印加される第 1導電型の第 3の拡散領域と、 前記第 1極性とは異なる第 2極性のバックバイアス電圧が印加される第 2導電型の第 4の拡散領域とを有することを特徴とする半導体回路装置。  A third diffusion region of a first conductivity type to which a back bias voltage of the first polarity is applied; and a fourth diffusion of a second conductivity type to which a back bias voltage of a second polarity different from the first polarity is applied. A semiconductor circuit device having a region.
[2] 前記第 1導電型の第 1の拡散領域と、前記第 2導電型の第 2の拡散領域は、トランジ スタの配置領域を形成し、 [2] The first diffusion region of the first conductivity type and the second diffusion region of the second conductivity type form a transistor arrangement region,
前記半導体回路装置は、前記配置領域内に形成された、前記トランジスタに電圧を 供給するための第一の電源端子と、  The semiconductor circuit device includes a first power supply terminal that is formed in the arrangement region and supplies a voltage to the transistor;
前記第 3の拡散領域に形成された、前記第 3の拡散領域から前記第 1の拡散領域に 対する第 1極性のノックバイアス電圧を印加するための第 2の電源端子と、 前記第 4の拡散領域に形成された、前記第 4の拡散領域から前記第 2の拡散領域に 対する第 2極性のノ ックバイアス電圧を印加するための第 3の電源端子と、を更に備 えることを特徴とする請求項 1記載の半導体回路装置。  A second power supply terminal formed in the third diffusion region for applying a first polarity knock bias voltage from the third diffusion region to the first diffusion region; and the fourth diffusion And a third power supply terminal for applying a second polarity knock bias voltage from the fourth diffusion region to the second diffusion region, formed in the region. Item 14. A semiconductor circuit device according to Item 1.
[3] 前記半導体回路装置はさらに、前記第 1導電型の半導体基板上に、第 1導電型の第 5及び第 7の拡散領域と、第 2導電型の第 6の拡散領域とを有し、  [3] The semiconductor circuit device further includes fifth and seventh diffusion regions of the first conductivity type and a sixth diffusion region of the second conductivity type on the first conductivity type semiconductor substrate. ,
前記第 5の拡散領域上に第 2導電型のトランジスタが形成されるとともに、 前記第 6の拡散領域上に第 1導電型のトランジスタが形成され、  A second conductivity type transistor is formed on the fifth diffusion region, and a first conductivity type transistor is formed on the sixth diffusion region,
前記第 5及び前記第 6の拡散領域にはバックバイアス電圧を印カロしないことを特徴と する請求項 1又は 2記載の半導体回路装置。  3. The semiconductor circuit device according to claim 1, wherein no back bias voltage is applied to the fifth and sixth diffusion regions.
[4] 前記第 3の拡散領域は、その長手方向が前記第 4の拡散領域の長手方向に対して 所定の角度をなすように形成されることを特徴とする請求項 1記載の半導体回路装 置。  4. The semiconductor circuit device according to claim 1, wherein the third diffusion region is formed so that a longitudinal direction thereof forms a predetermined angle with respect to a longitudinal direction of the fourth diffusion region. Place.
[5] 前記所定の角度が 90度であることを特徴とする請求項 4記載の半導体回路装置。  5. The semiconductor circuit device according to claim 4, wherein the predetermined angle is 90 degrees.
[6] 前記第 1導電型と前記第 2導電型の組み合わせはそれぞれ、 P型と N型の組み合わ せ及び N型と P型の組み合わせのいずれか一つの組み合わせであることを特徴とす る請求項 1乃至 5記載の半導体回路装置。 [6] The combination of the first conductivity type and the second conductivity type is a combination of P type and N type, respectively. 6. The semiconductor circuit device according to claim 1, wherein the semiconductor circuit device is a combination of any one of N-type and P-type.
[7] 第 1導電型の半導体基板上に形成された前記第 1導電型とは異なる第 2導電型の第 4の拡散領域と、 [7] a fourth diffusion region of a second conductivity type different from the first conductivity type formed on the first conductivity type semiconductor substrate;
前記第 4の拡散領域内に形成された第 1導電型の第 3の拡散領域と、  A third diffusion region of the first conductivity type formed in the fourth diffusion region;
前記第 3拡散領域内に形成された第 1導電型の第 1の拡散領域と、  A first diffusion region of a first conductivity type formed in the third diffusion region;
前記第 3拡散領域内に形成された第 2導電型の第 2の拡散領域と、  A second conductivity type second diffusion region formed in the third diffusion region;
前記第 1の拡散領域上に形成された第 2導電型のトランジスタと、  A second conductivity type transistor formed on the first diffusion region;
前記第 3の拡散領域力も第 1極性のバックバイアス電圧を印加するための電源端子と 前記第 2の拡散領域上に形成された第 1導電型のトランジスタと、前記第 4の拡散領 域力も前記第 1極性とは異なる第 2極性のノ ックバイアス電圧を印加するための電源 端子とを有することを特徴とする半導体回路装置。  The third diffusion region force also has a power supply terminal for applying a back bias voltage of the first polarity, a first conductivity type transistor formed on the second diffusion region, and the fourth diffusion region force also has the above-mentioned A semiconductor circuit device comprising: a power supply terminal for applying a knock bias voltage having a second polarity different from the first polarity.
[8] 前記第 3の拡散領域の長手方向と前記第 4の拡散領域の長手方向とが所定の角度 をもって、前記第 3の拡散領域と前記第 4の拡散領域とが形成されることを特徴とする 請求項 7記載の半導体回路装置。 [8] The third diffusion region and the fourth diffusion region are formed such that the longitudinal direction of the third diffusion region and the longitudinal direction of the fourth diffusion region are at a predetermined angle. The semiconductor circuit device according to claim 7.
[9] 前記所定の角度が 90度であることを特徴とする請求項 7又は 8記載の半導体回路装 置。 9. The semiconductor circuit device according to claim 7, wherein the predetermined angle is 90 degrees.
[10] 前記第 1導電型と前記第 2導電型の組み合わせはそれぞれ、 P型と N型の組み合わ せ又は N型と P型の組み合わせであることを特徴とする請求項 7乃至 9記載の半導体 回路装置。  10. The semiconductor according to claim 7, wherein the combination of the first conductivity type and the second conductivity type is a combination of P type and N type or a combination of N type and P type, respectively. Circuit device.
[11] 半導体回路装置と、前記半導体回路装置に電圧を供給する電源装置とを備え、 前記半導体回路装置は、  [11] A semiconductor circuit device and a power supply device for supplying a voltage to the semiconductor circuit device,
第 1導電型の半導体基板と、  A first conductivity type semiconductor substrate;
前記第 1導電型とは異なる第 2導電型のトランジスタが形成された第 1導電型の第 1 の拡散領域と、  A first conductivity type first diffusion region in which a second conductivity type transistor different from the first conductivity type is formed;
第 1導電型のトランジスタが形成された第 2導電型の第 2の拡散領域と、  A second conductivity type second diffusion region in which a first conductivity type transistor is formed;
前記電源装置力も第 1極性のバックバイアス電圧が印加される第 1導電型の第 3の拡 散領域と、 The power supply device also has a third extension of the first conductivity type to which a back bias voltage of the first polarity is applied. The scattered area,
前記電源装置力も前記第 1極性とは異なる第 2極性のノ ックバイアス電圧が印加され る第 2導電型の第 4の拡散領域とを有することを特徴とする半導体回路装置システム  The semiconductor circuit device system, wherein the power supply device power also has a second conductivity type fourth diffusion region to which a knock bias voltage having a second polarity different from the first polarity is applied.
[12] 前記半導体回路装置において、前記第 1導電型の第 1の拡散領域と、前記第 2導電 型の第 2の拡散領域は、トランジスタの配置領域を形成し、 [12] In the semiconductor circuit device, the first diffusion region of the first conductivity type and the second diffusion region of the second conductivity type form a transistor arrangement region,
前記配置領域内に形成された、前記トランジスタに電圧を供給するための第 1の電源 端子と、  A first power supply terminal formed in the arrangement region for supplying a voltage to the transistor;
前記第 3の拡散領域に形成された、前記第 3の拡散領域から前記第 1の拡散領域に 対する前記第 1極性のバックバイアス電圧を印加するための第 2の電源端子と、 前記第 4の拡散領域に形成された、前記第 4の拡散領域から前記第 2の拡散領域 に対する前記第 2極性のバックバイアス電圧を印加するための第 3の電源端子とを有 することを特徴とする請求項 11記載の半導体回路装置システム。  A second power supply terminal formed in the third diffusion region for applying the first polarity back bias voltage from the third diffusion region to the first diffusion region; and A third power supply terminal for applying a back bias voltage of the second polarity from the fourth diffusion region to the second diffusion region formed in the diffusion region. 11. The semiconductor circuit device system according to 11.
[13] 第 1導電型の半導体基板上に第 2導電型の第 4の拡散領域を形成するステップと、 前記第 4の拡散領域内に第 1導電型の第 3の拡散領域を形成するステップと、 前記第 3拡散領域内に第 1導電型の第 1の拡散領域と第 2導電型の第 2の拡散領域 とを形成するステップを有することを特徴とする半導体回路装置の製造方法。  [13] A step of forming a second conductivity type fourth diffusion region on the first conductivity type semiconductor substrate, and a step of forming a first conductivity type third diffusion region in the fourth diffusion region And a step of forming a first conductivity type first diffusion region and a second conductivity type second diffusion region in the third diffusion region.
[14] 前記半導体回路装置の製造方法はさらに、  [14] The method for manufacturing the semiconductor circuit device further includes:
前記第 1の拡散領域上に第 2導電型のトランジスタを形成するとともに、前記第 2の拡 散領域上に第 1導電型のトランジスタを形成するステップと、  Forming a second conductivity type transistor on the first diffusion region, and forming a first conductivity type transistor on the second diffusion region;
前記第 3の拡散領域上に第 1極性のバックバイアス電圧を印加するための電源端子 を形成するとともに、前記第 4の拡散領域上に前記第 1極性とは異なる第 2極性のバ ックバイアス電圧を印加するための電源端子を形成するステップを有することを特徴 とする請求項 13記載の半導体回路装置の製造方法。  A power supply terminal for applying a back bias voltage of the first polarity is formed on the third diffusion region, and a back bias voltage of a second polarity different from the first polarity is applied on the fourth diffusion region. 14. The method of manufacturing a semiconductor circuit device according to claim 13, further comprising a step of forming a power supply terminal for applying.
[15] 第 1導電型の半導体基板と、 [15] a first conductivity type semiconductor substrate;
前記第 1導電型とは異なる第 2導電型のトランジスタが形成された第 1導電型の第 1 の拡散領域と、  A first conductivity type first diffusion region in which a second conductivity type transistor different from the first conductivity type is formed;
第 1導電型のトランジスタが形成された第 2導電型の第 2の拡散領域と、 第 1極性のバックバイアス電圧が印加される第 1導電型の第 3の拡散領域とを有する ことを特徴とする半導体回路装置。 A second conductivity type second diffusion region in which a first conductivity type transistor is formed; And a third diffusion region of a first conductivity type to which a back bias voltage of the first polarity is applied.
PCT/JP2006/314900 2006-07-27 2006-07-27 Semiconductor circuit device, semiconductor circuit device system, and manufacturing method for the semiconductor circuit device WO2008012899A1 (en)

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JP2014146220A (en) * 2013-01-30 2014-08-14 Fujitsu Semiconductor Ltd Method for designing semiconductor device, program, and design device
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