JPH04118964A - Thin film transistor - Google Patents

Abstract

PURPOSE:To easily realize CMOS constitution by forming at least one each of channel areas of different conductivity types on the upper and lower surfaces of one active region. CONSTITUTION:In this thin film transistor which has a plurality of source-drain areas and the active region of which is interbedded between two gate electrodes 3 and 3', channels of different conductivity types can be formed on the upper and lower surfaces of the active area 1 and an n- and p-channel thin transistors can be operated respectively in the two channels. When the n-channel is formed, moreover, no carrier delivery and reception are performed and the p-channel thin film transistor does not rely on the operating state of the n-channel thin film transistor, since a p-n junction is formed between the source-drain area of the p-channel thin film transistor and the n-channel. When the p-channel is formed, the same thing happens. Therefore, these two thin film transistors can be operated independently.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor formed on an insulating substrate.

[Background Art] In recent years, semiconductor technology has made remarkable progress, and it has become possible to integrate more than one million transistors on a chip with an area of several squares. The miniaturization and higher functionality of integrated circuits (ICs) are not only about reducing costs by improving the yield of the devices themselves and increasing the added value of semiconductor devices, but also about the use of these ICs. It can be expected that the device will be made smaller and cheaper. Therefore, it is expected that high integration will continue to increase in the future.

BACKGROUND ART One of the semiconductor devices that is currently widely used is a CMOS transistor, which has a configuration in which an NMOS transistor and a PMOS transistor coexist. FIG. 8 shows a cross-sectional view of a conventional CMOS transistor. NMOS
In order to fabricate a transistor and a PMO3h transistor on the same -Si substrate, a p-well region that will become the active region of the NMOS transistor is formed as shown in FIG.
An S transistor is being manufactured. In such a transistor with 0MO3 configuration, an NMOS transistor or a P
Compared to using a MOS transistor alone, this has the advantage that power consumption can be significantly reduced and the operating margin can be widened.

However, since it is manufactured using a conductive Si substrate, it is difficult to ensure electrical independence between the elements.

If the isolation between elements is not sufficient, the transistors will not operate properly due to parasitic capacitance and parasitic resistance from adjacent transistors. Therefore, there was a problem that transistors could not be laid out in a high-density layout.

On the other hand, one of the semiconductor technology fields that has recently attracted particular attention is 5OI (Silicon on Insulator).
There is a n on In5ulator) element. This is a thin film transistor made from a single crystal or polycrystalline Si thin film formed on an insulating substrate. When a circuit is constructed using these thin film transistors, the thin film transistors can be arranged in high density because each transistor is electrically independent.

For example, if an inverter circuit is constructed using conventional CMOS thin film transistors, the structure shown in FIG. 7 will be formed. That is, the gate electrodes 3 of the n-type thin film transistor and the p-type thin film transistor are connected together, and the drain 5 of the n-type thin film transistor and the drain 8 of the p-type thin film transistor are also connected. 7th
As can be seen from the figure, unlike the case of fabrication using the Si substrate described above, SOI devices can ensure electrical independence between elements, so the spacing between transistors can be narrowed to the limit of processing rules, resulting in higher density. This makes it possible to realize a transistor array.

[Problems to be solved by the invention] However, in order to achieve even higher integration, the geometric size of thin film transistors must be made finer, and it is necessary to develop microfabrication techniques that require precision on the order of submicrons and short channels. There is a need to prevent deterioration of transistor characteristics due to transistor size, such as effectiveness, and various research institutes are currently actively researching and developing it.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor that can be highly integrated using current processing technology and that can easily be configured to have an 0MO3 structure.

[Means for Solving the Problems] In order to solve the above problems, the thin film transistor of the present invention includes at least one channel region having different conductivity types formed on the upper surface and the lower surface of one active region. Features.

Further, in the thin film transistor of the present invention, at least two sets of source/drain regions of different conductivity types contacting one active region are formed opposite to each other or adjacent to each other, and the source/drain regions are formed on the upper and lower surfaces of the active region. A gate electrode is formed corresponding to the drain region, and at least two channel regions having different conductivity types are formed on the upper and lower surfaces of the active region between the source and drain regions.

[Effect]

In the present invention, by proposing a new thin film transistor structure in which channel regions of different conductivity types are formed on the upper and lower surfaces of one active region, at least two transistors can be manufactured for one active region, and the thin film transistor occupies By reducing the area involved, high integration can be easily achieved without developing new equipment or processing technology.

〔Example〕

FIG. 1 is a plan view of a thin film transistor according to the present invention, and FIG. 2 is a cross-sectional view taken along the line A--A in FIG. The thin film transistor according to the present invention has a plurality of source/drain regions (two in this example), and has a structure in which the active region 1 is sandwiched vertically by two gate electrodes 3 and 3'. is a major feature. In the thin film transistor according to the present invention, channels with different conductivity types can be formed on both the upper and lower surfaces of the active region l by the two gate electrodes, and one channel is an n-channel thin film and the other is a p-channel thin film. Transistors can be operated. Furthermore, n
When a channel is formed, a pn junction is formed between the source/drain region of the n-channel thin film transistor and the n-channel, so carriers are not exchanged.
The n-channel thin film transistor does not depend on the operating state of the n-channel thin film transistor. Moreover, the same thing can be said when an n-channel is formed, so these two thin film transistors can operate completely independently. In the thin film transistor of the present invention, one type of two
This means that two transistors are stacked one above the other, so it can be said that n-channel thin film transistors and n-channel thin film transistors are arranged three-dimensionally.

Next, a method for manufacturing a thin film transistor according to the present invention will be explained with reference to FIG. FIG. 3 shows a plan view at each step and a sectional view taken along the line A'-A'.

The gate electrode 3 and gate insulating film 2 shown in FIG. 3(a) are formed on an insulating substrate, such as a glass substrate, by sputtering or CVD. Next, as shown in FIG. 3(b), after forming the gate of the active region 1 of single-crystal Si or polycrystalline St film on the gate insulating film 2,
' and gate electrode 3' are formed in the same manner as in (a). As shown in FIG. 3C, phosphorus (P) is ion-implanted to form source A4 and drain regions having n-type conductivity. At this time, other regions are covered with a mask 6 such as resist to prevent ion implantation. Similarly, the source B7 and drain regions are formed by ion implantation. The result is as shown in FIG. 3(d). However, so that the conductivity type is p-type, boronate (B) is used.
This is done by ion implantation. Finally, after activation annealing is performed, metal wiring, for example Al wiring 9, is formed so as to be electrically connected to the outside, completing the process as shown in FIG. 3(e).

FIG. 4 shows an example of the structure of a thin film transistor according to the present invention. In this figure, the gate electrode is omitted for convenience. The difference in structure is the arrangement of the source and drain regions for n-channel and the source and drain regions for n-channel.

In FIG. 4(a), the source and drain are arranged facing each other, and in FIG. 4(b), the source and drain are arranged adjacent to each other. The arrows in the figure each represent the direction in which the majority carriers flow. That is, in (a) the flow of electrons and the flow of holes are orthogonal, and in (b) the electrons and holes flow in separate regions.

However, since the position of the channel region through which electrons or holes flow is different from the upper and lower surfaces of the active region, (
The difference between a) and (b) is only in the effective channel length and channel width, and there is little difference in device characteristics. Also,
Even if the source/drain regions for n-channel and n-channel in the figure are exchanged, there is no major difference in terms of the gist of the present invention, and it is sufficient to select a configuration that is easy to layout when integrated. The manufacturing method is shown in (a) in Fig. 4.
), but if the position of the mask 6 in (c) and (d) of FIG. 3 is changed, (b) of FIG.
) configuration is also applicable.

An example of application of the thin film transistor of the present invention is shown in FIG. 5(a). In FIG. 1, the drain A and drain B are electrically connected. FIG. 5(b) shows an equivalent circuit with such a configuration. As can be seen from this figure, it is completely equivalent to an inverter circuit with a 0MO3 configuration. Conventionally, a CMOS inverter circuit is constructed using two transistors, an n-channel transistor and an n-channel transistor, but by using the thin film transistor of the present invention, only one transistor is required, and the area occupied by the transistor can be reduced. FIG. 6 shows, for comparison, an example in which there is only one gate electrode on the upper surface of the active region 1. Although an inverter circuit can be constructed with the configuration shown in FIG. 6, only a so-called push-pull type inverter circuit is possible because the gate electrodes are common. In contrast, in the embodiment of the present invention, since separate voltages can be applied to the gate electrodes of the n-channel and n-channel TPT, not only the bush-pull type in which the potential of the upper and lower gate electrodes is the same, but also the It is also possible to configure an inverter circuit such as a current sink (Current-3 ink) type inverter circuit that applies different potentials. Furthermore, by using the thin film transistor of this embodiment in circuits other than inverter circuits, it is possible to efficiently lay out a circuit with an 0MO3 configuration, and it is easy to achieve high integration.

Although the present invention has been specifically explained above based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various changes can be made without departing from the gist thereof.

[Effects of the Invention] As explained above, the thin film transistor according to the present invention has a structure in which the active region of multiple thin film transistors is shared or the active region is sandwiched between gate electrodes. - Can have the same functionality. Therefore, it is possible to easily implement the 0MO3 configuration, and it is also possible to reduce the area occupied by the thin film transistor, which has the advantage that high integration can be easily achieved even with current processing technology. Furthermore, since the active region is shared, there is an advantage that transistor characteristics can be made more uniform compared to the case where thin film transistors are manufactured separately.

[Brief Description of the Drawings] Fig. 1 is a plan view of a thin film transistor according to the present invention, Fig. 2 is a plan view of a thin film transistor according to the present invention;
The figure is a sectional view taken along the line A-A in Figure 1, and Figure 3 (a
) to (e) are diagrams for explaining the manufacturing method of the thin film transistor according to the present invention, FIGS. 4(a) and (b) are examples of the structure of the thin film transistor according to the present invention, and FIGS. 5(a) and (b)
6(a) and 6(b) are diagrams showing an embodiment of a thin film transistor according to the present invention, FIGS. 6(a) and (b) are diagrams showing an embodiment in which only one gate electrode is used, and FIGS. 7(a) and (b) are diagrams showing a conventional thin film transistor. 0MO3 of
A plan view and a cross-sectional view of an inverter circuit constructed of thin film transistors, and FIG. 8 is a cross-sectional view of a conventional CMOS transistor. 1... Active region 2... Gate insulating film 3... Gate electrode 4... Source A 5... Drain A 6... Mask 7... Source B 8... Drain B 9.・AI wiring

Claims (1)

[Claims] 1. A thin film transistor characterized in that at least one channel region of different conductivity type is formed on the upper surface and the lower surface of one active region. 2. At least two sets of source/drain regions of different conductivity types in contact with one active region are formed opposite to each other or adjacent to each other, and are formed on an upper surface and a lower surface of the active region corresponding to the source/drain regions. A thin film transistor characterized in that a gate electrode is formed, and at least two channel regions of different conductivity types are formed on an upper surface and a lower surface of the active region between each of the source and drain regions.