WO2008012899A1 - Dispositif de circuit à semi-conducteurs, système de dispositif de circuit à semi-conducteurs et procédé de fabrication pour le dispositif de circuit à semi-conducteurs - Google Patents

Dispositif de circuit à semi-conducteurs, système de dispositif de circuit à semi-conducteurs et procédé de fabrication pour le dispositif de circuit à semi-conducteurs Download PDF

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Publication number
WO2008012899A1
WO2008012899A1 PCT/JP2006/314900 JP2006314900W WO2008012899A1 WO 2008012899 A1 WO2008012899 A1 WO 2008012899A1 JP 2006314900 W JP2006314900 W JP 2006314900W WO 2008012899 A1 WO2008012899 A1 WO 2008012899A1
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WIPO (PCT)
Prior art keywords
diffusion region
type
conductivity type
circuit device
semiconductor circuit
Prior art date
Application number
PCT/JP2006/314900
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English (en)
Japanese (ja)
Inventor
Hiroshi Katakura
Original Assignee
Fujitsu Limited
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Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2006/314900 priority Critical patent/WO2008012899A1/fr
Publication of WO2008012899A1 publication Critical patent/WO2008012899A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a technology for performing back bias control for reducing leakage current in a semiconductor circuit device.
  • Patent Document 1 discloses a back bias setting method in a MOS (Metal Oxide Semiconductor) circuit.
  • Leakage current refers to current that flows to the gate regardless of the operation of the transistor because the positional relationship between the source and the drain becomes closer as the transistor element becomes smaller due to miniaturization of the process.
  • the back bias control technique enables the leakage current at the gate of the transistor to be reduced by applying a negative bias to the entire semiconductor substrate in the direction in which the backside force current of the electronic device is difficult to flow.
  • FIGS. 8 to 10 are diagrams for explaining a back bias control method in a conventional semiconductor circuit device, and FIG. 8 is a side sectional view schematically showing a configuration of a back-input controlled 2-input NAND circuit.
  • FIG. 9 is a plan view schematically showing wiring in the second layer of the power wiring metal, and
  • FIG. 10 is a plan view schematically showing a part of the power wiring metal first layer in an enlarged manner.
  • the conventional two-input NAND circuit 100 shown in FIG. 8 is configured by forming NMOS transistors 61 and 62 on a P-type conductive semiconductor substrate 51 (hereinafter referred to as P-type substrate) 51.
  • a second N-type well 53 having N-type conductivity is formed so as to surround the type 52 and the first N-type 54 having N-type conductivity by forming PMOS transistors 63 and 64. It is constituted by.
  • the second N-type well 53 electrically isolates the first P-type well 52 and the first N-type well 54 from the P-type substrate 51.
  • the symbol G in the figure indicates the gate.
  • the ground voltage Vss is supplied to the NMOS transistors 61 and 62 via the wiring L1, and the power supply voltage Vdd is supplied to the PMOS transistors 63 and 64 via the wiring L2.
  • the 2-input NAND circuit 100 is configured so that the back bias voltage VBN1 is applied by pulling the wiring L3 to the P + region 65 power supply wiring metal layer (see Fig. 9) formed in the first P-type well 52. At the same time, it is possible to perform knock bias control by drawing the wiring L4 from the N + region 66 formed in the first N-type well 54 to the power distribution metal layer and applying the back bias voltage VBP1. Yes.
  • the P-type substrate 51 is partitioned in a matrix by a plurality of sites 71 and power supply wiring regions 72, which are arrangement regions for transistors and the like, and in one direction (vertical direction in FIG. 9).
  • a plurality of sites 71 are continuously formed in the direction), and the sites 71 and the power supply wiring regions 72 are alternately formed in the other direction (the horizontal direction in FIG. 9).
  • Each site 71 is provided with a first P-type 52 or a first N-type 54, and in the example shown in FIG.
  • the 1st N type uel 54 is formed alternately and repeatedly.
  • the power supply wiring area 72 includes a power supply wiring area 721 that supplies power to the first N-type well 54 and a power supply wiring area 722 that supplies power to the first P-type well 52.
  • a power supply wiring region 721 is formed adjacent to the first N-type well 54, and a power supply wiring region 722 is formed adjacent to the first P-type well 52. That is, for the P-type substrate 51, the power supply wiring region 72 is formed adjacent to each site 71, and power is supplied to each site 71.
  • the second layer of the power wiring metal formed as a layer different from the layer in which the NMOS transistors 61 and 62 and the PMOS transistors 63 and 64 are formed is shown in FIG. As shown, the wirings L1 to L4 are formed in parallel.
  • the power wiring metal first layer formed as a layer lower than the power wiring metal second layer in the P-type substrate 51 and different from the layer in which the NMOS transistors 61 and 62 and the PMOS transistors 63 and 64 are formed.
  • the direction in which the wires Ll to L4 are disposed (the vertical direction in the drawing of FIG. 9) and the direction perpendicular to the drawing (the horizontal direction in the drawing of FIG. 9) Wirings L1 to L4 are formed.
  • the wirings LI and L3 are formed so as to overlap the first P-type well 52, and the wirings L2 and L4 are formed so as to overlap the first N-type well 54.
  • the wiring 73 in the first layer of the power wiring metal is electrically connected to the wiring L4 in the second layer of the power wiring metal by the contact 73 formed from the first layer of the power wiring metal to the second layer of the power wiring metal. It is connected.
  • the contacts 74, 75, and 76 formed from the first layer of the power wiring metal to the second layer of the power wiring metal cause the wiring in the first layer of the power wiring metal and the second layer of the power wiring metal.
  • L2, L3, and L1 are electrically connected to each other.
  • the contact 73 is connected to the wiring M 11, and this wiring Ml 1 is connected to the IN type well 54 through the contact 78.
  • the contact 75 is connected to the wiring M12, and this wiring M12 is connected to the first P-type well 54 via the contact 79.
  • the back bias voltages VBN 1, VBP 1, Vss, and Vdd are supplied to the first P-type well 52 and the first N-type well 54 formed at the site 71 in the conventional semiconductor circuit device. It has come to be.
  • Patent Document 1 International Publication WO00Z45437 Pamphlet
  • the present invention was devised in view of such problems, and in a semiconductor circuit device, a power supply wiring region is reduced by pulling out a contact for supplying a back bias voltage from the outer periphery of the site matrix. At the same time, the purpose is to secure a normal logic circuit layout area.
  • a semiconductor circuit device of the present invention includes a first conductive type in which a first conductive type semiconductor substrate and a second conductive type transistor different from the first conductive type are formed.
  • the first conductivity type first diffusion region and the second conductivity type second diffusion region form a transistor placement region, and the semiconductor circuit device is formed in the placement region.
  • a first power supply terminal for supplying a voltage to the transistor, and the third diffusion region force formed in the third diffusion region is also a back bias having a first polarity with respect to the first diffusion region.
  • the third power supply terminal may be further provided.
  • the semiconductor circuit device is further On the first conductive type semiconductor substrate, the first conductive type fifth and seventh diffusion regions, and the second conductive type sixth diffusion region, A second conductivity type transistor is formed on the sixth diffusion region, and a first conductivity type transistor is formed on the sixth diffusion region.
  • a back bias voltage is applied to the fifth and sixth diffusion regions. It may be configured not to.
  • the third diffusion region is formed such that its longitudinal direction forms a predetermined angle with respect to the longitudinal direction of the fourth diffusion region. Further, the predetermined angle may be configured to be 90 degrees.
  • a semiconductor circuit device of the present invention includes a fourth diffusion region of a second conductivity type different from the first conductivity type formed on the first conductivity type semiconductor substrate, and a fourth diffusion region in the fourth diffusion region.
  • a first conductivity type transistor formed on the second diffusion region and a power supply terminal for applying a second bias knock bias voltage different from the first polarity in the fourth diffusion region force It is characterized by having. Further, the third diffusion region and the fourth diffusion region are formed so that the longitudinal direction of the third diffusion region and the longitudinal direction of the fourth diffusion region are at a predetermined angle. May be. Further, the predetermined angle may be 90 degrees.
  • the combination of the first conductivity type and the second conductivity type is a combination of P type and N type or a combination of N type and P type, respectively.
  • a semiconductor circuit device system of the present invention includes a semiconductor circuit device and a power supply device that supplies a voltage to the semiconductor circuit device.
  • the semiconductor circuit device includes a first conductivity type semiconductor substrate, the first A first conductivity type first diffusion region in which a second conductivity type transistor different from the first conductivity type is formed; and a second conductivity type second diffusion region in which the first conductivity type transistor is formed; The first conductivity is applied with the back bias voltage of the first polarity from the power supply device.
  • a third diffusion region of a mold and a fourth diffusion region of a second conductivity type to which a back bias voltage having a second polarity different from the first polarity is applied. It is a circuit device system.
  • the first conductivity type first diffusion region and the second conductivity type second diffusion region form a transistor arrangement region and are formed in the arrangement region.
  • a first power supply terminal for supplying a voltage to the transistor, and the third diffusion region force formed in the third diffusion region also has the first polarity with respect to the first diffusion region.
  • a second power supply terminal for applying a back bias voltage and the fourth diffusion region force formed in the fourth diffusion region also have a back bias voltage of the second polarity with respect to the second diffusion region.
  • a third power supply terminal for applying voltage includes the step of forming a second conductivity type fourth diffusion region on a first conductivity type semiconductor substrate;
  • the method for manufacturing the semiconductor circuit device further includes forming a second conductivity type transistor on the first diffusion region and forming a first conductivity type transistor on the second diffusion region; Forming a power supply terminal for applying a back-bias voltage of the first polarity on the third diffusion region and a second-polarity knock bias different from the first polarity on the fourth diffusion region; A step of forming a power supply terminal for applying a source voltage may be included.
  • a semiconductor circuit device of the present invention includes a first conductivity type semiconductor substrate, a first conductivity type first diffusion region in which a second conductivity type transistor different from the first conductivity type is formed, and A second conductivity type second diffusion region in which a first conductivity type transistor is formed; and an i th conductivity type third diffusion region to which a back bias voltage of the first polarity is applied.
  • the present invention has at least one of the following effects or advantages.
  • Wiring can be reduced, and by reducing the power supply wiring area, it is possible to secure a normal logic circuit arrangement area and increase the density.
  • FIG. 1 is a side sectional view schematically showing a configuration of a semiconductor circuit device as a first embodiment of the present invention.
  • FIG. 2 is a plan view for explaining a wiring state of the semiconductor circuit device as the first embodiment of the present invention.
  • FIG. 3 is a plan view for explaining a well arrangement in the semiconductor circuit device as the first embodiment of the present invention.
  • FIG. 4 is a side sectional view schematically showing a configuration of a modification of the semiconductor circuit device according to the first embodiment of the present invention.
  • FIG. 5 is a plan view for explaining a well arrangement in a semiconductor circuit device as a modification of the first embodiment of the present invention.
  • FIG. 6 is a side sectional view schematically showing a configuration of a semiconductor circuit device according to a second embodiment of the present invention.
  • FIG. 7 is a side sectional view schematically showing a configuration of a modified example of the semiconductor circuit device according to the first embodiment of the present invention.
  • FIG. 8 is a diagram for explaining a back bias control method in a conventional semiconductor circuit device.
  • FIG. 9 is a diagram for explaining a back bias control method in a conventional semiconductor circuit device.
  • FIG. 10 is a diagram for explaining a back bias control method in a conventional semiconductor circuit device.
  • FIG. 11 is a diagram schematically showing a configuration of a semiconductor circuit device system as one embodiment of the present invention.
  • FIG. 1 is a side sectional view schematically showing the configuration of the semiconductor circuit device as the first embodiment of the present invention
  • FIG. 2 is a plan view for explaining the wiring state
  • FIG. 3 is a plan view for explaining the arrangement of the wells in the semiconductor circuit device la according to the first embodiment, and schematically shows the arrangement of the respective wells.
  • the semiconductor circuit device (semiconductor circuit device system) la is configured by a technology such as a gate array or a standard cell method, and is used in an information processing device, for example.
  • a technology such as a gate array or a standard cell method
  • P-type substrate (semiconductor substrate) 10 1st N-type well (second diffusion region) 11, 1st P-type well (first diffusion region) 13, 2nd P-type well (third A diffusion region) 14 and a second N-type well (fourth diffusion region) 12 are provided, and a power supply device 201 (see FIG. 11) is further provided.
  • the semiconductor circuit device includes a digital circuit.
  • inverter circuit 30a that is a CMOS (Complementary Metal Oxide Semiconductor) circuit is formed as the semiconductor circuit device la will be described.
  • CMOS Complementary Metal Oxide Semiconductor
  • the P-type substrate 10 is a semiconductor substrate having P-type (first conductivity type) conductivity.
  • an N-type (second type) different from the P-type substrate 10 is used.
  • a second N-type well (fourth diffusion region) 12 having conductivity of the conductivity type is formed.
  • the first P-type well (first diffusion region) 13, the first N-type well (second diffusion region) 11, and the second P-type well (third diffusion region). ) 14 is formed, and the second N-type well 12 electrically separates the first P-type well 13, the first N-type well 11 and the second P-type well 14 and the P-type substrate 10.
  • the first N-type well 11 is formed with various elements such as resistors, capacitors, diodes, transistors, etc. on its surface (upper surface in the example shown in FIG. 1), and has N-type conductivity. Configured.
  • a P-type transistor (P-type transistor) 302 is formed on the first N-type well 11, and the P + regions 22-1, 22 -2 are formed in the first N-type well 11.
  • the gate 32 is formed in an insulated state through an oxide film or the like (not shown).
  • the power supply voltage Vdd is supplied to the P + region 22-1 through the wiring L12. It has become so.
  • the symbol G represents the gate and the symbol D represents the drain.
  • the first P-type well 13 has various elements such as resistors, capacitors, diodes, transistors, etc. formed on its surface (upper surface in the example shown in FIG. 1), and has P-type conductivity. Been Yes.
  • an N-type transistor (N-type transistor) 301 is formed on the first P-type well 13 and an N + region 23-1, 23-2 force S is formed.
  • the gate 31 is formed in an insulated state through an oxide film (not shown), and the ground voltage Vss is supplied to the N + region 23-2 through the wiring L13. Yes.
  • the first N-type well 11 and the first P-type well 13 form a transistor arrangement region.
  • the N + region 23-1 of the 1st P-type wel 13 and the P + region 22-2 of the 1st N-type wel 11 are connected as a drain output (X), and the gate 31 of the 1st P-type wel 13 and the 1st N-type wel 11 gate 32 is connected as gate input (A).
  • a site region 41 composed of a plurality of rectangular shaped sites 411 and a power supply wiring region 42 composed of a plurality of rectangular power supply wiring regions 421, 422 are provided.
  • the site areas 41 and the power supply wiring areas 42 are alternately arranged.
  • the site region 41 In the site region 41, the direction orthogonal to the direction in which the site regions 41 and the power supply wiring regions 42 are alternately arranged (in the example shown in FIG. 2, the horizontal direction in the drawing), the vertical direction in the drawing, in the example shown in FIG. ), The 1st N-type wel 11 and the 1st P-type wel 13 are alternately arranged. Further, in the power supply wiring area 42, the direction perpendicular to the direction in which the site areas 41 and the power supply wiring areas 42 are alternately arranged (the horizontal direction in the example in FIG. 2) (the vertical direction in the example in FIG. 2). Direction), power supply wiring regions 421 and power supply wiring regions 422 are alternately and repeatedly formed.
  • a plurality of rectangular sites 411 and power supply wiring regions 421 and 422 are formed (partitioned) in a matrix shape, and one direction thereof (in the example shown in FIG. ) And a plurality of sites 411 are formed continuously, and the sites 411 and the power supply wiring regions 42 are alternately formed in the other direction (the horizontal direction in the example shown in FIG. 2).
  • Each site 411 is formed with the first P-type well 13 or the first N-type well 11 described above.
  • p-type wel 13 and 1st n-type wel 11 and force It is.
  • the first N-type well 11 and the first P-type well 13 are alternately and repeatedly arranged in a matrix in parallel or substantially in parallel with each other.
  • site matrix the entire region where the site 411 and the power supply wiring regions 421 and 422 are formed in a matrix on the P-type substrate 10 may be referred to as a site matrix.
  • the power supply wiring area 42 includes a power supply wiring area 421 that supplies power to the first N-type wel 11 and a power supply wiring area 422 that supplies power to the first P-type wel 13.
  • a power supply wiring region 421 is formed adjacent to the first N-type well 11, and a power supply wiring region 422 is formed adjacent to the first P-type well 13.
  • the power supply wiring region 42 is formed adjacent to each site 411, and power is supplied to each site 411.
  • first N-type well 11, first P-type well 13 and power supply wiring regions 42, 422 may be referred to as a site array portion 43.
  • the second N-type well 12 is formed on the P-type substrate 10 as a region that includes cytolytics (a plurality of site array portions 43), and on the P-type substrate 10,
  • the P-type substrate 10 and the first N-type well 11, the first P-type well 13, and the second P-type well 14 are formed so as to be electrically separated.
  • the second P-type well 14 is disposed so as to be in electrical communication with at least a portion of the first P-type well 13 and is connected to the P + region (power supply terminal). , Contact) 26 is formed.
  • the P + region 26 is supplied with the first polarity knock bias voltage VBBN from the power supply device 201 (see FIG. 11).
  • an N + region (power supply terminal, contact) 21 is formed in the second N-type well 12.
  • the power supply device 201 receives the first polarity and the first polarity.
  • the knock bias voltage VBBP having a different second polarity is applied (supplied).
  • the power supply wiring metal second layer formed as a layer different from the layer in which the N-type transistor 301 and the P-type transistor 302 are formed has a power supply wiring region 421,
  • the wiring L12 and the wiring L13 are formed in parallel along the arrangement direction 422 (the vertical direction in FIG. 2).
  • the wirings L12 and L13 are formed in the direction perpendicular to the direction in which the wirings L12 and L13 are formed in the second power supply metal layer (the horizontal direction in FIG. 2). Yes.
  • a wiring L 12 is formed along the longitudinal direction of the first N-type well 11 so as to overlap the first N-type well 11, and overlaps the first P-type well 13.
  • a wiring L13 is formed along the longitudinal direction of the first P-type well 13.
  • the contact 17 formed from the first layer of the power distribution metal to the second layer of the power wiring metal causes the wiring L12 in the first layer of the power wiring metal to be electrically connected to the wiring L12 of the second layer of the power wiring metal. It is connected.
  • the wiring L12 is formed along the edge of the site 411 at the upper side of the paper, and the wiring L13 is placed near the lower mold of the paper at the site 411.
  • the contacts 17 and 18 are also formed close to the end of the site 411.
  • the second P-type well 14 is disposed and formed so as to be in contact with at least a part of the first N-type well 11, the first P-type well 13 and the power supply wiring regions 421 and 422 forming the site array unit 43. ing.
  • the second P-type well 14 is formed in a plane elongated shape, and in the longitudinal direction (the vertical direction in FIG. 3), the first N It is arranged and formed so that it intersects (orthogonally) at a predetermined angle (90 degrees or almost 90 degrees) with the longitudinal direction of the mold wel 11 and the first P wel 13 (lateral direction in FIG. 3).
  • one second P-type well 14 force is formed so as to cross and contact with a plurality of site array parts 43 in the longitudinal direction.
  • the mold wel 11 and the second N-type wel 12 are arranged so that they intersect (directly intersect) at a predetermined angle (90 degrees or almost 90 degrees). It is arranged and formed so that the longitudinal direction of the 2P-type well 14 intersects (orthogonally) at a predetermined angle (90 degrees or almost 90 degrees).
  • the semiconductor circuit device la according to the first embodiment has a triple wel structure including the second N-type wel 12, the second P-type wel 14 and the first N-type wel 11 (or the first P-type wel 13). It can be said.
  • the second P-type well 14 and the first N-type well 11 and the first P-type well 13 formed in a plane elongated shape have an angle of 90 degrees or almost 90 degrees.
  • Crossing (orthogonal) force The second P-type well 14 is not limited to this, but at least partially abuts against the first N-type well 11 and the first P-type well 13 (polymerization).
  • the position and shape of the 1N-type wel 11 and the 1P-type wel 13 that intersect at an angle other than 90 degrees may be variously modified. Can be implemented.
  • a back bias voltage is applied to the second P-type well 14 in a region that does not overlap with the site array portion 43 in the second P-type well 14, that is, outside the site matrix in the second P-type 14 (outer peripheral portion).
  • a contact 141 for electrically connecting the metal layer (not shown) for supplying VBBN and the second P-type well 14 is formed, and a power supply device 201 (see FIG. 11) is connected to the contact 141.
  • the first polarity back bias voltage VBBN supplied from the power supply device 201 is applied to the second P-type well 14 via the S contact 141. That is, this contact 141 force corresponds to the P + region 26 in FIG.
  • a contact layer 123 for electrically connecting the metal layer (not shown) for supplying the back bias voltage V BBP to the second N-type well 12 and the second N-type well 12 is formed.
  • a power supply device 201 (see FIG. 11) is connected to.
  • the second polarity back bias voltage VBBP supplied from the power supply device 201 is applied to the second P-type well 12 via the S contact 123. This corresponds to N + region 21 in 1.
  • the back bias voltage VBBN is applied to the first P-type well 13 via the second P-type well 14, and the back bias voltage VBBP to the first N-type well 11 is applied to the second N-type well 14. It is done through uel 12.
  • the semiconductor circuit device la of the first embodiment for example, after the second N-type well 12 is formed on the P-type substrate 10, the second P-type well 14 is grown, and then the first N-type
  • the semiconductor circuit device la can be manufactured by forming the wel 11 and the first P-type wel 13 and then performing a transistor bulking process (BULK) manufacturing process, a process for manufacturing each power supply terminal and wiring, and the like. .
  • BULK transistor bulking process
  • the contact 141 in the region where the site array portion 43 is absent in the second P-type well 14, the contact 141 (P + region 26)
  • the back bias voltage VBBN is applied to the second P-type well 14 and the contact 123 (N + region 21) force is applied to the second N-type well 12 in the region where the site array part 43 and the second P-type well 14 are absent.
  • the back bias voltage VBB P is applied to the wel 12.
  • the second P-type is supplied by the back bias voltage V BBN applied from the power supply device 201 through the P + region 26.
  • the N-channel MOS (NMOS) transistor is controlled via the well 14 and the first P-type well 13, and the second N-type well 12 is supplied by the back bias voltage VBBP supplied from the power supply 201 via the N + region 21. Further, by controlling the P-channel MOS (PMOS) transistor via the first N-type well 11, the back noise control of the inverter circuit 30a is performed.
  • the reverse bias voltage is applied so that the pell is directly minus if the well voltage just below the transistor is NMOS, and the nwell is plus if PMOS. Become! /
  • the power supply wiring In area 42 (power supply wiring areas 421 and 422), it is not necessary to arrange and form wiring and contacts to supply the back bias voltages VBBN and VBBP.
  • the area occupied by the regions (421, 422) can be reduced, and the density of the semiconductor circuit device la can be increased.
  • the number of wiring channels can be increased.
  • the power wiring area 42 since there is no contact or the like for supplying back bias voltages V BBN and VBBP to the power wiring area 42 (power wiring areas 421 and 422), the power wiring area 42 In this case, for example, a logic circuit such as a transistor can be arranged and formed below the metal layer, and this can also increase the density of the semiconductor circuit device la.
  • the leakage current can be reduced and the power consumption can be reduced.
  • the back bias voltage VBBN is applied via the second P-type well 14 and the back bias voltage VBBP is applied via the second N-type well 12.
  • the back bias control is performed for both the NMOS transistor and the PMOS transistor, but the present invention is not limited to this.
  • the NMOS transistor and the PMOS formed on the P-type substrate 10 are not limited thereto. Only one of the transistors may be applied with a back bias voltage through the well.
  • FIG. 4 is a side sectional view schematically showing a configuration of a modified example of the semiconductor circuit device according to the first embodiment of the present invention.
  • FIG. 5 is a side view of the semiconductor circuit device lb as a modified example of the first embodiment.
  • FIG. 6 is a plan view for explaining a cell arrangement. In FIG. 5, for convenience, a part of the semiconductor circuit device lb is extracted and shown.
  • the semiconductor circuit device lb as a modified example of the first embodiment is configured by, for example, a technology such as a gate array or a standard cell system. Etc. are used.
  • an inverter circuit 30b that is a CMOS circuit is formed as a semiconductor circuit device lb as a modification of the first embodiment will be described.
  • the semiconductor circuit device lb includes a P-type substrate (semiconductor substrate) 10, a first N-type well (second diffusion region) 11, a first P-type well (first diffusion region) 13 and A second N-type well (fourth diffusion region) 12 is configured, and a first polarity knock bias voltage VBBN is applied from the power supply 201 (see FIG. 11) to the P + region (power supply terminal) 261.
  • Back bias voltage with a second polarity different from the first polarity VBBP force The power is supplied from the power supply 201 (see Fig. 11) via the N + region (power terminal) 21 formed in the second N-type well 12. Yes.
  • the semiconductor circuit device lb as a modification of the first embodiment has N-type (second conductivity type) conductivity on a P-type substrate 10 having P-type (first conductivity type) conductivity.
  • a second N-type wel 12 is formed, and on the second N-type wel 12, a first P-type wel 13 and a first N-type wel 11 are formed.
  • the wel 13 and the first N-type wel 11 and the P-type substrate 10 are electrically separated.
  • a P-type transistor (P-type transistor) 302 is formed on the first N-type well 11.
  • An N-type transistor (P-type transistor) 301 is formed on the first P-type well 13, and N + regions 23-1, 23-2 and 31 are formed, and a P + region 261 is formed.
  • the knock bias voltage VBBN is applied from the power supply device 201 (see FIG. 11) through the metal wiring (not shown) from the P + region 261. Further, the ground voltage Vss is supplied to the N + region 23-2 from the power supply device 201 (see FIG. 11) via the wiring L13.
  • the first N-type well 11 and the first P-type well 13 form a transistor arrangement region.
  • the second N-type well 12 is formed on the P-type substrate 10 as a region including the cytomatrix (a plurality of site array portions 43).
  • This P-type substrate 10 is electrically connected to the 1st N-type well 11 and the 1st P-type well 13 It is formed so as to be separated.
  • the semiconductor circuit device lb as a modification of the first embodiment is configured without the second P-type well 14 in the semiconductor circuit device la of the first embodiment, and the P + region 261
  • the P + region 261 is configured in substantially the same manner as the semiconductor circuit device la of the first embodiment except that it is applied from the power supply device 201 via the back bias voltage VBBN cathodic wiring (not shown). Yes.
  • Back bias control is performed by the back bias voltage VBBP applied via the PB, and only the P-channel MOS (PMOS) transistor performs the back bias control via the second N-type well 12 and the first N-type well 11. It has come to be.
  • PMOS P-channel MOS
  • this back-bias control is specifically applied by applying a reverse bias to the P-well when the NMOS voltage is just below the transistor is N MOS, and to the N-well plus when the PMOS is PMOS. To do.
  • the semiconductor circuit device lb as a modification of the first embodiment has a double-well structure by the second N-type wel 12 and the first N-type wel 11 (or the first P-type wel 13).
  • the semiconductor circuit device lb as a modification of the first embodiment includes, for example, the first N-type well 11 and the first P-type well after the second N-type well 12 is formed on the P-type substrate 10. 13 is formed, and then the transistor is manufactured by the process of manufacturing the transistor and the process of manufacturing each power supply terminal and wiring.
  • the power supply device 201 in the region where the site array portion 43 (see FIGS. 2 and 3) is absent in the second N-type well 12.
  • the back bias voltage VBBP applied to the second N-type well 12 from the N + region 21 to the P + region 261 from the power supply unit 201 is controlled by the back bias voltage VBBN applied to the second N-type well 12 from the power supply device 201. It is.
  • the power supply wiring In area 42 (power supply wiring area 421, 422), arrange wiring and contacts to supply knock bias voltage VBBP.By reducing the number of wirings that need not be formed, power supply wiring area 42 (power supply wiring area 421, 422 422) can be reduced, and the density of the semiconductor circuit device lb can be increased. In addition, the number of wiring channels can be increased.
  • the power supply wiring area 42 since there is no contact or the like for supplying the back bias voltage V BBP to the power supply wiring area 42 (power supply wiring areas 421, 422), the power supply wiring area 42 has no contact.
  • a logic circuit such as a transistor can be arranged and formed below the metal layer, and this can also increase the density of the semiconductor circuit device la.
  • the space efficiency is improved, and by performing the knock bias control, the leakage current can be reduced and the power consumption can be reduced. it can.
  • the inverter circuits 30a and 30b are formed on the P-type substrate 10 is described.
  • Various circuits may be formed on the P-type substrate 10.
  • a plurality of CMOS circuits may be provided on the P-type substrate 10, and moreover, these plural CMOS circuits may be provided.
  • Back bias control may be performed on only part of the circuit.
  • FIG. 6 is a side sectional view schematically showing the configuration of the semiconductor circuit device lc according to the second embodiment of the present invention.
  • the semiconductor circuit device lc of the second embodiment is configured by, for example, a gate array or a standard cell system and used in an information processing device or the like. .
  • the 2-input NAND circuit 30c and the inverter circuit 30d are formed on the same P-type substrate 10, and the 2-input NAND circuit 30c among them is formed in the 2-input NAND circuit 30c.
  • the back bias control is performed only on the inverter circuit 30d, and the back bias control is not performed on the inverter circuit 30d.
  • the inverter circuit 30d functions as a non-back bias control circuit unit in which knock bias control is not performed.
  • the semiconductor circuit device lc of the second embodiment of the present invention includes a P-type substrate (semiconductor substrate) 10, a first N-type well 11-1, 11-2, and a first P-type as shown in FIG. It consists of wels 13–1, 13-2, second P type wels 14–1, 14–2 and second N type wels 12.
  • P-type substrate 10, 1st N-type wel (second diffusion region) 11—1, 1st P-type wel (first diffusion region) 13—1, 2nd P-type wel (third diffusion region) 14— 1 and 2N type well (fourth diffusion region) 12 form a 2-input NAND circuit 30c
  • P type substrate 10, 1st N type well 11-2, 1st type P well 13-2 and 2nd type P An example in which the inverter circuit 30d is formed by the wel 14-2 is shown below.
  • N-type (second conductivity type) conductivity which is a conductivity type different from P-type substrate 10 on P-type substrate 10 having P-type (first conductivity type) conductivity.
  • a second N-type well (fourth diffusion region) 12 is formed. Further, on the second N-type well 12, the first P-type wel 13-1, the first N-type wel 11-1 and the second P-type wel 14-1 are formed. The 1P type wel 13-1, the first N type wel 11-1 and the second P type wel 14-1 are electrically separated from the P type substrate 10.
  • the first N-type well 11-1 forms a transistor arrangement region, and various elements such as resistors, capacitors, diodes, and transistors are arranged on the surface (the upper surface in the example of FIG. 6). It has N-type conductivity.
  • a P-type transistor (P-type transistor) 3 04 forming a part of a 2-input NAND circuit 30c is formed on the first N-type well 11-1 and a P + region 22— 1, 22-2, 22-3 are formed, and gates 32-1, 32-2 are formed in an insulated state through an oxide film or the like (not shown). Then, in the P + region 22-2, the power supply voltage Vdd is supplied from the power supply 201 (see FIG. 11) via the wiring L121.
  • the first P-well 13-1 forms an arrangement region of transistors, and various elements such as resistors, capacitors, diodes, transistors, etc. are formed on its surface (upper surface in the example of FIG. 6). It has P-type conductivity.
  • an N-type transistor (N-type transistor) 303 force S is formed on the first P-type well 13-1 and forms part of the 2-input NAND circuit 30c. 1, 23-2, 23-3 are formed, and gates 31-1, 31-2 are formed in an insulated state through an oxide film or the like (not shown). Further, the ground voltage Vss is supplied to the N + region 23-3 from the power supply device 201 (see FIG. 11) via the wiring L131.
  • a P-type second P-type well (seventh diffusion region) 14-2 is formed on the P-type substrate 10, and the second P-type well 14 is formed.
  • the 1st P-type wel (fifth diffusion region) 13-2 and the 1st N-type wel (sixth diffusion region) 11-2 are formed, and the 2nd P-type wel 14-2
  • the first P-type well 13-2 and the P-type substrate 10 are electrically connected.
  • the first N-type well 11-2 also forms a transistor arrangement region, and various elements such as resistors, capacitors, diodes, and transistors are arranged on the surface (the upper surface in the example of FIG. 6). Has N-type conductivity.
  • P + regions 22-4, 22-5 and N + region 24 are formed in the first N-type well 11-2 and insulated through an oxide film (not shown).
  • a gate 33 is formed.
  • the power supply voltage Vdd is supplied to the P + region 22-5 and the N + region 24 from the power supply device 201 (see FIG. 11) via the wiring L124.
  • the first P-type well 13-2 also forms a transistor arrangement region, and various elements such as resistors, capacitors, diodes, and transistors are formed on the surface (upper surface in the example of FIG. 6). It has the conductivity of.
  • N + regions 23-4, 23-5 and P + region 25 are formed in the first P-type well 13-2 and insulated through an oxide film or the like (not shown).
  • a gate 34 is formed.
  • the P + region 25 and the N + region 2 3-4 are supplied with the ground voltage Vss from the power supply device 201 (see FIG. 11) via the wiring L132.
  • the inverter circuit 30d does not perform back bias control, and does not apply a back bias voltage to the first P-type well 13-2 and the first N-type well 11-2.
  • the two-input NAND circuit 30c is configured as a site matrix similarly to the semiconductor circuit device la of the first embodiment (see FIGS. 2 and 3).
  • a site array portion 43 is formed on the second N-type well 12 formed on the P-type substrate 10.
  • the semiconductor circuit device lc of the second embodiment is also the same as the semiconductor circuit device la of the first embodiment in the two-input NAND circuit 30c as in the second N-type well 12, the second P-type well 14- It can be said that it has a triple wel structure by 1 and 1N type wel 11-1 (or 1st type P wel 13-1).
  • a contact layer 141 (see FIG. 3) is formed to electrically connect a metal layer (not shown) for supplying a back bias voltage VBBN of the first polarity to the second P-type well 14-1.
  • the first-polarity back bias voltage VBBN supplied from the power supply device 201 (see FIG. 11) is applied to the second P-type well 14-1 via 141 (P + region 26).
  • the region where neither the site array portion 43 nor the second P-type well 14-1 overlaps that is, the site matrix in the second N-type well 12 and the second P-type well 14
  • a metal layer (not shown) for supplying a back bias voltage VBBP having a second polarity different from the first polarity to the second N-type well 12 and a second N-type well 12 are electrically connected.
  • a contact 123 (see FIG. 3) is formed, and the second polarity back bias voltage VBBP supplied from the power supply device 201 (see FIG. 11) is supplied via this contact 123 (N + region 21). It is designed to be applied to 2nd N-type wel 12.
  • the back bias voltage VBBN is supplied to the first P-type well 13-1 from the second P-type well 14-1 and to the first N-type well 11-1.
  • the back bias voltage VBBP is supplied from the second N-type well 12.
  • the size in the second P-type well 14-1 is the same as the semiconductor circuit device la of the first embodiment.
  • the back bias voltage VBB N is applied to the second P-type well 14 1 in the region where the second array type 43 14 is absent, and the second N-type well 12 in the region where the site array unit 43 and the second P-type well 14-1 are absent.
  • Back bias voltage VBBP is applied to 2N type wel 12.
  • the 2-input NA ND circuit 30c formed in the first N-type wel 11-1 and the first P-type wel 13-1 it is applied via the P + region 26 from the power supply device 201 (see FIG. 11).
  • the N-channel MOS (NMOS) transistor is controlled by the back bias voltage VBBN via the second P-type 14 1 and the first P-type 131, and also from the power supply 201 (see FIG. 11).
  • the P-channel MOS (PMOS) transistor is controlled by the back bias voltage VBB P applied through the second N-type well 12 and the first N-type well 11—1, thereby Back bias control is performed.
  • this back bias control is specifically applied by applying a reverse bias to the P-well when the NMOS voltage is just below the transistor is N MOS, and to the N-well when the PMOS is N-MOS. It is done by.
  • the semiconductor circuit device lc of the second embodiment for example, after forming the second N-type well 12 on the P-type substrate 10, forms the second P-type wells 14-1, 14-2, After forming the 1st N-type wels 11-1, 11-2 and 1st P-type wels 13-1, 13-2, perform the transistor's Balta manufacturing process, the manufacturing process of each power supply terminal and wiring, etc. Can be manufactured.
  • the semiconductor circuit device lc as the second embodiment of the present invention it is possible to obtain the same effect as that of the first embodiment.
  • the area where power consumption is reduced by controlling the voltage to reduce the leakage current in this second embodiment, the 2-input NAND circuit 30c part
  • the back bias voltage sometimes referred to as the well voltage
  • a region (inverter circuit 30d portion in the second embodiment; non-back bias control circuit portion) can be formed without control, and one P-type substrate 10 can be formed in accordance with, for example, circuit characteristics. Can be used properly.
  • two types of transistors with and without knock bias control can be placed on the same chip. It can be created and is very convenient.
  • the clock width and the sensitivity of the sense amplifier are controlled. It is desirable to form a circuit without the need for knock bias control because of the influence on the
  • the back bias voltage VBBN is applied via the second P-type 14-1 in the 2-input NAND circuit 30c, and the second N-type 12 is applied.
  • the back bias voltage VBBP is applied to control the back bias for the! / And the deviation between the NMOS transistor and the PMOS transistor.
  • the back bias control may be performed only on one of the NMOS transistor and the PMOS transistor formed in the above.
  • FIG. 7 is a side sectional view schematically showing a configuration of a modified example of the semiconductor circuit device according to the first embodiment of the present invention.
  • the semiconductor circuit device Id as a modification of the second embodiment is also configured by, for example, a gate array, a standard cell system, etc. It is what is done.
  • a two-input NAND circuit 30e and an inverter circuit 30d are formed on the same P-type substrate 10, and this two-input NAND circuit An example in which back bias control is performed only for the PMOS transistor at 30e will be described.
  • the inverter circuit 30d functions as a non-back bias control circuit unit that does not perform back bias control.
  • a semiconductor circuit device Id as a modification of the second embodiment of the present invention includes a P-type substrate 10, first N-type wells 11-1, 11-2, first P-type well 13 — 1, 13-2, 2nd P-type wel 14-2 and 2nd N-type wel 12.
  • a two-input NAND circuit 30e is formed by the P-type wel (first diffusion region) 13-1 and the second N-type wel (fourth diffusion region) 12 and supplied from the power supply 201 (see FIG. 11).
  • a back bias voltage VBBN of the first polarity is applied to the P + region (power supply terminal) 262, and a back bias voltage of the second polarity different from the first polarity supplied from the power supply device 201 (see FIG. 11).
  • VBBP is applied through an N + region (power supply terminal) 21 formed in the second N-type well 12.
  • the inverter circuit 30d is formed by the P-type substrate 10, the first N-type well 11-2, the first P-type well 13-2, and the second P-type well 14-2.
  • the N-type (second conductivity type) conductivity is provided on the P-type substrate 10 having the P-type conductivity in the two-input NAND circuit 30e.
  • a second N-type well 12 is formed.
  • the first P-type well 13-1 and the first N-type well 11-1 are formed, and the second N-type well 1 2 force. These first P-type well 13-1 and the first N The mold well 11-1 and the P-type substrate 10 are electrically separated.
  • the first P-type well 13-1 forms an arrangement region of the transistor, and various elements such as a resistor, a capacitor, a diode, and a transistor are formed on the surface (upper surface in the example of FIG. 7).
  • P-type conductivity In the example shown in FIG. 7, the N + region 23-1, 1, 23-2, 23-3 and the P + region 262 are formed in the first P-type well 13-1, and the power supply device 201 is included in the P + region 262.
  • the back bias voltage VBBN of the first polarity is printed.
  • gates 31-1 and 31-2 are formed on the first P-type well 13-1 in an insulated state through an oxide film or the like (not shown). Further, the ground voltage Vss is supplied to the N + region 23-3 from the power supply device 201 (see FIG. 11) via the wiring L131.
  • the second N-type well 12 has a site matrix (a plurality of site array units 43) formed on the P-type substrate 10 in the same manner as the two-input NA ND circuit 30c in the semiconductor circuit device lc of the second embodiment.
  • the P-type substrate 1 is formed on the P-type substrate 10. It is formed so that 0 is electrically separated from the IN type wel 11-1 and the IP type wel 13-1.
  • the 2-input NAND circuit 30e is not provided with the second P-type well 14-1 in the semiconductor circuit device lc of the second embodiment.
  • the P + region 262 is provided, and the back bias voltage VBBN is applied to the P + region 262.
  • the semiconductor circuit device 1c of the second embodiment is substantially the same.
  • a double well formed by the second N-type well 12 and the first N-type well 11-1 (or the first P-type well 13-1) is used. If you have a structure,
  • a semiconductor circuit device Id as a modification of the second embodiment includes, for example, forming a second N-type well 12-2 on a P-type substrate 10 and then forming a second P-type well 14-2.
  • First N-type wels 11-1, 11-2 and 1P-type wels 13-1, 1, 13-2 are formed, and then manufactured by performing the transistor's Balta manufacturing process and the power supply terminal and wiring manufacturing processes. Can do.
  • the site array section 43 in the second N-type well 12 (Fig. 2, Fig. 2). 3) Back bias voltage VBBP applied to second N-type well 12 from power supply 201 through Balta contact N + region 21 in the absence region, and back bias voltage VBBN applied to P + region 262 from power supply 201
  • the back bias control of the 2-input NAND circuit 30e is performed.
  • this back bias control is specifically applied by applying a reverse bias voltage to the p-well if the NMOS voltage just below the transistor is N MOS, to P-minus if it is PMOS, or to N-plus if it is PMOS. Is done.
  • the semiconductor circuit device Id as a modified example of the second embodiment of the present invention can obtain the same operation and effect as the semiconductor circuit device lc of the second embodiment, and the power wiring region 42 ( In the power supply wiring area (421, 422), it is not necessary to arrange and form wiring and contacts to supply the back bias voltage VBBP, and to reduce the number of wiring As a result, the area occupied by the power supply wiring region 42 (power supply wiring regions 421 and 422) can be reduced, and the density of the semiconductor circuit device la can be increased. In addition, the number of wiring channels can be increased.
  • the power supply wiring area 42 Since there is no contact or the like for supplying the back bias voltage V BBP to the power supply wiring area 42 (power supply wiring areas 421, 422), the power supply wiring area 42 has no contact.
  • a logic circuit such as a transistor can be arranged and formed below the metal layer, and this can also increase the density of the semiconductor circuit device Id.
  • FIG. 11 is a diagram schematically showing a configuration of a semiconductor circuit device system as an embodiment of the present invention.
  • the semiconductor circuit device system 100 includes a power supply device 201 and a semiconductor circuit device la, and the power supply device 201 has a back bias voltage VBBN, VBBP, power supply voltage Vdd, and ground voltage Vss are supplied.
  • the semiconductor circuit device to which the power supply device 201 supplies the voltage is not limited to the semiconductor circuit device la shown in FIG. 11, and the semiconductor circuit device shown as each of the above-described embodiments and modifications thereof. Even if it is lb, lc, or Id, various modifications can be made without departing from the spirit of the present invention. In addition, the present invention is not limited to the above-described embodiments and modifications thereof, and various modifications can be made without departing from the spirit of the present invention.
  • the force described in the example in which the inverter circuit or the 2-input NAND circuit is formed on the P-type substrate 10 is not limited to this.
  • Various circuits other than these inverter circuits and 2-input NAND circuits may be formed.
  • the bias control voltage is applied to the second P-type well 14 (14-1) and the second N-type well 12 as contacts 141 (P + region 26),
  • force applied through contact 123 (N + region 21) is not limited to this.
  • it can be applied directly from the second P-type well 14 or the second N-type well 12 to the metal first layer, etc.
  • You can apply the back bias voltage by using various known methods that can be passed through the 1st P-type wel 13 or the 1st N-type wel 11! /.
  • the knock bias setting of the well may be performed by directly supplying the external terminal force. Further, as the knock bias setting circuit inside the chip, the power supply voltage force supplied from the external terminal is boosted. Alternatively, it may be supplied after being stepped down.
  • the well voltage directly under the transistor is NMOS
  • the P-type well is negative
  • PMO S is the N-type well
  • the force described for the example in which the inverter circuit 30d is provided as the non-back bias control circuit unit in which the back bias control is not performed is not performed.
  • Various circuits other than the inverter circuit that is not limited may be used as the non-back bias control circuit section.
  • the P-type substrate 10 which is a semiconductor substrate having a P-type conductivity is used.
  • the present invention is not limited to this.
  • An N-type substrate having a mold may be used.
  • the second P-type well 14 is replaced with an N-type well (second N-type well).
  • second N-type well an N-type well
  • second P-type well instead of the second n-type well 12.
  • it can manufacture easily by reversing the formation order of the well produced
  • the PMOS transistor in the inverter circuit 30b is well (second N-type well 12).
  • the force shown in the example of applying the back bias voltage through the gate is not limited to this.
  • the back bias voltage may be applied through the well only to the NMOS transistor.
  • the back bias voltage is applied only to the PMOS transistor in the two-input NAND circuit 30e via the well (the first N-type well 11-1).
  • the present invention is not limited to this.
  • the back bias voltage may be applied to the NMOS transistor only through the well.
  • the present invention can be applied to back bias control of various circuits in a semiconductor circuit device.

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Abstract

Dispositif de circuit à semi-conducteurs constitué d'un premier substrat à semi-conducteurs (10) d'un premier type de conduction, d'un premier domaine de diffusion (13) du premier type de conduction ayant un transistor du deuxième type de conduction (301) formé dans celui-ci, un deuxième domaine de diffusion (11) d'un deuxième type de conduction ayant un transistor du premier type de conduction (302) formé dans celui-ci, un troisième domaine de diffusion (14) du premier type de conduction, auquel une tension de polarisation inverse d'une première polarité est appliquée, et un quatrième domaine de diffusion (12) du deuxième type de conduction, auquel une tension de polarisation inverse d'une deuxième polarité est appliquée. Cette constitution peut diminuer la quantité de câblage pour ainsi réduire la zone de câblage de prise d'alimentation.
PCT/JP2006/314900 2006-07-27 2006-07-27 Dispositif de circuit à semi-conducteurs, système de dispositif de circuit à semi-conducteurs et procédé de fabrication pour le dispositif de circuit à semi-conducteurs WO2008012899A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/314900 WO2008012899A1 (fr) 2006-07-27 2006-07-27 Dispositif de circuit à semi-conducteurs, système de dispositif de circuit à semi-conducteurs et procédé de fabrication pour le dispositif de circuit à semi-conducteurs

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/314900 WO2008012899A1 (fr) 2006-07-27 2006-07-27 Dispositif de circuit à semi-conducteurs, système de dispositif de circuit à semi-conducteurs et procédé de fabrication pour le dispositif de circuit à semi-conducteurs

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102666222A (zh) * 2009-12-21 2012-09-12 雷诺股份公司 用于安装或移除机动车辆电池的方法和系统
JP2014146220A (ja) * 2013-01-30 2014-08-14 Fujitsu Semiconductor Ltd 半導体装置の設計方法、プログラム及び設計装置
JPWO2020230465A1 (ja) * 2019-05-16 2021-10-28 富士電機株式会社 半導体集積回路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05108194A (ja) * 1991-10-17 1993-04-30 Hitachi Ltd 低消費電力型半導体集積回路
JPH0689574A (ja) * 1992-03-30 1994-03-29 Mitsubishi Electric Corp 半導体装置
JP2002158293A (ja) * 2000-11-16 2002-05-31 Sharp Corp 半導体装置及び携帯電子機器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05108194A (ja) * 1991-10-17 1993-04-30 Hitachi Ltd 低消費電力型半導体集積回路
JPH0689574A (ja) * 1992-03-30 1994-03-29 Mitsubishi Electric Corp 半導体装置
JP2002158293A (ja) * 2000-11-16 2002-05-31 Sharp Corp 半導体装置及び携帯電子機器

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102666222A (zh) * 2009-12-21 2012-09-12 雷诺股份公司 用于安装或移除机动车辆电池的方法和系统
JP2014146220A (ja) * 2013-01-30 2014-08-14 Fujitsu Semiconductor Ltd 半導体装置の設計方法、プログラム及び設計装置
JPWO2020230465A1 (ja) * 2019-05-16 2021-10-28 富士電機株式会社 半導体集積回路
JP7115637B2 (ja) 2019-05-16 2022-08-09 富士電機株式会社 半導体集積回路

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