JP4787554B2 - 入出力回路装置 - Google Patents
入出力回路装置 Download PDFInfo
- Publication number
- JP4787554B2 JP4787554B2 JP2005193265A JP2005193265A JP4787554B2 JP 4787554 B2 JP4787554 B2 JP 4787554B2 JP 2005193265 A JP2005193265 A JP 2005193265A JP 2005193265 A JP2005193265 A JP 2005193265A JP 4787554 B2 JP4787554 B2 JP 4787554B2
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- Prior art keywords
- input
- transistor
- source
- output circuit
- circuit device
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- Expired - Fee Related
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- 239000000758 substrate Substances 0.000 claims description 40
- 238000009792 diffusion process Methods 0.000 description 31
- 239000012535 impurity Substances 0.000 description 18
- 239000004065 semiconductor Substances 0.000 description 11
- 238000002955 isolation Methods 0.000 description 6
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Description
本発明の第1の実施形態について図面を参照しながら説明する。
図2は本発明の第1の実施形態に係る入出力回路装置10の第1構成例の断面構成を示している。図2に示すように、第1構成例に係る入出力回路装置10は、プルダウントランジスタQ1及びカスケードトランジスタQ2が、例えばシリコン(Si)からなる半導体基板101の上部に選択的に形成された素子分離膜102により区画された第1のp型ウェル103及び第2のp型ウェル113にそれぞれ形成されている。
図3は本発明の第1の実施形態に係る入出力回路装置10の第2構成例の断面構成を示している。図3に示すように、第2構成例に係る入出力回路装置10は、プルダウントランジスタQ1及びカスケードトランジスタQ2が、いわゆるSOI(Silicon On Insulator)基板201の上部に選択的に形成された素子分離膜202により区画された第1のp型ウェル203及び第2のp型ウェル213にそれぞれ形成されている。SOI基板201には、その主面から所定の深さで埋め込まれた絶縁層201aが形成されている。
以下、本発明の第2の実施形態について図面を参照しながら説明する。
図5は本発明の第2の実施形態に係る入出力回路装置20の第1構成例の断面構成を示している。図5において、図2に示した構成部材と同一の構成部材には同一の符号を付すことにより説明を省略する。図5に示すように、第1構成例に係る入出力回路装置20は、カスケードトランジスタQ2における第2のp型ウェル113の外側の端部に高濃度のp型不純物拡散層118が形成されており、該p型不純物拡散層118が内部ノードVcと接続されて、本発明の第2の実施形態に係る入出力回路装置20が実現される。
図6は本発明の第2の実施形態に係る入出力回路装置20の第2構成例の断面構成を示している。図6において、図3に示した構成部材と同一の構成部材には同一の符号を付すことにより説明を省略する。図6に示すように、第2構成例に係る入出力回路装置20は、カスケードトランジスタQ2における第2のp型ウェル213の外側の端部に高濃度のp型不純物拡散層218が形成されており、該p型不純物拡散層218がいわゆるボディコンタクト構造によって内部ノードVcと接続されて、本発明の第2の実施形態に係る入出力回路装置20が実現される。
Q2 カスケードトランジスタ(第2のトランジスタ)
Vn 信号端子
Vc 内部ノード
V0 入出力端子
10 入出力回路装置
20 入出力回路装置
101 半導体基板
102 素子分離膜
103 第1のp型ウェル
104 ゲート絶縁膜
105 ゲート電極
106 ソース拡散層
107 ドレイン拡散層
108 p型不純物拡散層
113 第2のp型ウェル
114 ゲート絶縁膜
115 ゲート電極
116 ソースドレイン拡散層
118 p型不純物拡散層
119 n型ウェル
201 SOI基板
201a 絶縁層
202 素子分離膜
203 第1のp型ウェル
204 ゲート絶縁膜
205 ゲート電極
206 ソース拡散層
207 ドレイン拡散層
208 p型不純物拡散層
213 第2のp型ウェル
214 ゲート絶縁膜
215 ゲート電極
216 ソースドレイン拡散層
218 p型不純物拡散層
Claims (5)
- 基板に形成されており、第1のゲートが入力信号を受け、第1のソースドレインの一方が第1の電源端子と接続され、前記第1のソースドレインの他方が内部ノードと接続された第1のトランジスタと、
前記基板に形成されており、第2のゲートが第2の電源端子と接続され、第2のソースドレインの一方が入出力ノードと接続され、前記第2のソースドレインの他方が前記内部ノードと接続された第2のトランジスタとを備え、
前記第2のトランジスタの基板電位は、電気的にフローティング状態にされていることを特徴とする入出力回路装置。 - 前記第1のトランジスタの基板電位は、前記第1の電源端子と接続されていることを特徴とする請求項1に記載の入出力回路装置。
- 前記基板には、前記第2のソースドレインが形成された第1導電型ウェルと、該第1導電型ウェルの周囲及びその下方を覆う第2導電型ウェルとが形成されていることを特徴とする請求項1又は2に記載の入出力回路装置。
- 前記基板には、前記第2のソースドレインが形成された第1導電型ウェルと、該第1導電型ウェルの周囲及びその下方を覆う絶縁膜とが形成されていることを特徴とする請求項1又は2に記載の入出力回路装置。
- 前記第1のソースドレイン及び第2のソースドレインの導電型はn型であり、
前記第1の電源端子には接地電圧が印加され、前記第2の電源端子には電源電圧が印加されることを特徴とする請求項1〜4のいずれか1項に記載の入出力回路装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005193265A JP4787554B2 (ja) | 2005-07-01 | 2005-07-01 | 入出力回路装置 |
CNA2006100743870A CN1893275A (zh) | 2005-07-01 | 2006-04-14 | 输出入电路装置 |
US11/436,641 US7388401B2 (en) | 2005-07-01 | 2006-05-19 | Input/output circuit device |
KR1020060053033A KR20070003562A (ko) | 2005-07-01 | 2006-06-13 | 입출력회로장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005193265A JP4787554B2 (ja) | 2005-07-01 | 2005-07-01 | 入出力回路装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2007013748A JP2007013748A (ja) | 2007-01-18 |
JP2007013748A5 JP2007013748A5 (ja) | 2008-02-21 |
JP4787554B2 true JP4787554B2 (ja) | 2011-10-05 |
Family
ID=37597846
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005193265A Expired - Fee Related JP4787554B2 (ja) | 2005-07-01 | 2005-07-01 | 入出力回路装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7388401B2 (ja) |
JP (1) | JP4787554B2 (ja) |
KR (1) | KR20070003562A (ja) |
CN (1) | CN1893275A (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9287253B2 (en) * | 2011-11-04 | 2016-03-15 | Synopsys, Inc. | Method and apparatus for floating or applying voltage to a well of an integrated circuit |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0738583B2 (ja) * | 1985-01-26 | 1995-04-26 | 株式会社東芝 | 半導体集積回路 |
KR900019026A (ko) * | 1989-05-11 | 1990-12-22 | 김광호 | 반도체 장치의 기준전압 발생회로 |
JPH04329024A (ja) * | 1991-04-30 | 1992-11-17 | Toshiba Corp | 入出力バッファ回路 |
GB2258100B (en) | 1991-06-28 | 1995-02-15 | Digital Equipment Corp | Floating-well CMOS output driver |
US5191244A (en) * | 1991-09-16 | 1993-03-02 | Advanced Micro Devices, Inc. | N-channel pull-up transistor with reduced body effect |
JPH0786910A (ja) * | 1993-09-10 | 1995-03-31 | Oki Electric Ind Co Ltd | 出力駆動回路 |
JP3210567B2 (ja) * | 1996-03-08 | 2001-09-17 | 株式会社東芝 | 半導体出力回路 |
FR2760151B1 (fr) * | 1997-02-25 | 1999-05-14 | Sgs Thomson Microelectronics | Amplificateur-tampon de commande de bus |
JP3544819B2 (ja) * | 1997-03-31 | 2004-07-21 | 株式会社 沖マイクロデザイン | 入力回路および出力回路ならびに入出力回路 |
JP3954198B2 (ja) * | 1998-06-01 | 2007-08-08 | 富士通株式会社 | 出力回路、レベルコンバータ回路、論理回路、及び、オペアンプ回路 |
JP3514645B2 (ja) * | 1998-12-28 | 2004-03-31 | 株式会社 沖マイクロデザイン | 半導体集積回路装置の入出力回路 |
JP4145410B2 (ja) * | 1999-03-26 | 2008-09-03 | 株式会社ルネサステクノロジ | 出力バッファ回路 |
JP2000312004A (ja) * | 1999-04-27 | 2000-11-07 | Seiko Epson Corp | 低消費電力論理機能回路 |
US6184700B1 (en) * | 1999-05-25 | 2001-02-06 | Lucent Technologies, Inc. | Fail safe buffer capable of operating with a mixed voltage core |
-
2005
- 2005-07-01 JP JP2005193265A patent/JP4787554B2/ja not_active Expired - Fee Related
-
2006
- 2006-04-14 CN CNA2006100743870A patent/CN1893275A/zh active Pending
- 2006-05-19 US US11/436,641 patent/US7388401B2/en active Active
- 2006-06-13 KR KR1020060053033A patent/KR20070003562A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
US20070008007A1 (en) | 2007-01-11 |
CN1893275A (zh) | 2007-01-10 |
JP2007013748A (ja) | 2007-01-18 |
KR20070003562A (ko) | 2007-01-05 |
US7388401B2 (en) | 2008-06-17 |
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