JP2007095965A - 半導体装置およびバイパスキャパシタモジュール - Google Patents
半導体装置およびバイパスキャパシタモジュール Download PDFInfo
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】CMOSトランジスタやダイオード等の半導体素子が形成されたSi基板10の一方の面側に、半導体素子に電源を供給するためのVcc電源層30およびGND層50と、当該Vcc電源層30およびグランド層50間に狭持された高誘電率層40とで構成されるバイパスキャパシタを形成する。
【選択図】 図1−1
Description
10a〜d コンタクトホール
11a〜d 配線
20 絶縁層(配線層)
21 配線
30 Vcc電源層
40 高誘電率層
50 GND層
100、200 バイパスキャパシタシート
PTr PチャネルMOSトランジスタ
NTr NチャネルMOSトランジスタ
Di ダイオード
W1、W2 N型ウェル
S1、S2 ソース領域
D1、D2 ドレイン領域
AE アノード電極
CE カソード電極
SE1、SE2 ソース電極
GE1、GE2 ゲート電極
DE1、DE2 ドレイン電極
Claims (13)
- 半導体素子が形成された基板の一方の面側に、前記半導体素子に電源を供給するための電源層およびグランド層と、当該電源層およびグランド層間に狭持された高誘電率層とで構成されるバイパスキャパシタを形成したことを特徴とする半導体装置。
- 前記バイパスキャパシタは、前記基板の半導体素子の形成面側に形成されることを特徴とする請求項1に記載の半導体装置。
- 前記バイパスキャパシタは、前記基板の半導体素子の形成面に対して反対面側に形成されることを特徴とする請求項1または請求項2に記載の半導体装置。
- 前記電源層は回路ブロック毎に分離して形成されることを特徴とする請求項1〜請求項3のいずれか1つに記載の半導体装置。
- 前記半導体素子は、PチャネルMOSトランジスタであり、そのソース電極が前記電源層に接続されており、そのドレイン電極が前記グランド層に接続されることを特徴とする請求項1〜請求項4のいずれか1つに記載の半導体装置。
- 前記半導体素子は、NチャネルMOSトランジスタであり、そのドレイン電極が前記電源層に接続されており、そのソース電極が前記グランド層に接続されることを特徴とする請求項1〜請求項4のいずれか1つに記載の半導体装置。
- 前記半導体素子は、CMOSトランジスタであり、そのPチャネルMOSトランジスタのソース電極が前記電源層に接続されており、そのNチャネルMOSトランジスタのソース電極が前記グランド層に接続されることを特徴とする請求項1〜請求項4のいずれか1つに記載の半導体装置。
- 前記半導体素子は、ダイオードであり、そのアノード電極またはカソード電極が前記電源層に接続され、そのカソード電極またはアノード電極が前記グランド層に接続されることを特徴とする請求項1〜請求項4のいずれか1つに記載の半導体装置。
- 前記バイバスキャパシタはモジュール構成されていることを特徴とする請求項1〜請求項8のいずれか1つに記載の半導体装置。
- 前記バイパスキャパシタの前記電源層およびグランド層と前記基板とは、ボンディングワイヤまたは半田ボールで接続されることを特徴とする請求項9に記載の半導体装置。
- 基板に形成された半導体素子に電源を供給するための電源層およびグランド層と、
前記電源層およびグランド層間に狭持された高誘電率層と、
を備えたことを特徴とするバイパスキャパシタモジュール。 - 前記バイバスキャパシタモジュールは、シート構造を呈することを特徴とする請求項11に記載のバイパスキャパシタモジュール。
- 前記電源層およびグランド層は、前記基板にボンディングワイヤまたは半田ボールで接続されることを特徴とする請求項11または請求項12に記載のバイパスキャパシタモジュール。
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JP2005282899A JP5124839B2 (ja) | 2005-09-28 | 2005-09-28 | 半導体装置 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110260289A1 (en) * | 2008-03-17 | 2011-10-27 | Seisei Oyamada | Semiconductor device and bypass capacitor module |
JP2013033917A (ja) * | 2011-07-05 | 2013-02-14 | Denso Corp | 半導体装置 |
JP2013131758A (ja) * | 2011-12-21 | 2013-07-04 | Power Integrations Inc | 半導体装置 |
JP2021090035A (ja) * | 2019-12-06 | 2021-06-10 | アオイ電子株式会社 | 半導体装置の製造方法、半導体装置および半導体装置の中間体 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3107703B1 (fr) | 2020-02-28 | 2023-06-23 | Saint Gobain | Vitrage de controle solaire comprenant une couche de nitrure de titane |
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JPH02260559A (ja) * | 1989-03-31 | 1990-10-23 | Seiko Epson Corp | 半導体集積回路装置 |
JPH0322470A (ja) * | 1989-06-19 | 1991-01-30 | Nec Ic Microcomput Syst Ltd | 半導体集積回路 |
JPH0555380A (ja) * | 1991-08-22 | 1993-03-05 | Toshiba Corp | 半導体集積回路装置 |
JPH05299584A (ja) * | 1992-02-21 | 1993-11-12 | Toshiba Corp | 薄膜容量素子及び半導体記憶装置 |
JPH10189873A (ja) * | 1996-12-20 | 1998-07-21 | Internatl Business Mach Corp <Ibm> | 半導体集積回路 |
JPH11154733A (ja) * | 1997-11-20 | 1999-06-08 | Seiko Epson Corp | 半導体集積装置 |
JP2001060664A (ja) * | 1999-08-23 | 2001-03-06 | Mitsubishi Electric Corp | 半導体装置 |
JP2002033453A (ja) * | 2000-07-14 | 2002-01-31 | Nec Corp | 半導体装置およびその製造方法ならびに薄膜コンデンサ |
JP2002270767A (ja) * | 2001-03-06 | 2002-09-20 | Canon Inc | 半導体集積回路 |
-
2005
- 2005-09-28 JP JP2005282899A patent/JP5124839B2/ja not_active Expired - Fee Related
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02260559A (ja) * | 1989-03-31 | 1990-10-23 | Seiko Epson Corp | 半導体集積回路装置 |
JPH0322470A (ja) * | 1989-06-19 | 1991-01-30 | Nec Ic Microcomput Syst Ltd | 半導体集積回路 |
JPH0555380A (ja) * | 1991-08-22 | 1993-03-05 | Toshiba Corp | 半導体集積回路装置 |
JPH05299584A (ja) * | 1992-02-21 | 1993-11-12 | Toshiba Corp | 薄膜容量素子及び半導体記憶装置 |
JPH10189873A (ja) * | 1996-12-20 | 1998-07-21 | Internatl Business Mach Corp <Ibm> | 半導体集積回路 |
JPH11154733A (ja) * | 1997-11-20 | 1999-06-08 | Seiko Epson Corp | 半導体集積装置 |
JP2001060664A (ja) * | 1999-08-23 | 2001-03-06 | Mitsubishi Electric Corp | 半導体装置 |
JP2002033453A (ja) * | 2000-07-14 | 2002-01-31 | Nec Corp | 半導体装置およびその製造方法ならびに薄膜コンデンサ |
JP2002270767A (ja) * | 2001-03-06 | 2002-09-20 | Canon Inc | 半導体集積回路 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110260289A1 (en) * | 2008-03-17 | 2011-10-27 | Seisei Oyamada | Semiconductor device and bypass capacitor module |
US8299518B2 (en) * | 2008-03-17 | 2012-10-30 | Liquid Design Systems Inc. | Semiconductor device and bypass capacitor module |
JP2013033917A (ja) * | 2011-07-05 | 2013-02-14 | Denso Corp | 半導体装置 |
JP2013131758A (ja) * | 2011-12-21 | 2013-07-04 | Power Integrations Inc | 半導体装置 |
US10002957B2 (en) | 2011-12-21 | 2018-06-19 | Power Integrations, Inc. | Shield wrap for a heterostructure field effect transistor |
US10199488B2 (en) | 2011-12-21 | 2019-02-05 | Power Integrations, Inc. | Shield wrap for a heterostructure field effect transistor |
JP2021090035A (ja) * | 2019-12-06 | 2021-06-10 | アオイ電子株式会社 | 半導体装置の製造方法、半導体装置および半導体装置の中間体 |
JP7410700B2 (ja) | 2019-12-06 | 2024-01-10 | アオイ電子株式会社 | 半導体装置の製造方法、半導体装置および半導体装置の中間体 |
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