JP5339484B2 - 半導体装置およびバイパスキャパシタモジュール - Google Patents
半導体装置およびバイパスキャパシタモジュール Download PDFInfo
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- JP5339484B2 JP5339484B2 JP2011262274A JP2011262274A JP5339484B2 JP 5339484 B2 JP5339484 B2 JP 5339484B2 JP 2011262274 A JP2011262274 A JP 2011262274A JP 2011262274 A JP2011262274 A JP 2011262274A JP 5339484 B2 JP5339484 B2 JP 5339484B2
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- Japan
- Prior art keywords
- layer
- bypass capacitor
- power supply
- substrate
- dielectric constant
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
本発明の態様によれば、基板に形成された半導体素子に接続して使用されるバイパスキャパシタモジュールであって、電源層と、グランド層と、前記電源層およびグランド層間に狭持された高誘電率層、前記電源層の一表面上に設けられたパッド又は半田ボールと、前記グランド層にパッドにより電気的に接続されると共に前記電源層に対して電気的に絶縁され、前記電源層及び前記高誘電率層を通して、前記電源層の前記一表面上に取り出されたボンディングワイヤ又は半田ボールを有していることを特徴とするバイパスキャパシタモジュールが得られる。
10a〜d コンタクトホール
11a〜d 配線
20 絶縁層(配線層)
21 配線
30 Vcc電源層
40 高誘電率層
50 GND層
100、200 バイパスキャパシタシート
PTr PチャネルMOSトランジスタ
NTr NチャネルMOSトランジスタ
Di ダイオード
W1、W2 N型ウェル
S1、S2 ソース領域
D1、D2 ドレイン領域
AE アノード電極
CE カソード電極
SE1、SE2 ソース電極
GE1、GE2 ゲート電極
DE1、DE2 ドレイン電極
Claims (4)
- 基板に形成された半導体素子に接続して使用されるバイパスキャパシタモジュールであって、前記バイパスキャパシタモジュールは、
電源層と、
グランド層と、
前記電源層およびグランド層間に狭持された高誘電率層からなるバイパスキャパシタシートによって構成され、
前記グランド層は、前記高誘電率層及び前記電源層を介して延び、前記グランド層に電気的に接続されたパッドを通して前記電源層から突出したハンダボールに接続され、
前記電源層は、当該電源層表面から突出するように設けられた半田ボールに電気的に接続され、
前記バイパスキャパシタシートが前記基板に取り付けられた場合、前記グランド層は前記電源層及び前記高誘電率層を覆うように設けられていると共に前記基板全面を覆うように設けられ、且つ、前記グランド層が最上部に位置付けられていることを特徴とするバイパスキャパシタモジュール。 - 請求項1において、前記電源層、前記グランド層、及び前記高誘電率層は、前記基板と同一面積を有していることを特徴とするバイパスキャパシタモジュール。
- 請求項2に記載されたバイバスキャパシタモジュールを搭載した前記基板を有することを特徴とする半導体装置。
- 請求項1又は2において、前記高誘電率層は10以上の比誘電率を有する誘電体材料によって形成されていることを特徴とするバイパスキャパシタモジュール。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2011262274A JP5339484B2 (ja) | 2011-11-30 | 2011-11-30 | 半導体装置およびバイパスキャパシタモジュール |
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JP2011262274A JP5339484B2 (ja) | 2011-11-30 | 2011-11-30 | 半導体装置およびバイパスキャパシタモジュール |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005282899A Division JP5124839B2 (ja) | 2005-09-28 | 2005-09-28 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2012064969A JP2012064969A (ja) | 2012-03-29 |
JP5339484B2 true JP5339484B2 (ja) | 2013-11-13 |
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JP2011262274A Expired - Fee Related JP5339484B2 (ja) | 2011-11-30 | 2011-11-30 | 半導体装置およびバイパスキャパシタモジュール |
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Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0547586A (ja) * | 1991-08-16 | 1993-02-26 | Toshiba Corp | コンデンサ部品 |
JPH07183470A (ja) * | 1993-10-19 | 1995-07-21 | Kyocera Corp | 半導体装置 |
US5528083A (en) * | 1994-10-04 | 1996-06-18 | Sun Microsystems, Inc. | Thin film chip capacitor for electrical noise reduction in integrated circuits |
JP3918675B2 (ja) * | 2002-08-01 | 2007-05-23 | 日本電気株式会社 | 薄膜キャパシタ、それを内蔵した配線基板、それを搭載した半導体集積回路および電子機器システム |
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2011
- 2011-11-30 JP JP2011262274A patent/JP5339484B2/ja not_active Expired - Fee Related
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JP2012064969A (ja) | 2012-03-29 |
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