JPH05108194A - Low power consumption type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable high speed operation with low power supply voltage under a operation mode and to reduce voltage consumption under a waiting mode by setting the threshold of a MOS transistor to a low value and increasing the threshold at the time of the waiting mode by applying a circuit board bias. CONSTITUTION:The threshold of the MOB transistor (MN,MP) is set to a low value and under the waiting mode, a clock CKm to be supplied to an MPU (microprocessor unit) 1 is stopped by a clock control circuit 3, circuit board bias circuits 2-1, 2-2 are actuated with an operation mode switching signal A and a negative circuit board bias VBN is applied to an NMOS transistor (MN) and a positive circuit board bias VBP than the power supply is applied to a PMOS transistor (MP). At this time, the threshold of the MOS transistor increases and leak current decreases by means of exponential function by the amount of the increase of the threshold. That is, by applying the circuit board bias, subthreshold characteristics can be improved and the leak current can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low power consumption type semiconductor integrated circuit, and more particularly to an information processing device such as a microprocessor which operates on a battery and uses a MOS transistor.

[0002]

2. Description of the Related Art Conventionally, as an example of a semiconductor circuit to which a substrate bias is applied, "Ultra High Speed MOS Device", pp. 259 to 26, published by Baifukan on February 10, 1987.
Some are mentioned on page 1 (supervised by Takuo Sugano).

The conventional application of a general substrate bias is aimed at speeding up by reducing the pn junction capacitance as in this conventional example. On the other hand, when a substrate bias is applied, the threshold value of the n-channel MOSFET rises and is designed to be a practical value of about 0.6 to 1.0V. According to this example, the higher the value of the substrate bias, the wider the depletion layer of the drain and the smaller the capacitance of the pn junction, so that the speed can be increased.

On the other hand, as an example of measures for reducing the power consumption of a processor using a CMOS type circuit, Japanese Patent Laid-Open No.
As described in Japanese Laid-Open Patent No. 42827, there is a device which attempts to reduce power consumption by stopping a clock supply to a CPU portion and a circuit which does not operate by a program instruction to enter a standby mode. In a CMOS type circuit, if the clock is stopped and all switching is stopped, the power consumption is MOS
Since only the leak current due to the subthreshold current of the transistor is used, the current consumption in the standby mode can be reduced by three digits or more as compared with the operating time.

[0005]

The present threshold value (0.5
A microprocessor using a MOS transistor of about V) can be operated at a high speed by using a power supply voltage of 5 V, and the speed can be increased by reducing the pn junction capacitance by applying a substrate bias as in the conventional case. there were.
However, from the viewpoint of low power consumption, since the power consumption is proportional to the square of the power supply voltage, it is necessary to reduce the power supply voltage to 5V or less. Particularly in the case of battery operation, it is necessary to reduce the voltage to about 1V. Further, as the miniaturization of the MOS transistor progresses, the withstand voltage of the element also decreases, so that it is necessary to lower the power supply voltage.

On the other hand, the delay time of the CMOS circuit is the time for charging / discharging the charge of the load capacitance with the drain current, and is proportional to the power supply voltage / (power supply voltage-threshold value) squared. Therefore, the delay time is inversely proportional to the power supply voltage at a high power supply voltage where the threshold value can be ignored, but at a low voltage where the threshold value cannot be ignored, the delay time rapidly increases with a decrease in the power supply voltage. When a substrate bias is applied during the operation at such a low voltage, the threshold value rises, so that there is a problem that the operation speed is rather lowered. Therefore, when operating at a low voltage, basically no substrate bias is applied and the threshold value of the MOS transistor must be kept low.

On the other hand, lowering the threshold voltage is
Another problem occurs that the leakage current increases due to the subthreshold current of the MOS transistor. This leak current increases exponentially with about 47 times each time the threshold value is lowered by 0.1 V at room temperature. For example, if the threshold value is lowered from 0.5V to 0.3V, the leak current becomes about 2200 times. In the case of a microprocessor having a scale of hundreds of thousands of elements, the leak current is 10% or less as compared with the current during operation, and the power consumption does not increase so much.
However, the current consumption in the standby mode in which only the clock is stopped as in the conventional example is exactly due to this leak current. Therefore, if the threshold value is reduced from 0.5V to 0.3V, the leak current directly increases by 2200 times. .. Therefore, when the threshold voltage is lowered, stopping the clock is not sufficient to reduce the current consumption, and the battery backup time in the standby mode is significantly shortened.

The present invention was made on the basis of the results of the study by the present inventors as described above. The purpose of the present invention is to enable high-speed operation even at a low power supply voltage during operation, and in the standby mode. An object is to provide an information processing device that consumes less power due to a leak current.

[0009]

The above-mentioned problem is caused by the low threshold value of the MOS transistor even in the standby mode in which the switching operation is not performed.

Therefore, if the threshold value is lowered during operation to enable high-speed operation even at a low power supply voltage, and the threshold value is increased during standby mode to reduce leakage current, high-speed operability during operation at a low power supply voltage is achieved. It is possible to achieve both low power consumption and standby mode. Therefore, the threshold value of the MOS transistor itself is set low, and the threshold value is raised by applying the substrate bias in the standby mode.

Needless to say, the substrate bias at this time needs to be set so that the amount of reduction of the leak current due to the rise of the threshold value is larger than the current consumption of the substrate bias circuit.

[0012]

Since the threshold value is low during operation, high-speed operation is possible even at low voltage, while the threshold voltage is high during standby mode, so that leakage current can be greatly reduced.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows a typical embodiment of the present invention, and the basic concept thereof will be described. First, in order to maintain high-speed operation with a low power supply voltage, MOS transistors (MN, MP)
Threshold is set low. On the other hand, when there is no keyboard input for a certain time or more, or when the state of the minimum power consumption continues for a certain time or more, it is determined that the standby mode is entered by a program command or an external control signal.

In the standby mode, the clock control circuit 3 stops the clock Ckm supplied to the MPU (microprocessor unit) 1, and at the same time, the operation mode switching signal A
To activate the substrate bias circuits 2-1 and 2-2,
A negative substrate bias V _Bn is applied to the NMOS transistor (MN), and a positive substrate bias V _Bp is applied to the PMOS transistor (MP) rather than the power source. By applying the substrate bias, the threshold of the MOS transistor rises,
The leak current decreases with an exponential function of the threshold rise. That is, when the substrate bias is applied, the subthreshold characteristic is improved and the leak current is reduced. The smaller the number of elements of the microprocessor is, the larger the reduction amount of the leak current is, and the value is equal to or more than the current consumption of the substrate bias circuits 2-1 and 2-2. With the above operation, it is possible to realize an information processing device capable of high-speed operation at a low voltage and low power consumption in the standby mode.

Next, the embodiment of FIG. 1 will be described in detail with reference to the drawings. As shown in FIG. 1, the microprocessor is configured by integrating the MPU 1, the substrate bias circuits 2-1, 2-2, the clock control circuit 3 and the like on one chip. As is well known to those skilled in the art, the MPU 1 is composed of an instruction fetch unit, an instruction decoder, an instruction execution unit and the like. MPU1 is composed of CMOS circuit, NMO
The threshold value of the S transistor is set to 0.3V and the threshold value of the PMOS transistor is set to -0.3V.
High speed operation is possible even when c is a low voltage of 1V.
The power supply voltage Vcc supply terminal of the microprocessor chip is connected to a battery (not shown),
cc is supplied from the battery. In addition, a terminal is exposed on each substrate (or well region) of the NMOS and PMOS of the MPU 1 for applying the substrate bias.

The operation mode switching signal A in response to a program command or an external signal is applied to the substrate bias circuits 2-1 and 2-2 for NMOS and PMOS to control the levels of the substrate biases V _Bp and V _Bn . The mode can be switched depending on the presence / absence of input from the keyboard and the magnitude of current consumption. By controlling the clock control circuit 3 with the operation mode switching signal A and the frequency switching signal B, M
The on / off and frequency of the clock supplied to PU1 are controlled.

FIG. 2 shows changes in clock and substrate bias in each of the normal operation mode, the low power consumption mode and the standby mode.

In the normal operation mode, the high-speed clock of 16 MHz is supplied and the substrate bias is not applied. Therefore, the absolute value of the threshold value of each of the N and P channel MOS transistors remains 0.3V, so that the low power supply voltage V of 1V
High-speed operation is possible even with cc. On the other hand, since the threshold value is low, a steady leakage current due to the subthreshold current flows, but in the case of a 100,000-gate microprocessor, the consumption current due to the steady leakage current is 1/10 of the consumption current due to the switching operation. Since it is below, the current consumption during operation does not change much.

In the low power consumption mode, in order to suppress the power consumption due to switching, the clock control circuit 3 responds to the frequency switching signal B and the clock frequency is divided by 2 to 8 MHz.
z. The substrate bias circuits 2-1 and 2-2 allow the substrate bias V _Bn for NMOS of -0.5 V and +1.5 V.
_Is applied to increase the threshold value of the MOS transistor to an absolute value of about 0.5V. Since the operation speed is slow, there is no problem in operation even if the threshold value is raised. With this low power consumption mode, the switching current can be reduced to 1/2 and the leakage current can be reduced to approximately 1/2200.

Since no operation is performed in the standby mode, the clock is stopped. If the clock is stopped, all switching operations will stop. Further, in order to obtain the threshold value raised in absolute value, the substrate biases V _Bn and V _Bp are similarly applied. Therefore, the consumption current of the CMOS circuit is only a leakage current due to an extremely minute subthreshold current corresponding to a high threshold value. Since the absolute value of the threshold value is increased to about 0.5 V by applying the substrate bias, the leak current can be suppressed to about 1/2200 of that at the time of operation.

Next, an embodiment of the substrate bias circuits 2-1 and 2-2 is shown in FIG. When the operation mode switching signal becomes 1, a clock signal is supplied to the substrate bias circuit and the operation starts. A charge pumping circuit is used to generate a negative voltage for the NMOS and a voltage higher than the power supply voltage for the PMOS. If the power supply voltage Vcc is 1V, for NMOS-
Bias voltages V _Bn and V _{Bp of} about 0.5 V and about +1.5 V for PMOS can be generated. This clock signal is a clock,
A new oscillator circuit is unnecessary because it uses a basic clock that always operates for microprocessors, etc.
The current consumption for applying the substrate bias is about 100 μA. In this embodiment, the substrate bias circuit is provided on the basis of a single power source, but in the case of battery operation, a battery dedicated to the substrate bias may be provided.

Next, an embodiment of the clock control circuit 3 is shown in FIG.
Shown in. As for the basic clock signal, the operation mode switching signal A is 0
Output CK through the clock control circuit 3
m is supplied to MPU1. In the standby mode, the operation mode switching signal becomes 1, and the clock output is not supplied to MPU1. One of the clock inputs enters the frequency dividing circuit by the T flip-flop, and the other passes through the clock frequency switching circuit. When the clock frequency switching signal B is 1, the high-speed clock is supplied to the MPU 1 as it is, and when the clock frequency switching signal B is 0, the low-speed clock for the low power consumption mode divided by 1/2 is supplied.

FIG. 5 shows an embodiment of an element structure for applying a substrate bias to a CMOS transistor. Normal C
It is possible to apply a bias without grounding the substrate even in the MOS structure, but the packaging becomes complicated,
There is a problem that it is easy to pick up noise. In order to apply substrate biases V _Bn and V _Bp to both N and P channel MOS transistors with the P type semiconductor substrate 1 grounded, an N channel M
The substrate p well 3 of the OS is insulated from the substrate 1 by the substrate n epitaxial layer 2 of the P channel MOS. A negative voltage is applied to the p well 3 through the substrate bias terminal 5-1 as the NMOS substrate bias V _Bn , and a positive voltage is applied to the n epitaxial layer 2 through the substrate bias terminal 5-2 as the PMOS substrate bias V _Bp. , All bias relationships are reverse bias of the pn junction, so they are insulated from each other.

Since the substrate bias voltage that can be generated at a low power supply voltage is also low, the device structure is devised. The p-type high-concentration region 7 and P immediately below the gate electrode of the N-channel MOS
The n-type high concentration region 8 just below the gate electrode of the channel MOS is provided at a position deeper than the thickness of the surface depletion layer at the time of forming the channel inversion layer. Therefore, the threshold value is not affected when the substrate bias is not applied. When the substrate bias is applied, the depletion layer spreads to the high concentration regions 7 and 8,
Since the effective substrate concentration is high, the threshold value largely changes due to the substrate bias. The amount of change in the substrate bias and the threshold value is shown in FIG. The surface concentration of the p-type well 3 is 5 × 10 ¹⁶ /
The concentration of cm ³ and the p-type high concentration region 7 is 3 × 10 ¹⁷ / cm ³ . When the p-type high-concentration region 7 is not provided, the substrate constant is small, and therefore the threshold value does not change much even when the substrate bias is applied, and the control width of the threshold value is too small at low power supply voltage.
By providing the p-type high concentration region 7, the substrate constant is doubled or more, and the threshold value can be largely controlled.
By applying a substrate bias of 0.5 V, the threshold value is reduced to about 0.5.
Can be increased by 2V.

Next, as another embodiment of the present invention, FIG. 7 shows a basic configuration in which the substrate bias is automatically switched according to the clock frequency. The substrate bias control circuit 2-0 detects a change in the frequency of the clock signal, and the substrate bias circuit 2-
The values of the substrate biases V _Bn and V _Bp generated from 1 and 2-2 are switched. As a result, the substrate bias can be switched between the normal mode, the low power consumption mode, and the standby mode using only the clock signal.

An embodiment of the substrate bias control circuit 2-0 is shown in FIG. A charge pump circuit generates a voltage Vc from a clock signal. The value of Vc is proportional to the frequency of the clock and can be adjusted by the coupling capacitance _Cc and the load resistance _Rb . Vc when the clock frequency is high
Is high and the signal at the point a is low level because the MOS transistor MN1 is in the same state, the ring oscillator does not oscillate and the substrate biases V _Bn and V _Bp are not applied. Next, when the clock frequency is low, since the Vc value is low and MN1 does not pass through the same, point a becomes a high level and the ring oscillator oscillates to apply the substrate biases V _Bn and V _Bp .
Of course, when the clock signal is stopped, the point a becomes high, and the substrate biases V _Bn and V _Bp are applied. In this embodiment, since the ring oscillator is oscillated to generate the substrate bias, the power consumption in the standby mode is as large as about 300 μA, but it is effective because the reduction amount of the leak current is larger. Further, since the substrate biases V _Bn and V _Bp automatically change according to the clock frequency, it is not necessary to provide a specific command or control signal.

FIG. 9 shows a change in drain current characteristic of a MOS transistor according to a threshold value. The leak current is a drain current when the gate voltage is 0V. Threshold
Leak current is 44 when increasing from 0.3V to 0.5V.
It decreases from nA to about 1/200. Considering that a microprocessor is composed of MOS transistors having a threshold voltage of 0.3 V and a leak current of 44 nA, when the number of gates of the microprocessor is about 100,000, the leak current is 4. 4 mA
Reach When a substrate bias of 0.5 V is applied, the threshold value rises to 0.5 V, and the leak current decreases to about 20 pA, which is almost the same as the original transistor having a threshold value of 0.5 V. On the other hand, the current consumption of the substrate bias circuit is 1
Since it is about 00 μA, the total current consumption is 102 μA. FIG. 10 shows a summary of comparison between the conventional example and the present example having threshold values of 0.5 V and 0.3 V with respect to the maximum operating frequency and current consumption of the microprocessor.

[0029]

According to the present invention, since the threshold voltage can be set low, high-speed operation is possible even with a low power supply voltage, and a substrate bias is applied to increase the threshold voltage during low-speed operation or standby mode. Therefore, the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 shows a waveform change of each part in each mode of the semiconductor integrated circuit of FIG.

FIG. 3 shows an embodiment of a substrate bias circuit of the semiconductor integrated circuit of FIG.

FIG. 4 shows an embodiment of a clock control circuit of the semiconductor integrated circuit of FIG.

5 shows a cross-sectional view of the CMOS structure of the semiconductor integrated circuit of FIG.

FIG. 6 shows the relationship between the substrate bias and the threshold voltage of a MOS transistor.

FIG. 7 is a block diagram of a semiconductor integrated circuit according to another embodiment of the present invention.

8 shows an embodiment of the substrate bias control circuit and the substrate bias circuit of FIG.

FIG. 9 shows a relationship between an N-channel MOS transistor, a threshold voltage and a leak current.

FIG. 10 is a table showing a comparison between the conventional art and the present invention regarding the maximum operating frequency and the current consumption of the microprocessor.

[Explanation of symbols]

V _Bn ... N-channel MOS substrate bias, V _Bp ... P-channel MOS substrate bias, CKm ... Microprocessor clock signal, CKb ... Substrate bias generation clock signal.

Front page continuation (72) Inventor Koichi Seki 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (6)

[Claims] 1. A MOS transistor circuit and a control circuit for controlling a threshold voltage of a MOS transistor of the MOS transistor circuit. In the first operation mode, the control circuit is a MOS transistor circuit of the MOS transistor circuit. By setting the threshold voltage low, the above-mentioned MOS
The transistor circuit executes a high speed operation, and in the second operation mode, the control circuit controls the MO transistor of the MOS transistor circuit.
A semiconductor integrated circuit characterized by reducing the power consumption of the MOS transistor circuit by setting a high threshold voltage of the S transistor. 2. The threshold voltage is set by the difference in the substrate bias supplied from the control circuit to the MOS transistor between the first operation mode and the second operation mode. 1. The semiconductor integrated circuit according to 1. 3. A clock having a predetermined frequency is supplied to the MOS circuit in the first operation mode, and a frequency lower than the predetermined frequency is supplied to the MOS circuit in the second operation mode. Item 2. The semiconductor integrated circuit according to item 2. 4. The clock of a predetermined frequency is supplied to the MOS circuit in the first operation mode, and the supply of the clock to the MOS circuit is stopped in the second operation mode. Semiconductor integrated circuit. 5. The semiconductor integrated circuit according to any one of claims 1 to 4, wherein the MOS circuit is a microprocessor unit. 6. The power supply voltage supply terminal of the semiconductor integrated circuit is connected to a battery, and the power supply voltage of the MOS circuit is supplied from the battery. The semiconductor integrated circuit according to any one of claims.